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GET /api/patches/5988/?format=api
{ "id": 5988, "url": "https://patches.dpdk.org/api/patches/5988/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1435656489-27986-21-git-send-email-adrien.mazarguil@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1435656489-27986-21-git-send-email-adrien.mazarguil@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1435656489-27986-21-git-send-email-adrien.mazarguil@6wind.com", "date": "2015-06-30T09:28:06", "name": "[dpdk-dev,v2,20/23] mlx4: add L2 tunnel (VXLAN) checksum offload support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bd39fd89001acfee38e4cf338517bbd07e347be5", "submitter": { "id": 165, "url": "https://patches.dpdk.org/api/people/165/?format=api", "name": "Adrien Mazarguil", "email": "adrien.mazarguil@6wind.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1435656489-27986-21-git-send-email-adrien.mazarguil@6wind.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/5988/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/5988/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id E4C54C4FE;\n\tTue, 30 Jun 2015 11:29:43 +0200 (CEST)", "from mail-wi0-f176.google.com (mail-wi0-f176.google.com\n\t[209.85.212.176]) by dpdk.org (Postfix) with ESMTP id 346F2C43E\n\tfor <dev@dpdk.org>; Tue, 30 Jun 2015 11:29:18 +0200 (CEST)", "by widjy10 with SMTP id jy10so24874406wid.1\n\tfor <dev@dpdk.org>; Tue, 30 Jun 2015 02:29:18 -0700 (PDT)", "from 6wind.com (6wind.net2.nerim.net. [213.41.151.210])\n\tby mx.google.com with ESMTPSA id\n\tho10sm12317310wjb.39.2015.06.30.02.29.16\n\t(version=TLSv1.2 cipher=RC4-SHA bits=128/128);\n\tTue, 30 Jun 2015 02:29:17 -0700 (PDT)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=qSp/muR5EffDVy4nTHdjSgACyVQREy0G/gExc0H4odk=;\n\tb=bR6pF6tDcbZwZH2ga14oWpgvXxEaKbM191/JyxA2giAZrVod0QkQtGOiUwBc2dVNdw\n\tVM26Cc3lQoUIIgCpelW7BcjGAvn4D8kZ2dD4scLHn5br6cmLpheZ31dUkuBkzZ9a8gPE\n\thGt2sdjUdWeeRrSuzLbuWVWEOkcoQbEFqgxrEp6vXwyNJTXyq5J44M9mu+Bx8S0n3xOG\n\tdqkJOzA2AjQHp/Bt9T4oN41+cUMyXAWKxAiPbFkFh3lyFptP8VYplKYgB19jYwSdFeCN\n\tyKW2C9eP121sGJDnTh+VX7Ut/qP9PcMWfxAVc5H/czfTZTEvmhwGX+2DAm23e8a0ZAnd\n\tDK7Q==", "X-Gm-Message-State": "ALoCoQmN1rfXPGube5jlm+Dgq1znS0eh9Ij2hQRl0/ZsblS1IIeQG6mgU3Icm/GTLVJxurU22QQm", "X-Received": "by 10.194.5.74 with SMTP id q10mr36172184wjq.27.1435656558102;\n\tTue, 30 Jun 2015 02:29:18 -0700 (PDT)", "From": "Adrien Mazarguil <adrien.mazarguil@6wind.com>", "To": "dev@dpdk.org", "Date": "Tue, 30 Jun 2015 11:28:06 +0200", "Message-Id": "<1435656489-27986-21-git-send-email-adrien.mazarguil@6wind.com>", "X-Mailer": "git-send-email 2.1.0", "In-Reply-To": "<1435656489-27986-1-git-send-email-adrien.mazarguil@6wind.com>", "References": "<1433546120-2254-1-git-send-email-adrien.mazarguil@6wind.com>\n\t<1435656489-27986-1-git-send-email-adrien.mazarguil@6wind.com>", "Subject": "[dpdk-dev] [PATCH v2 20/23] mlx4: add L2 tunnel (VXLAN) checksum\n\toffload support", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Depending on adapters features and VXLAN support in the kernel, VXLAN frames\ncan be automatically recognized, in which case checksum validation and\ngeneration occurs on inner and outer L3 and L4.\n\nSigned-off-by: Olga Shern <olgas@mellanox.com>\nSigned-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>\n---\n drivers/net/mlx4/mlx4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 48 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c\nindex fa9216f..3c72235 100644\n--- a/drivers/net/mlx4/mlx4.c\n+++ b/drivers/net/mlx4/mlx4.c\n@@ -203,6 +203,7 @@ struct rxq {\n \t} elts;\n \tunsigned int sp:1; /* Use scattered RX elements. */\n \tunsigned int csum:1; /* Enable checksum offloading. */\n+\tunsigned int csum_l2tun:1; /* Same for L2 tunnels. */\n \tuint32_t mb_len; /* Length of a mp-issued mbuf. */\n \tstruct mlx4_rxq_stats stats; /* RX queue counters. */\n \tunsigned int socket; /* CPU socket ID for allocations. */\n@@ -276,6 +277,7 @@ struct priv {\n \tunsigned int hw_tss:1; /* TSS is supported. */\n \tunsigned int hw_rss:1; /* RSS is supported. */\n \tunsigned int hw_csum:1; /* Checksum offload is supported. */\n+\tunsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */\n \tunsigned int rss:1; /* RSS is enabled. */\n \tunsigned int vf:1; /* This is a VF device. */\n #ifdef INLINE_RECV\n@@ -1243,8 +1245,21 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)\n \t\t}\n \t\t/* Should we enable HW CKSUM offload */\n \t\tif (buf->ol_flags &\n-\t\t (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))\n+\t\t (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {\n \t\t\tsend_flags |= IBV_EXP_QP_BURST_IP_CSUM;\n+\t\t\t/* HW does not support checksum offloads at arbitrary\n+\t\t\t * offsets but automatically recognizes the packet\n+\t\t\t * type. For inner L3/L4 checksums, only VXLAN (UDP)\n+\t\t\t * tunnels are currently supported.\n+\t\t\t *\n+\t\t\t * FIXME: since PKT_TX_UDP_TUNNEL_PKT has been removed,\n+\t\t\t * the outer packet type is unknown. All we know is\n+\t\t\t * that the L2 header is of unusual length (not\n+\t\t\t * ETHER_HDR_LEN with or without 802.1Q header). */\n+\t\t\tif ((buf->l2_len != ETHER_HDR_LEN) &&\n+\t\t\t (buf->l2_len != (ETHER_HDR_LEN + 4)))\n+\t\t\t\tsend_flags |= IBV_EXP_QP_BURST_TUNNEL;\n+\t\t}\n \t\tif (likely(segs == 1)) {\n \t\t\tuintptr_t addr;\n \t\t\tuint32_t length;\n@@ -2443,6 +2458,25 @@ rxq_cq_to_ol_flags(const struct rxq *rxq, uint32_t flags)\n \t\t\tTRANSPOSE(~flags,\n \t\t\t\t IBV_EXP_CQ_RX_TCP_UDP_CSUM_OK,\n \t\t\t\t PKT_RX_L4_CKSUM_BAD);\n+\t/*\n+\t * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place\n+\t * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional\n+\t * (its value is 0).\n+\t */\n+\tif ((flags & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))\n+\t\tol_flags |=\n+\t\t\tTRANSPOSE(flags,\n+\t\t\t\t IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,\n+\t\t\t\t PKT_RX_TUNNEL_IPV4_HDR) |\n+\t\t\tTRANSPOSE(flags,\n+\t\t\t\t IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,\n+\t\t\t\t PKT_RX_TUNNEL_IPV6_HDR) |\n+\t\t\tTRANSPOSE(~flags,\n+\t\t\t\t IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,\n+\t\t\t\t PKT_RX_IP_CKSUM_BAD) |\n+\t\t\tTRANSPOSE(~flags,\n+\t\t\t\t IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,\n+\t\t\t\t PKT_RX_L4_CKSUM_BAD);\n \treturn ol_flags;\n }\n \n@@ -2976,6 +3010,10 @@ rxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq)\n \t\ttmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n \t\trxq->csum = tmpl.csum;\n \t}\n+\tif (priv->hw_csum_l2tun) {\n+\t\ttmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n+\t\trxq->csum_l2tun = tmpl.csum_l2tun;\n+\t}\n \t/* Enable scattered packets support for this queue if necessary. */\n \tif ((dev->data->dev_conf.rxmode.jumbo_frame) &&\n \t (dev->data->dev_conf.rxmode.max_rx_pkt_len >\n@@ -3200,6 +3238,8 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,\n \t/* Toggle RX checksum offload if hardware supports it. */\n \tif (priv->hw_csum)\n \t\ttmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n+\tif (priv->hw_csum_l2tun)\n+\t\ttmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;\n \t/* Enable scattered packets support for this queue if necessary. */\n \tif ((dev->data->dev_conf.rxmode.jumbo_frame) &&\n \t (dev->data->dev_conf.rxmode.max_rx_pkt_len >\n@@ -4427,6 +4467,8 @@ static const struct eth_dev_ops mlx4_dev_ops = {\n \t.mac_addr_remove = mlx4_mac_addr_remove,\n \t.mac_addr_add = mlx4_mac_addr_add,\n \t.mtu_set = mlx4_dev_set_mtu,\n+\t.udp_tunnel_add = NULL,\n+\t.udp_tunnel_del = NULL,\n \t.fdir_add_signature_filter = NULL,\n \t.fdir_update_signature_filter = NULL,\n \t.fdir_remove_signature_filter = NULL,\n@@ -4757,6 +4799,11 @@ mlx4_pci_devinit(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n \t\tDEBUG(\"checksum offloading is %ssupported\",\n \t\t (priv->hw_csum ? \"\" : \"not \"));\n \n+\t\tpriv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &\n+\t\t\t\t\t IBV_EXP_DEVICE_VXLAN_SUPPORT);\n+\t\tDEBUG(\"L2 tunnel checksum offloads are %ssupported\",\n+\t\t (priv->hw_csum_l2tun ? \"\" : \"not \"));\n+\n #ifdef INLINE_RECV\n \t\tpriv->inl_recv_size = mlx4_getenv_int(\"MLX4_INLINE_RECV_SIZE\");\n \n", "prefixes": [ "dpdk-dev", "v2", "20/23" ] }