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{ "id": 59878, "url": "https://patches.dpdk.org/api/patches/59878/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190926123609.28417-7-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190926123609.28417-7-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190926123609.28417-7-rnagadheeraj@marvell.com", "date": "2019-09-26T12:36:57", "name": "[v5,6/8] crypto/nitrox: add burst enqueue and dequeue operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e8075c88152038d4e0d21ccacc7de73a020ba9d5", "submitter": { "id": 1365, "url": "https://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190926123609.28417-7-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 6550, "url": "https://patches.dpdk.org/api/series/6550/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6550", "date": "2019-09-26T12:36:45", "name": "add Nitrox crypto device support", "version": 5, "mbox": "https://patches.dpdk.org/series/6550/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59878/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59878/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost 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"eMstlxDvLatXJDmXmdt1bJNOdtS169pYrWtDfyxuZKd3Vg2zFBJEFXrctiDEFMyGJxsgheGhy/QrnlwUeEikH6B2uZ670ez4WiuKXDPox/8=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB2766", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.95,1.0.8\n\tdefinitions=2019-09-26_06:2019-09-25,2019-09-26 signatures=0", "Subject": "[dpdk-dev] [PATCH v5 6/8] crypto/nitrox: add burst enqueue and\n\tdequeue operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add burst enqueue and dequeue operations along with interface for\nsymmetric request manager.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n drivers/crypto/nitrox/nitrox_qp.h | 60 +++++++++++\n drivers/crypto/nitrox/nitrox_sym.c | 126 +++++++++++++++++++++-\n drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 174 ++++++++++++++++++++++++++++++\n drivers/crypto/nitrox/nitrox_sym_reqmgr.h | 10 ++\n 4 files changed, 368 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/nitrox_qp.h\nindex 0244c4dbf..e8c564cb1 100644\n--- a/drivers/crypto/nitrox/nitrox_qp.h\n+++ b/drivers/crypto/nitrox/nitrox_qp.h\n@@ -34,12 +34,72 @@ struct nitrox_qp {\n \trte_atomic16_t pending_count;\n };\n \n+static inline uint16_t\n+nitrox_qp_free_count(struct nitrox_qp *qp)\n+{\n+\tuint16_t pending_count = rte_atomic16_read(&qp->pending_count);\n+\n+\tRTE_ASSERT(qp->count >= pending_count);\n+\treturn (qp->count - pending_count);\n+}\n+\n static inline bool\n nitrox_qp_is_empty(struct nitrox_qp *qp)\n {\n \treturn (rte_atomic16_read(&qp->pending_count) == 0);\n }\n \n+static inline uint16_t\n+nitrox_qp_used_count(struct nitrox_qp *qp)\n+{\n+\treturn rte_atomic16_read(&qp->pending_count);\n+}\n+\n+static inline struct nitrox_softreq *\n+nitrox_qp_get_softreq(struct nitrox_qp *qp)\n+{\n+\tuint32_t tail = qp->tail % qp->count;\n+\n+\treturn qp->ridq[tail].sr;\n+}\n+\n+static inline void\n+nitrox_ring_dbell(struct nitrox_qp *qp, uint16_t cnt)\n+{\n+\tstruct command_queue *cmdq = &qp->cmdq;\n+\n+\tif (!cnt)\n+\t\treturn;\n+\n+\trte_write64(cnt, cmdq->dbell_csr_addr);\n+}\n+\n+static inline void\n+nitrox_qp_enqueue(struct nitrox_qp *qp, void *instr, struct nitrox_softreq *sr)\n+{\n+\tuint32_t head = qp->head % qp->count;\n+\n+\tqp->head++;\n+\tmemcpy(&qp->cmdq.ring[head * qp->cmdq.instr_size],\n+\t instr, qp->cmdq.instr_size);\n+\tqp->ridq[head].sr = sr;\n+\trte_wmb();\n+\trte_atomic16_inc(&qp->pending_count);\n+\trte_wmb();\n+}\n+\n+static inline void\n+nitrox_qp_dequeue(struct nitrox_qp *qp)\n+{\n+\tuint32_t tail = qp->tail % qp->count;\n+\n+\tqp->tail++;\n+\tqp->ridq[tail].sr = NULL;\n+\trte_wmb();\n+\trte_atomic16_dec(&qp->pending_count);\n+\trte_wmb();\n+}\n+\n int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr,\n \t\t const char *dev_name, uint32_t nb_descriptors,\n \t\t uint8_t inst_size, int socket_id);\ndiff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nitrox_sym.c\nindex c7d3b8d49..0ca15f847 100644\n--- a/drivers/crypto/nitrox/nitrox_sym.c\n+++ b/drivers/crypto/nitrox/nitrox_sym.c\n@@ -539,6 +539,128 @@ nitrox_sym_dev_sess_clear(struct rte_cryptodev *cdev,\n \trte_mempool_put(sess_mp, ctx);\n }\n \n+static struct nitrox_crypto_ctx *\n+get_crypto_ctx(struct rte_crypto_op *op)\n+{\n+\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {\n+\t\tif (likely(op->sym->session))\n+\t\t\treturn get_sym_session_private_data(op->sym->session,\n+\t\t\t\t\t\t\t nitrox_sym_drv_id);\n+\t}\n+\n+\treturn NULL;\n+}\n+\n+static int\n+nitrox_enq_single_op(struct nitrox_qp *qp, struct rte_crypto_op *op)\n+{\n+\tstruct nitrox_crypto_ctx *ctx;\n+\tstruct nitrox_softreq *sr;\n+\tint err;\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\tctx = get_crypto_ctx(op);\n+\tif (unlikely(!ctx)) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (unlikely(rte_mempool_get(qp->sr_mp, (void **)&sr)))\n+\t\treturn -ENOMEM;\n+\n+\terr = nitrox_process_se_req(qp->qno, op, ctx, sr);\n+\tif (unlikely(err)) {\n+\t\trte_mempool_put(qp->sr_mp, sr);\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\treturn err;\n+\t}\n+\n+\tnitrox_qp_enqueue(qp, nitrox_sym_instr_addr(sr), sr);\n+\treturn 0;\n+}\n+\n+static uint16_t\n+nitrox_sym_dev_enq_burst(void *queue_pair, struct rte_crypto_op **ops,\n+\t\t\t uint16_t nb_ops)\n+{\n+\tstruct nitrox_qp *qp = queue_pair;\n+\tuint16_t free_slots = 0;\n+\tuint16_t cnt = 0;\n+\tbool err = false;\n+\n+\tfree_slots = nitrox_qp_free_count(qp);\n+\tif (nb_ops > free_slots)\n+\t\tnb_ops = free_slots;\n+\n+\tfor (cnt = 0; cnt < nb_ops; cnt++) {\n+\t\tif (unlikely(nitrox_enq_single_op(qp, ops[cnt]))) {\n+\t\t\terr = true;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\tnitrox_ring_dbell(qp, cnt);\n+\tqp->stats.enqueued_count += cnt;\n+\tif (unlikely(err))\n+\t\tqp->stats.enqueue_err_count++;\n+\n+\treturn cnt;\n+}\n+\n+static int\n+nitrox_deq_single_op(struct nitrox_qp *qp, struct rte_crypto_op **op_ptr)\n+{\n+\tstruct nitrox_softreq *sr;\n+\tint ret;\n+\tstruct rte_crypto_op *op;\n+\n+\tsr = nitrox_qp_get_softreq(qp);\n+\tif (unlikely(!sr)) {\n+\t\tNITROX_LOG(ERR, \"Invalid softreq\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = nitrox_check_se_req(sr, op_ptr);\n+\tif (ret < 0)\n+\t\treturn -EAGAIN;\n+\n+\top = *op_ptr;\n+\tnitrox_qp_dequeue(qp);\n+\trte_mempool_put(qp->sr_mp, sr);\n+\tif (!ret) {\n+\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t\tqp->stats.dequeued_count++;\n+\n+\t\treturn 0;\n+\t}\n+\n+\tif (ret == MC_MAC_MISMATCH_ERR_CODE)\n+\t\top->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\telse\n+\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\n+\tqp->stats.dequeue_err_count++;\n+\treturn 0;\n+}\n+\n+static uint16_t\n+nitrox_sym_dev_deq_burst(void *queue_pair, struct rte_crypto_op **ops,\n+\t\t\t uint16_t nb_ops)\n+{\n+\tstruct nitrox_qp *qp = queue_pair;\n+\tuint16_t filled_slots = nitrox_qp_used_count(qp);\n+\tint cnt = 0;\n+\n+\tif (nb_ops > filled_slots)\n+\t\tnb_ops = filled_slots;\n+\n+\tfor (cnt = 0; cnt < nb_ops; cnt++)\n+\t\tif (nitrox_deq_single_op(qp, &ops[cnt]))\n+\t\t\tbreak;\n+\n+\treturn cnt;\n+}\n+\n static struct rte_cryptodev_ops nitrox_cryptodev_ops = {\n \t.dev_configure\t\t= nitrox_sym_dev_config,\n \t.dev_start\t\t= nitrox_sym_dev_start,\n@@ -580,8 +702,8 @@ nitrox_sym_pmd_create(struct nitrox_device *ndev)\n \tndev->rte_sym_dev.name = cdev->data->name;\n \tcdev->driver_id = nitrox_sym_drv_id;\n \tcdev->dev_ops = &nitrox_cryptodev_ops;\n-\tcdev->enqueue_burst = NULL;\n-\tcdev->dequeue_burst = NULL;\n+\tcdev->enqueue_burst = nitrox_sym_dev_enq_burst;\n+\tcdev->dequeue_burst = nitrox_sym_dev_deq_burst;\n \tcdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n \t\tRTE_CRYPTODEV_FF_HW_ACCELERATED |\n \t\tRTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING;\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\nindex 42d67317c..a37b754f2 100644\n--- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c\n@@ -4,12 +4,113 @@\n \n #include <rte_crypto.h>\n #include <rte_cryptodev.h>\n+#include <rte_cycles.h>\n #include <rte_errno.h>\n \n #include \"nitrox_sym_reqmgr.h\"\n #include \"nitrox_logs.h\"\n \n+#define PENDING_SIG 0xFFFFFFFFFFFFFFFFUL\n+#define CMD_TIMEOUT 2\n+\n+union pkt_instr_hdr {\n+\tuint64_t value;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz_48_63 : 16;\n+\t\tuint64_t g : 1;\n+\t\tuint64_t gsz : 7;\n+\t\tuint64_t ihi : 1;\n+\t\tuint64_t ssz : 7;\n+\t\tuint64_t raz_30_31 : 2;\n+\t\tuint64_t fsz : 6;\n+\t\tuint64_t raz_16_23 : 8;\n+\t\tuint64_t tlen : 16;\n+#else\n+\t\tuint64_t tlen : 16;\n+\t\tuint64_t raz_16_23 : 8;\n+\t\tuint64_t fsz : 6;\n+\t\tuint64_t raz_30_31 : 2;\n+\t\tuint64_t ssz : 7;\n+\t\tuint64_t ihi : 1;\n+\t\tuint64_t gsz : 7;\n+\t\tuint64_t g : 1;\n+\t\tuint64_t raz_48_63 : 16;\n+#endif\n+\t} s;\n+};\n+\n+union pkt_hdr {\n+\tuint64_t value[2];\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t opcode : 8;\n+\t\tuint64_t arg : 8;\n+\t\tuint64_t ctxc : 2;\n+\t\tuint64_t unca : 1;\n+\t\tuint64_t raz_44 : 1;\n+\t\tuint64_t info : 3;\n+\t\tuint64_t destport : 9;\n+\t\tuint64_t unc : 8;\n+\t\tuint64_t raz_19_23 : 5;\n+\t\tuint64_t grp : 3;\n+\t\tuint64_t raz_15 : 1;\n+\t\tuint64_t ctxl : 7;\n+\t\tuint64_t uddl : 8;\n+#else\n+\t\tuint64_t uddl : 8;\n+\t\tuint64_t ctxl : 7;\n+\t\tuint64_t raz_15 : 1;\n+\t\tuint64_t grp : 3;\n+\t\tuint64_t raz_19_23 : 5;\n+\t\tuint64_t unc : 8;\n+\t\tuint64_t destport : 9;\n+\t\tuint64_t info : 3;\n+\t\tuint64_t raz_44 : 1;\n+\t\tuint64_t unca : 1;\n+\t\tuint64_t ctxc : 2;\n+\t\tuint64_t arg : 8;\n+\t\tuint64_t opcode : 8;\n+#endif\n+\t\tuint64_t ctxp;\n+\t} s;\n+};\n+\n+union slc_store_info {\n+\tuint64_t value[2];\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz_39_63 : 25;\n+\t\tuint64_t ssz : 7;\n+\t\tuint64_t raz_0_31 : 32;\n+#else\n+\t\tuint64_t raz_0_31 : 32;\n+\t\tuint64_t ssz : 7;\n+\t\tuint64_t raz_39_63 : 25;\n+#endif\n+\t\tuint64_t rptr;\n+\t} s;\n+};\n+\n+struct nps_pkt_instr {\n+\tuint64_t dptr0;\n+\tunion pkt_instr_hdr ih;\n+\tunion pkt_hdr irh;\n+\tunion slc_store_info slc;\n+\tuint64_t fdata[2];\n+};\n+\n+struct resp_hdr {\n+\tuint64_t orh;\n+\tuint64_t completion;\n+};\n+\n struct nitrox_softreq {\n+\tstruct nitrox_crypto_ctx *ctx;\n+\tstruct rte_crypto_op *op;\n+\tstruct nps_pkt_instr instr;\n+\tstruct resp_hdr resp;\n+\tuint64_t timeout;\n \trte_iova_t iova;\n };\n \n@@ -20,6 +121,79 @@ softreq_init(struct nitrox_softreq *sr, rte_iova_t iova)\n \tsr->iova = iova;\n }\n \n+static int\n+process_cipher_auth_data(struct nitrox_softreq *sr)\n+{\n+\tRTE_SET_USED(sr);\n+\treturn 0;\n+}\n+\n+static int\n+process_softreq(struct nitrox_softreq *sr)\n+{\n+\tstruct nitrox_crypto_ctx *ctx = sr->ctx;\n+\tint err = 0;\n+\n+\tswitch (ctx->nitrox_chain) {\n+\tcase NITROX_CHAIN_CIPHER_AUTH:\n+\tcase NITROX_CHAIN_AUTH_CIPHER:\n+\t\terr = process_cipher_auth_data(sr);\n+\t\tbreak;\n+\tdefault:\n+\t\terr = -EINVAL;\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+int\n+nitrox_process_se_req(uint16_t qno, struct rte_crypto_op *op,\n+\t\t struct nitrox_crypto_ctx *ctx,\n+\t\t struct nitrox_softreq *sr)\n+{\n+\tRTE_SET_USED(qno);\n+\tsoftreq_init(sr, sr->iova);\n+\tsr->ctx = ctx;\n+\tsr->op = op;\n+\tprocess_softreq(sr);\n+\tsr->timeout = rte_get_timer_cycles() + CMD_TIMEOUT * rte_get_timer_hz();\n+\treturn 0;\n+}\n+\n+int\n+nitrox_check_se_req(struct nitrox_softreq *sr, struct rte_crypto_op **op)\n+{\n+\tuint64_t cc;\n+\tuint64_t orh;\n+\tint err;\n+\n+\trte_rmb();\n+\tcc = *(volatile uint64_t *)(&sr->resp.completion);\n+\torh = *(volatile uint64_t *)(&sr->resp.orh);\n+\tif (cc != PENDING_SIG)\n+\t\terr = 0;\n+\telse if ((orh != PENDING_SIG) && (orh & 0xff))\n+\t\terr = orh & 0xff;\n+\telse if (rte_get_timer_cycles() >= sr->timeout)\n+\t\terr = 0xff;\n+\telse\n+\t\treturn -EAGAIN;\n+\n+\tif (unlikely(err))\n+\t\tNITROX_LOG(ERR, \"Request err 0x%x, orh 0x%\"PRIx64\"\\n\", err,\n+\t\t\t sr->resp.orh);\n+\n+\t*op = sr->op;\n+\treturn err;\n+}\n+\n+void *\n+nitrox_sym_instr_addr(struct nitrox_softreq *sr)\n+{\n+\treturn &sr->instr;\n+}\n+\n static void\n req_pool_obj_init(__rte_unused struct rte_mempool *mp,\n \t\t __rte_unused void *opaque, void *obj,\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h\nindex 5953c958c..fa2637bdb 100644\n--- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h\n+++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h\n@@ -5,6 +5,16 @@\n #ifndef _NITROX_SYM_REQMGR_H_\n #define _NITROX_SYM_REQMGR_H_\n \n+#include \"nitrox_sym_ctx.h\"\n+\n+struct nitrox_qp;\n+struct nitrox_softreq;\n+\n+int nitrox_process_se_req(uint16_t qno, struct rte_crypto_op *op,\n+\t\t\t struct nitrox_crypto_ctx *ctx,\n+\t\t\t struct nitrox_softreq *sr);\n+int nitrox_check_se_req(struct nitrox_softreq *sr, struct rte_crypto_op **op);\n+void *nitrox_sym_instr_addr(struct nitrox_softreq *sr);\n struct rte_mempool *nitrox_sym_req_pool_create(struct rte_cryptodev *cdev,\n \t\t\t\t\t uint32_t nobjs, uint16_t qp_id,\n \t\t\t\t\t int socket_id);\n", "prefixes": [ "v5", "6/8" ] }