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GET /api/patches/59611/?format=api
{ "id": 59611, "url": "https://patches.dpdk.org/api/patches/59611/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190920200628.6444-2-adamx.dybkowski@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190920200628.6444-2-adamx.dybkowski@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190920200628.6444-2-adamx.dybkowski@intel.com", "date": "2019-09-20T20:06:26", "name": "[v3,1/3] common/qat: add QAT RAM bank definitions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6c4cb35252f476331ebf9211e14370eed3d65f2e", "submitter": { "id": 1322, "url": "https://patches.dpdk.org/api/people/1322/?format=api", "name": "Dybkowski, AdamX", "email": "adamx.dybkowski@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190920200628.6444-2-adamx.dybkowski@intel.com/mbox/", "series": [ { "id": 6488, "url": "https://patches.dpdk.org/api/series/6488/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6488", "date": "2019-09-20T20:06:25", "name": "compress/qat: add stateful decompression", "version": 3, "mbox": "https://patches.dpdk.org/series/6488/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59611/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59611/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DF8C21BEF1;\n\tMon, 23 Sep 2019 15:25:31 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 5B9291BEE8\n\tfor <dev@dpdk.org>; Mon, 23 Sep 2019 15:25:28 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Sep 2019 06:25:28 -0700", "from adamdybx-mobl.ger.corp.intel.com (HELO\n\taddy-VirtualBox.isw.intel.com) ([10.103.104.111])\n\tby fmsmga001.fm.intel.com with ESMTP; 23 Sep 2019 06:25:26 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,540,1559545200\"; d=\"scan'208\";a=\"203127078\"", "From": "Adam Dybkowski <adamx.dybkowski@intel.com>", "To": "dev@dpdk.org, fiona.trahe@intel.com, arturx.trybula@intel.com,\n\takhil.goyal@nxp.com", "Cc": "Adam Dybkowski <adamx.dybkowski@intel.com>", "Date": "Fri, 20 Sep 2019 22:06:26 +0200", "Message-Id": "<20190920200628.6444-2-adamx.dybkowski@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190920200628.6444-1-adamx.dybkowski@intel.com>", "References": "<20190920124452.29449-2-adamx.dybkowski@intel.com>\n\t<20190920200628.6444-1-adamx.dybkowski@intel.com>", "Subject": "[dpdk-dev] [PATCH v3 1/3] common/qat: add QAT RAM bank definitions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds QAT RAM bank definitions and related macros.\n\nSigned-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>\n---\n drivers/common/qat/qat_adf/icp_qat_fw_comp.h | 73 ++++++++++++++++++++\n 1 file changed, 73 insertions(+)", "diff": "diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h\nindex 813817720..c89a2c2fd 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_comp.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_comp.h\n@@ -479,4 +479,77 @@ struct icp_qat_fw_comp_resp {\n \t/**< Common response params (checksums and byte counts) */\n };\n \n+/* RAM Bank definitions */\n+#define QAT_FW_COMP_BANK_FLAG_MASK 0x1\n+\n+#define QAT_FW_COMP_BANK_I_BITPOS 8\n+#define QAT_FW_COMP_BANK_H_BITPOS 7\n+#define QAT_FW_COMP_BANK_G_BITPOS 6\n+#define QAT_FW_COMP_BANK_F_BITPOS 5\n+#define QAT_FW_COMP_BANK_E_BITPOS 4\n+#define QAT_FW_COMP_BANK_D_BITPOS 3\n+#define QAT_FW_COMP_BANK_C_BITPOS 2\n+#define QAT_FW_COMP_BANK_B_BITPOS 1\n+#define QAT_FW_COMP_BANK_A_BITPOS 0\n+\n+/**\n+ *****************************************************************************\n+ * @ingroup icp_qat_fw_comp\n+ * Definition of the ram bank enabled values\n+ * @description\n+ * Enumeration used to define whether a ram bank is enabled or not\n+ *\n+ *****************************************************************************/\n+enum icp_qat_fw_comp_bank_enabled {\n+\tICP_QAT_FW_COMP_BANK_DISABLED = 0, /*!< BANK DISABLED */\n+\tICP_QAT_FW_COMP_BANK_ENABLED = 1, /*!< BANK ENABLED */\n+\tICP_QAT_FW_COMP_BANK_DELIMITER = 2 /**< Delimiter type */\n+};\n+\n+/**\n+ ******************************************************************************\n+ * @ingroup icp_qat_fw_comp\n+ *\n+ * @description\n+ * Build the ram bank flags in the compression content descriptor\n+ * which specify which banks are used to save history\n+ *\n+ * @param bank_i_enable\n+ * @param bank_h_enable\n+ * @param bank_g_enable\n+ * @param bank_f_enable\n+ * @param bank_e_enable\n+ * @param bank_d_enable\n+ * @param bank_c_enable\n+ * @param bank_b_enable\n+ * @param bank_a_enable\n+ *****************************************************************************/\n+#define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, \\\n+\t\t\t\t\tbank_h_enable, \\\n+\t\t\t\t\tbank_g_enable, \\\n+\t\t\t\t\tbank_f_enable, \\\n+\t\t\t\t\tbank_e_enable, \\\n+\t\t\t\t\tbank_d_enable, \\\n+\t\t\t\t\tbank_c_enable, \\\n+\t\t\t\t\tbank_b_enable, \\\n+\t\t\t\t\tbank_a_enable) \\\n+\t((((bank_i_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_I_BITPOS) | \\\n+\t(((bank_h_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_H_BITPOS) | \\\n+\t(((bank_g_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_G_BITPOS) | \\\n+\t(((bank_f_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_F_BITPOS) | \\\n+\t(((bank_e_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_E_BITPOS) | \\\n+\t(((bank_d_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_D_BITPOS) | \\\n+\t(((bank_c_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_C_BITPOS) | \\\n+\t(((bank_b_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_B_BITPOS) | \\\n+\t(((bank_a_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \\\n+\t\t<< QAT_FW_COMP_BANK_A_BITPOS))\n+\n #endif\n", "prefixes": [ "v3", "1/3" ] }