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GET /api/patches/59594/?format=api
{ "id": 59594, "url": "https://patches.dpdk.org/api/patches/59594/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190923074448.7847-24-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190923074448.7847-24-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190923074448.7847-24-qi.z.zhang@intel.com", "date": "2019-09-23T07:44:41", "name": "[v5,23/30] net/ice/base: search field vector indices for result slots", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "244cb5a603b44cd2a4e8585d12de0800f6615ed5", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190923074448.7847-24-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6483, "url": "https://patches.dpdk.org/api/series/6483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6483", "date": "2019-09-23T07:44:18", "name": "net/ice/base: share code update secend batch.", "version": 5, "mbox": "https://patches.dpdk.org/series/6483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59594/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59594/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id ED49F1BF07;\n\tMon, 23 Sep 2019 09:43:52 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id 3CA701BE0C\n\tfor <dev@dpdk.org>; Mon, 23 Sep 2019 09:42:39 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Sep 2019 00:42:38 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:36 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,539,1559545200\"; d=\"scan'208\";a=\"182445711\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tDan Nowline <dan.nowlin@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 23 Sep 2019 15:44:41 +0800", "Message-Id": "<20190923074448.7847-24-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190923074448.7847-1-qi.z.zhang@intel.com>", "References": "<20190902035551.16852-1-qi.z.zhang@intel.com>\n\t<20190923074448.7847-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 23/30] net/ice/base: search field vector\n\tindices for result slots", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Previously, switch code would use only pre-reserved index\nslots at the end of each field vector for recipe result index\nlocations. This patch adds code that detects other internal\nempty index slots that could potentially be used. For each\nrecipe that is added, a determ ination is made as to whether\nany of these additional index slots alige with all the profiles\nselected for the recipe; if alignment is achieved, then these\nresult index slots can be used.\n\nSigned-off-by: Dan Nowline <dan.nowlin@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 41 +++++++++++++++++++++\n drivers/net/ice/base/ice_flex_pipe.h | 2 ++\n drivers/net/ice/base/ice_flex_type.h | 2 ++\n drivers/net/ice/base/ice_protocol_type.h | 2 +-\n drivers/net/ice/base/ice_switch.c | 61 +++++++++++++++-----------------\n drivers/net/ice/base/ice_switch.h | 1 -\n drivers/net/ice/base/ice_type.h | 3 ++\n 7 files changed, 78 insertions(+), 34 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 76c26fd4e..318168910 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -1661,6 +1661,47 @@ ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,\n }\n \n /**\n+ * ice_init_profile_to_result_bm - Initialize the profile result index bitmap\n+ * @hw: pointer to hardware structure\n+ */\n+void\n+ice_init_prof_result_bm(struct ice_hw *hw)\n+{\n+\tstruct ice_pkg_enum state;\n+\tstruct ice_seg *ice_seg;\n+\tstruct ice_fv *fv;\n+\n+\tif (!hw->seg)\n+\t\treturn;\n+\n+\tice_seg = hw->seg;\n+\tdo {\n+\t\tu32 off;\n+\t\tu16 i;\n+\n+\t\tfv = (struct ice_fv *)\n+\t\t\tice_pkg_enum_entry(ice_seg, &state, ICE_SID_FLD_VEC_SW,\n+\t\t\t\t\t &off, ice_sw_fv_handler);\n+\t\tice_seg = NULL;\n+\t\tif (!fv)\n+\t\t\tbreak;\n+\n+\t\tice_zero_bitmap(hw->switch_info->prof_res_bm[off],\n+\t\t\t\tICE_MAX_FV_WORDS);\n+\n+\t\t/* Determine empty field vector indices, these can be\n+\t\t * used for recipe results. Skip index 0, since it is\n+\t\t * always used for Switch ID.\n+\t\t */\n+\t\tfor (i = 1; i < ICE_MAX_FV_WORDS; i++)\n+\t\t\tif (fv->ew[i].prot_id == ICE_PROT_INVALID &&\n+\t\t\t fv->ew[i].off == ICE_FV_OFFSET_INVAL)\n+\t\t\t\tice_set_bit(i,\n+\t\t\t\t\t hw->switch_info->prof_res_bm[off]);\n+\t} while (fv);\n+}\n+\n+/**\n * ice_pkg_buf_free\n * @hw: pointer to the HW structure\n * @bld: pointer to pkg build (allocated by ice_pkg_buf_alloc())\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h\nindex 137eaa7f8..e7d42e3de 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.h\n+++ b/drivers/net/ice/base/ice_flex_pipe.h\n@@ -33,6 +33,8 @@ ice_find_label_value(struct ice_seg *ice_seg, char const *name, u32 type,\n void\n ice_get_sw_fv_bitmap(struct ice_hw *hw, enum ice_prof_type type,\n \t\t ice_bitmap_t *bm);\n+void\n+ice_init_prof_result_bm(struct ice_hw *hw);\n enum ice_status\n ice_get_sw_fv_list(struct ice_hw *hw, u16 *prot_ids, u8 ids_cnt,\n \t\t ice_bitmap_t *bm, struct LIST_HEAD_TYPE *fv_list);\ndiff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h\nindex c30d407c2..48c1e5184 100644\n--- a/drivers/net/ice/base/ice_flex_type.h\n+++ b/drivers/net/ice/base/ice_flex_type.h\n@@ -16,6 +16,8 @@ struct ice_fv_word {\n };\n #pragma pack()\n \n+#define ICE_MAX_NUM_PROFILES 256\n+\n #define ICE_MAX_FV_WORDS 48\n struct ice_fv {\n \tstruct ice_fv_word ew[ICE_MAX_FV_WORDS];\ndiff --git a/drivers/net/ice/base/ice_protocol_type.h b/drivers/net/ice/base/ice_protocol_type.h\nindex c6caa8562..98185c9de 100644\n--- a/drivers/net/ice/base/ice_protocol_type.h\n+++ b/drivers/net/ice/base/ice_protocol_type.h\n@@ -110,7 +110,7 @@ enum ice_prot_id {\n \tICE_PROT_ARP_OF\t\t= 118,\n \tICE_PROT_EAPOL_OF\t= 120,\n \tICE_PROT_META_ID\t= 255, /* when offset == metaddata */\n-\tICE_PROT_INVALID\t= 255 /* when offset == 0xFF */\n+\tICE_PROT_INVALID\t= 255 /* when offset == ICE_FV_OFFSET_INVAL */\n };\n \n #define ICE_VNI_OFFSET\t\t12 /* offset of VNI from ICE_PROT_UDP_OF */\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex 62ccf533c..9681d9590 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -467,21 +467,6 @@ static void ice_collect_result_idx(struct ice_aqc_recipe_data_elem *buf,\n }\n \n /**\n- * ice_init_possible_res_bm - initialize possible result bitmap\n- * @pos_result_bm: pointer to the bitmap to initialize\n- */\n-static void ice_init_possible_res_bm(ice_bitmap_t *pos_result_bm)\n-{\n-\tu16 bit;\n-\n-\tice_zero_bitmap(pos_result_bm, ICE_MAX_FV_WORDS);\n-\n-\tfor (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)\n-\t\tif (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))\n-\t\t\tice_set_bit(bit, pos_result_bm);\n-}\n-\n-/**\n * ice_get_recp_frm_fw - update SW bookkeeping from FW recipe entries\n * @hw: pointer to hardware structure\n * @recps: struct that we need to populate\n@@ -496,7 +481,6 @@ static enum ice_status\n ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \t\t bool *refresh_required)\n {\n-\tice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);\n \tice_declare_bitmap(result_bm, ICE_MAX_FV_WORDS);\n \tstruct ice_aqc_recipe_data_elem *tmp;\n \tu16 num_recps = ICE_MAX_NUM_RECIPES;\n@@ -505,7 +489,6 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \tenum ice_status status;\n \n \tice_zero_bitmap(result_bm, ICE_MAX_FV_WORDS);\n-\tice_init_possible_res_bm(possible_idx);\n \n \t/* we need a buffer big enough to accommodate all the recipes */\n \ttmp = (struct ice_aqc_recipe_data_elem *)ice_calloc(hw,\n@@ -541,7 +524,7 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \tfor (sub_recps = 0; sub_recps < num_recps; sub_recps++) {\n \t\tstruct ice_aqc_recipe_data_elem root_bufs = tmp[sub_recps];\n \t\tstruct ice_recp_grp_entry *rg_entry;\n-\t\tu8 prof_id, idx, prot = 0;\n+\t\tu8 prof, idx, prot = 0;\n \t\tbool is_root;\n \t\tu16 off = 0;\n \n@@ -561,8 +544,8 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \t\t\t\t ~ICE_AQ_RECIPE_RESULT_EN, result_bm);\n \n \t\t/* get the first profile that is associated with rid */\n-\t\tprof_id = ice_find_first_bit(recipe_to_profile[idx],\n-\t\t\t\t\t ICE_MAX_NUM_PROFILES);\n+\t\tprof = ice_find_first_bit(recipe_to_profile[idx],\n+\t\t\t\t\t ICE_MAX_NUM_PROFILES);\n \t\tfor (i = 0; i < ICE_NUM_WORDS_RECIPE; i++) {\n \t\t\tu8 lkup_indx = root_bufs.content.lkup_indx[i + 1];\n \n@@ -579,12 +562,13 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \t\t\t * has ICE_AQ_RECIPE_LKUP_IGNORE or 0 since it isn't a\n \t\t\t * valid offset value.\n \t\t\t */\n-\t\t\tif (ice_is_bit_set(possible_idx, rg_entry->fv_idx[i]) ||\n+\t\t\tif (ice_is_bit_set(hw->switch_info->prof_res_bm[prof],\n+\t\t\t\t\t rg_entry->fv_idx[i]) ||\n \t\t\t rg_entry->fv_idx[i] & ICE_AQ_RECIPE_LKUP_IGNORE ||\n \t\t\t rg_entry->fv_idx[i] == 0)\n \t\t\t\tcontinue;\n \n-\t\t\tice_find_prot_off(hw, ICE_BLK_SW, prof_id,\n+\t\t\tice_find_prot_off(hw, ICE_BLK_SW, prof,\n \t\t\t\t\t rg_entry->fv_idx[i], &prot, &off);\n \t\t\tlkup_exts->fv_words[fv_word_idx].prot_id = prot;\n \t\t\tlkup_exts->fv_words[fv_word_idx].off = off;\n@@ -4950,30 +4934,32 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,\n \t\t\t ice_bitmap_t *free_idx)\n {\n \tice_declare_bitmap(possible_idx, ICE_MAX_FV_WORDS);\n-\tice_declare_bitmap(used_idx, ICE_MAX_FV_WORDS);\n \tice_declare_bitmap(recipes, ICE_MAX_NUM_RECIPES);\n+\tice_declare_bitmap(used_idx, ICE_MAX_FV_WORDS);\n \tu16 count = 0;\n \tu16 bit;\n \n-\tice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS);\n-\tice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS);\n+\tice_zero_bitmap(possible_idx, ICE_MAX_FV_WORDS);\n \tice_zero_bitmap(recipes, ICE_MAX_NUM_RECIPES);\n-\tice_init_possible_res_bm(possible_idx);\n+\tice_zero_bitmap(used_idx, ICE_MAX_FV_WORDS);\n+\tice_zero_bitmap(free_idx, ICE_MAX_FV_WORDS);\n \n-\tfor (bit = 0; bit < ICE_MAX_FV_WORDS; bit++)\n-\t\tif (ICE_POSSIBLE_RES_IDX & BIT_ULL(bit))\n-\t\t\tice_set_bit(bit, possible_idx);\n+\tfor (count = 0; count < ICE_MAX_FV_WORDS; count++)\n+\t\tice_set_bit(count, possible_idx);\n \n \t/* For each profile we are going to associate the recipe with, add the\n \t * recipes that are associated with that profile. This will give us\n-\t * the set of recipes that our recipe may collide with.\n+\t * the set of recipes that our recipe may collide with. Also, determine\n+\t * what possible result indexes are usable given this set of profiles.\n \t */\n \tbit = 0;\n \twhile (ICE_MAX_NUM_PROFILES >\n \t (bit = ice_find_next_bit(profiles, ICE_MAX_NUM_PROFILES, bit))) {\n \t\tice_or_bitmap(recipes, recipes, profile_to_recipe[bit],\n \t\t\t ICE_MAX_NUM_RECIPES);\n-\n+\t\tice_and_bitmap(possible_idx, possible_idx,\n+\t\t\t hw->switch_info->prof_res_bm[bit],\n+\t\t\t ICE_MAX_FV_WORDS);\n \t\tbit++;\n \t}\n \n@@ -4981,14 +4967,16 @@ ice_find_free_recp_res_idx(struct ice_hw *hw, const ice_bitmap_t *profiles,\n \t * which indexes have been used.\n \t */\n \tfor (bit = 0; bit < ICE_MAX_NUM_RECIPES; bit++)\n-\t\tif (ice_is_bit_set(recipes, bit))\n+\t\tif (ice_is_bit_set(recipes, bit)) {\n \t\t\tice_or_bitmap(used_idx, used_idx,\n \t\t\t\t hw->switch_info->recp_list[bit].res_idxs,\n \t\t\t\t ICE_MAX_FV_WORDS);\n+\t\t}\n \n \tice_xor_bitmap(free_idx, used_idx, possible_idx, ICE_MAX_FV_WORDS);\n \n \t/* return number of free indexes */\n+\tcount = 0;\n \tbit = 0;\n \twhile (ICE_MAX_FV_WORDS >\n \t (bit = ice_find_next_bit(free_idx, ICE_MAX_FV_WORDS, bit))) {\n@@ -5029,6 +5017,9 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,\n \tice_zero_bitmap(result_idx_bm, ICE_MAX_FV_WORDS);\n \tfree_res_idx = ice_find_free_recp_res_idx(hw, profiles, result_idx_bm);\n \n+\tice_debug(hw, ICE_DBG_SW, \"Result idx slots: %d, need %d\\n\",\n+\t\t free_res_idx, rm->n_grp_count);\n+\n \tif (rm->n_grp_count > 1) {\n \t\tif (rm->n_grp_count > free_res_idx)\n \t\t\treturn ICE_ERR_MAX_LIMIT;\n@@ -6081,6 +6072,12 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,\n \tu32 act = 0;\n \tu8 q_rgn;\n \n+\t/* Initialize profile to result index bitmap */\n+\tif (!hw->switch_info->prof_res_bm_init) {\n+\t\thw->switch_info->prof_res_bm_init = 1;\n+\t\tice_init_prof_result_bm(hw);\n+\t}\n+\n \tif (!lkups_cnt)\n \t\treturn ICE_ERR_PARAM;\n \ndiff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h\nindex 0f0a1e98e..61083738a 100644\n--- a/drivers/net/ice/base/ice_switch.h\n+++ b/drivers/net/ice/base/ice_switch.h\n@@ -222,7 +222,6 @@ struct ice_sw_recipe {\n \t/* Profiles this recipe should be associated with */\n \tstruct LIST_HEAD_TYPE fv_list;\n \n-#define ICE_MAX_NUM_PROFILES 256\n \t/* Profiles this recipe is associated with */\n \tu8 num_profs, *prof_ids;\n \ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 8322d88a0..a8e4229a1 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -730,6 +730,9 @@ struct ice_port_info {\n struct ice_switch_info {\n \tstruct LIST_HEAD_TYPE vsi_list_map_head;\n \tstruct ice_sw_recipe *recp_list;\n+\tu16 prof_res_bm_init;\n+\n+\tice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);\n };\n \n /* Port hardware description */\n", "prefixes": [ "v5", "23/30" ] }