Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 59589,
    "url": "https://patches.dpdk.org/api/patches/59589/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190923074448.7847-18-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190923074448.7847-18-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190923074448.7847-18-qi.z.zhang@intel.com",
    "date": "2019-09-23T07:44:35",
    "name": "[v5,17/30] net/ice/base: enable symmetric hash for RSS",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "dacf0da08455aabeaed21068f3063c5079a648f7",
    "submitter": {
        "id": 504,
        "url": "https://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 31221,
        "url": "https://patches.dpdk.org/api/users/31221/?format=api",
        "username": "yexl",
        "first_name": "xiaolong",
        "last_name": "ye",
        "email": "xiaolong.ye@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190923074448.7847-18-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 6483,
            "url": "https://patches.dpdk.org/api/series/6483/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6483",
            "date": "2019-09-23T07:44:18",
            "name": "net/ice/base: share code update secend batch.",
            "version": 5,
            "mbox": "https://patches.dpdk.org/series/6483/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/59589/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/59589/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 81DBE1BEFD;\n\tMon, 23 Sep 2019 09:42:59 +0200 (CEST)",
            "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id 3563E1BEA3\n\tfor <dev@dpdk.org>; Mon, 23 Sep 2019 09:42:28 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Sep 2019 00:42:27 -0700",
            "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:26 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.64,539,1559545200\"; d=\"scan'208\";a=\"182445672\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com",
        "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Mon, 23 Sep 2019 15:44:35 +0800",
        "Message-Id": "<20190923074448.7847-18-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20190923074448.7847-1-qi.z.zhang@intel.com>",
        "References": "<20190902035551.16852-1-qi.z.zhang@intel.com>\n\t<20190923074448.7847-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v5 17/30] net/ice/base: enable symmetric hash for\n\tRSS",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add parameter \"symm\" to rss configuration APIs.\nWhen symm is 1, Symmetric Teoplitz Hash can be enabled by\nconfiguring GLQF_HSYMM properly.\n\nNOTE:\nSymmetric Teoplitz hash will work only if hash schema of\nVSIQF_HASH_CTL be configured to 01b and it is assumed be enabled\nin PMD.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n---\n drivers/net/ice/base/ice_flow.c | 149 +++++++++++++++++++++++++++++++++++++---\n drivers/net/ice/base/ice_flow.h |   5 +-\n drivers/net/ice/ice_ethdev.c    |  16 ++---\n 3 files changed, 150 insertions(+), 20 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex d91922527..e0e4fcab6 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -1876,6 +1876,7 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)\n \n \trss_cfg->hashed_flds = prof->segs[prof->segs_cnt - 1].match;\n \trss_cfg->packet_hdr = prof->segs[prof->segs_cnt - 1].hdrs;\n+\trss_cfg->symm = prof->cfg.symm;\n \tice_set_bit(vsi_handle, rss_cfg->vsis);\n \n \tLIST_ADD_TAIL(&rss_cfg->l_entry, &hw->rss_list_head);\n@@ -1903,6 +1904,107 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)\n \t      (((u64)(hdr) << ICE_FLOW_PROF_HDR_S) & ICE_FLOW_PROF_HDR_M) | \\\n \t      ((u8)((segs_cnt) - 1) ? ICE_FLOW_PROF_ENCAP_M : 0))\n \n+static void\n+ice_rss_config_xor_word(struct ice_hw *hw, u8 prof_id, u8 src, u8 dst)\n+{\n+\tu32 s = ((src % 4) << 3); /* byte shift */\n+\tu32 v = dst | 0x80; /* value to program */\n+\tu8 i = src / 4; /* register index */\n+\tu32 reg;\n+\n+\treg = rd32(hw, GLQF_HSYMM(prof_id, i));\n+\treg = (reg & ~(0xff << s)) | (v << s);\n+\twr32(hw, GLQF_HSYMM(prof_id, i), reg);\n+}\n+\n+static void\n+ice_rss_config_xor(struct ice_hw *hw, u8 prof_id, u8 src, u8 dst, u8 len)\n+{\n+\tint fv_last_word =\n+\t\tICE_FLOW_SW_FIELD_VECTOR_MAX / ICE_FLOW_FV_EXTRACT_SZ - 1;\n+\tint i;\n+\n+\tfor (i = 0; i < len; i++) {\n+\t\tice_rss_config_xor_word(hw, prof_id,\n+\t\t\t\t\t/* Yes, field vector in GLQF_HSYMM and\n+\t\t\t\t\t * GLQF_HINSET is inversed!\n+\t\t\t\t\t */\n+\t\t\t\t\tfv_last_word - (src + i),\n+\t\t\t\t\tfv_last_word - (dst + i));\n+\t\tice_rss_config_xor_word(hw, prof_id,\n+\t\t\t\t\tfv_last_word - (dst + i),\n+\t\t\t\t\tfv_last_word - (src + i));\n+\t}\n+}\n+\n+static void\n+ice_rss_update_symm(struct ice_hw *hw,\n+\t\t    struct ice_flow_prof *prof)\n+{\n+\tstruct ice_prof_map *map;\n+\tu8 prof_id, m;\n+\n+\tmap = ice_search_prof_id(hw, ICE_BLK_RSS, prof->id);\n+\tprof_id = map->prof_id;\n+\n+\t/* clear to default */\n+\tfor (m = 0; m < 6; m++)\n+\t\twr32(hw, GLQF_HSYMM(prof_id, m), 0);\n+\tif (prof->cfg.symm) {\n+\t\tstruct ice_flow_seg_info *seg =\n+\t\t\t&prof->segs[prof->segs_cnt - 1];\n+\n+\t\tstruct ice_flow_seg_xtrct *ipv4_src =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_IPV4_SA].xtrct;\n+\t\tstruct ice_flow_seg_xtrct *ipv4_dst =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_IPV4_DA].xtrct;\n+\t\tstruct ice_flow_seg_xtrct *ipv6_src =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_IPV6_SA].xtrct;\n+\t\tstruct ice_flow_seg_xtrct *ipv6_dst =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_IPV6_DA].xtrct;\n+\n+\t\tstruct ice_flow_seg_xtrct *tcp_src =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_TCP_SRC_PORT].xtrct;\n+\t\tstruct ice_flow_seg_xtrct *tcp_dst =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_TCP_DST_PORT].xtrct;\n+\n+\t\tstruct ice_flow_seg_xtrct *udp_src =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_UDP_SRC_PORT].xtrct;\n+\t\tstruct ice_flow_seg_xtrct *udp_dst =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_UDP_DST_PORT].xtrct;\n+\n+\t\tstruct ice_flow_seg_xtrct *sctp_src =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT].xtrct;\n+\t\tstruct ice_flow_seg_xtrct *sctp_dst =\n+\t\t\t&seg->fields[ICE_FLOW_FIELD_IDX_SCTP_DST_PORT].xtrct;\n+\n+\t\t/* xor IPv4 */\n+\t\tif (ipv4_src->prot_id != 0 && ipv4_dst->prot_id != 0)\n+\t\t\tice_rss_config_xor(hw, prof_id,\n+\t\t\t\t\t   ipv4_src->idx, ipv4_dst->idx, 2);\n+\n+\t\t/* xor IPv6 */\n+\t\tif (ipv6_src->prot_id != 0 && ipv6_dst->prot_id != 0)\n+\t\t\tice_rss_config_xor(hw, prof_id,\n+\t\t\t\t\t   ipv6_src->idx, ipv6_dst->idx, 8);\n+\n+\t\t/* xor TCP */\n+\t\tif (tcp_src->prot_id != 0 && tcp_dst->prot_id != 0)\n+\t\t\tice_rss_config_xor(hw, prof_id,\n+\t\t\t\t\t   tcp_src->idx, tcp_dst->idx, 1);\n+\n+\t\t/* xor UDP */\n+\t\tif (udp_src->prot_id != 0 && udp_dst->prot_id != 0)\n+\t\t\tice_rss_config_xor(hw, prof_id,\n+\t\t\t\t\t   udp_src->idx, udp_dst->idx, 1);\n+\n+\t\t/* xor SCTP */\n+\t\tif (sctp_src->prot_id != 0 && sctp_dst->prot_id != 0)\n+\t\t\tice_rss_config_xor(hw, prof_id,\n+\t\t\t\t\t   sctp_src->idx, sctp_dst->idx, 1);\n+\t}\n+}\n+\n /**\n  * ice_add_rss_cfg_sync - add an RSS configuration\n  * @hw: pointer to the hardware structure\n@@ -1910,12 +2012,13 @@ ice_add_rss_list(struct ice_hw *hw, u16 vsi_handle, struct ice_flow_prof *prof)\n  * @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure\n  * @addl_hdrs: protocol header fields\n  * @segs_cnt: packet segment count\n+ * @symm: symmetric hash enable/disable\n  *\n  * Assumption: lock has already been acquired for RSS list\n  */\n static enum ice_status\n ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n-\t\t     u32 addl_hdrs, u8 segs_cnt)\n+\t\t     u32 addl_hdrs, u8 segs_cnt, bool symm)\n {\n \tconst enum ice_block blk = ICE_BLK_RSS;\n \tstruct ice_flow_prof *prof = NULL;\n@@ -1944,8 +2047,12 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n \t\t\t\t\tvsi_handle,\n \t\t\t\t\tICE_FLOW_FIND_PROF_CHK_FLDS |\n \t\t\t\t\tICE_FLOW_FIND_PROF_CHK_VSI);\n-\tif (prof)\n-\t\tgoto exit;\n+\tif (prof) {\n+\t\tif (prof->cfg.symm == symm)\n+\t\t\tgoto exit;\n+\t\tprof->cfg.symm = symm;\n+\t\tgoto update_symm;\n+\t}\n \n \t/* Check if a flow profile exists with the same protocol headers and\n \t * associated with the input VSI. If so disasscociate the VSI from\n@@ -1976,9 +2083,18 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n \t\t\t\t\tvsi_handle,\n \t\t\t\t\tICE_FLOW_FIND_PROF_CHK_FLDS);\n \tif (prof) {\n-\t\tstatus = ice_flow_assoc_prof(hw, blk, prof, vsi_handle);\n-\t\tif (!status)\n-\t\t\tstatus = ice_add_rss_list(hw, vsi_handle, prof);\n+\t\tif (prof->cfg.symm == symm) {\n+\t\t\tstatus = ice_flow_assoc_prof(hw, blk, prof,\n+\t\t\t\t\t\t     vsi_handle);\n+\t\t\tif (!status)\n+\t\t\t\tstatus = ice_add_rss_list(hw, vsi_handle,\n+\t\t\t\t\t\t\t  prof);\n+\t\t} else {\n+\t\t\t/* if a profile exist but with different symmetric\n+\t\t\t * requirement, just return error.\n+\t\t\t */\n+\t\t\tstatus = ICE_ERR_NOT_SUPPORTED;\n+\t\t}\n \t\tgoto exit;\n \t}\n \n@@ -2004,6 +2120,13 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n \n \tstatus = ice_add_rss_list(hw, vsi_handle, prof);\n \n+\tprof->cfg.symm = symm;\n+\tif (!symm)\n+\t\tgoto exit;\n+\n+update_symm:\n+\tice_rss_update_symm(hw, prof);\n+\n exit:\n \tice_free(hw, segs);\n \treturn status;\n@@ -2015,6 +2138,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n  * @vsi_handle: software VSI handle\n  * @hashed_flds: hash bit fields (ICE_FLOW_HASH_*) to configure\n  * @addl_hdrs: protocol header fields\n+ * @symm: symmetric hash enable/disable\n  *\n  * This function will generate a flow profile based on fields associated with\n  * the input fields to hash on, the flow type and use the VSI number to add\n@@ -2022,7 +2146,7 @@ ice_add_rss_cfg_sync(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n  */\n enum ice_status\n ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n-\t\tu32 addl_hdrs)\n+\t\tu32 addl_hdrs, bool symm)\n {\n \tenum ice_status status;\n \n@@ -2032,10 +2156,11 @@ ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n \n \tice_acquire_lock(&hw->rss_locks);\n \tstatus = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds, addl_hdrs,\n-\t\t\t\t      ICE_RSS_OUTER_HEADERS);\n+\t\t\t\t      ICE_RSS_OUTER_HEADERS, symm);\n \tif (!status)\n \t\tstatus = ice_add_rss_cfg_sync(hw, vsi_handle, hashed_flds,\n-\t\t\t\t\t      addl_hdrs, ICE_RSS_INNER_HEADERS);\n+\t\t\t\t\t      addl_hdrs, ICE_RSS_INNER_HEADERS,\n+\t\t\t\t\t      symm);\n \tice_release_lock(&hw->rss_locks);\n \n \treturn status;\n@@ -2148,13 +2273,15 @@ enum ice_status ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle)\n \t\t\tstatus = ice_add_rss_cfg_sync(hw, vsi_handle,\n \t\t\t\t\t\t      r->hashed_flds,\n \t\t\t\t\t\t      r->packet_hdr,\n-\t\t\t\t\t\t      ICE_RSS_OUTER_HEADERS);\n+\t\t\t\t\t\t      ICE_RSS_OUTER_HEADERS,\n+\t\t\t\t\t\t      r->symm);\n \t\t\tif (status)\n \t\t\t\tbreak;\n \t\t\tstatus = ice_add_rss_cfg_sync(hw, vsi_handle,\n \t\t\t\t\t\t      r->hashed_flds,\n \t\t\t\t\t\t      r->packet_hdr,\n-\t\t\t\t\t\t      ICE_RSS_INNER_HEADERS);\n+\t\t\t\t\t\t      ICE_RSS_INNER_HEADERS,\n+\t\t\t\t\t\t      r->symm);\n \t\t\tif (status)\n \t\t\t\tbreak;\n \t\t}\ndiff --git a/drivers/net/ice/base/ice_flow.h b/drivers/net/ice/base/ice_flow.h\nindex 3afd201c4..6f26f3935 100644\n--- a/drivers/net/ice/base/ice_flow.h\n+++ b/drivers/net/ice/base/ice_flow.h\n@@ -315,6 +315,8 @@ struct ice_flow_prof {\n \t\t/* struct sw_recipe */\n \t\t/* struct fd */\n \t\tu32 data;\n+\t\t/* Symmetric Hash for RSS */\n+\t\tbool symm;\n \t} cfg;\n \n \t/* Default actions */\n@@ -327,6 +329,7 @@ struct ice_rss_cfg {\n \tice_declare_bitmap(vsis, ICE_MAX_VSI);\n \tu64 hashed_flds;\n \tu32 packet_hdr;\n+\tbool symm;\n };\n \n enum ice_flow_action_type {\n@@ -402,7 +405,7 @@ ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds);\n enum ice_status ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle);\n enum ice_status\n ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n-\t\tu32 addl_hdrs);\n+\t\tu32 addl_hdrs, bool symm);\n enum ice_status\n ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,\n \t\tu32 addl_hdrs);\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 63997fdfb..ccd64f49f 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -1790,50 +1790,50 @@ static int ice_init_rss(struct ice_pf *pf)\n \n \t/* configure RSS for IPv4 with input set IPv4 src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,\n-\t\t\t      ICE_FLOW_SEG_HDR_IPV4);\n+\t\t\t      ICE_FLOW_SEG_HDR_IPV4, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s IPV4 rss flow fail %d\", __func__, ret);\n \n \t/* configure RSS for IPv6 with input set IPv6 src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,\n-\t\t\t      ICE_FLOW_SEG_HDR_IPV6);\n+\t\t\t      ICE_FLOW_SEG_HDR_IPV6, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s IPV6 rss flow fail %d\", __func__, ret);\n \n \t/* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,\n-\t\t\t      ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);\n+\t\t\t      ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s TCP_IPV6 rss flow fail %d\", __func__, ret);\n \n \t/* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,\n-\t\t\t      ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);\n+\t\t\t      ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s UDP_IPV6 rss flow fail %d\", __func__, ret);\n \n \t/* configure RSS for sctp6 with input set IPv6 src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,\n-\t\t\t      ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);\n+\t\t\t      ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s SCTP_IPV6 rss flow fail %d\",\n \t\t\t\t__func__, ret);\n \n \t/* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,\n-\t\t\t      ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);\n+\t\t\t      ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s TCP_IPV4 rss flow fail %d\", __func__, ret);\n \n \t/* configure RSS for udp4 with input set IP src/dst, UDP src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,\n-\t\t\t      ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);\n+\t\t\t      ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s UDP_IPV4 rss flow fail %d\", __func__, ret);\n \n \t/* configure RSS for sctp4 with input set IP src/dst */\n \tret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,\n-\t\t\t      ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);\n+\t\t\t      ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);\n \tif (ret)\n \t\tPMD_DRV_LOG(ERR, \"%s SCTP_IPV4 rss flow fail %d\",\n \t\t\t\t__func__, ret);\n",
    "prefixes": [
        "v5",
        "17/30"
    ]
}