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GET /api/patches/59577/?format=api
{ "id": 59577, "url": "https://patches.dpdk.org/api/patches/59577/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190923074448.7847-6-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190923074448.7847-6-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190923074448.7847-6-qi.z.zhang@intel.com", "date": "2019-09-23T07:44:23", "name": "[v5,05/30] net/ice/base: correct the mask for checking protocol header", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "3e6c970898a448db568778f12d3dc58f4e83b8aa", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190923074448.7847-6-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6483, "url": "https://patches.dpdk.org/api/series/6483/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6483", "date": "2019-09-23T07:44:18", "name": "net/ice/base: share code update secend batch.", "version": 5, "mbox": "https://patches.dpdk.org/series/6483/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/59577/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/59577/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1570E1BEB2;\n\tMon, 23 Sep 2019 09:42:29 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id 82ADA1BE92\n\tfor <dev@dpdk.org>; Mon, 23 Sep 2019 09:42:06 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Sep 2019 00:42:06 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga008.jf.intel.com with ESMTP; 23 Sep 2019 00:42:04 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,539,1559545200\"; d=\"scan'208\";a=\"182445553\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tZhirun Yan <zhirun.yan@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 23 Sep 2019 15:44:23 +0800", "Message-Id": "<20190923074448.7847-6-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190923074448.7847-1-qi.z.zhang@intel.com>", "References": "<20190902035551.16852-1-qi.z.zhang@intel.com>\n\t<20190923074448.7847-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 05/30] net/ice/base: correct the mask for\n\tchecking protocol header", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Before this patch, the logic of protocol header checking only support\nnon-tunneled packet. This patch remove the inner protocol in L3/L4 RSS\nseg hdr mask and change the protocol header validation to reflect this.\nSo, for ice_add_rss_cfg(), the last parameter addl_hdrs could specify\nthe protocol header for tunnel.\n\nSigned-off-by: Zhirun Yan <zhirun.yan@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flow.c | 20 +++++++++++---------\n 1 file changed, 11 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex 769fd2da7..682f26ce6 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -372,15 +372,18 @@ struct ice_flow_prof_params {\n \tice_declare_bitmap(ptypes, ICE_FLOW_PTYPE_MAX);\n };\n \n+#define ICE_FLOW_RSS_HDRS_INNER_MASK \\\n+\t(ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_GTPC | \\\n+\t ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU)\n+\n #define ICE_FLOW_SEG_HDRS_L2_MASK\t\\\n \t(ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)\n #define ICE_FLOW_SEG_HDRS_L3_MASK\t\\\n \t(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | \\\n-\t ICE_FLOW_SEG_HDR_ARP | ICE_FLOW_SEG_HDR_PPPOE)\n+\t ICE_FLOW_SEG_HDR_ARP)\n #define ICE_FLOW_SEG_HDRS_L4_MASK\t\\\n \t(ICE_FLOW_SEG_HDR_ICMP | ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \\\n-\t ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC | \\\n-\t ICE_FLOW_SEG_HDR_GTPC_TEID | ICE_FLOW_SEG_HDR_GTPU)\n+\t ICE_FLOW_SEG_HDR_SCTP)\n \n /**\n * ice_flow_val_hdrs - validates packet segments for valid protocol headers\n@@ -1686,13 +1689,11 @@ ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,\n (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN)\n \n #define ICE_FLOW_RSS_SEG_HDR_L3_MASKS \\\n-\t(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_PPPOE)\n+\t(ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6)\n \n #define ICE_FLOW_RSS_SEG_HDR_L4_MASKS \\\n \t(ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_UDP | \\\n-\t ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_GTPC_TEID | \\\n-\t ICE_FLOW_SEG_HDR_GTPU)\n-\n+\t ICE_FLOW_SEG_HDR_SCTP)\n \n #define ICE_FLOW_RSS_SEG_HDR_VAL_MASKS \\\n \t(ICE_FLOW_RSS_SEG_HDR_L2_MASKS | \\\n@@ -1729,11 +1730,12 @@ ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u64 hash_fields,\n \t}\n \tICE_FLOW_SET_HDRS(segs, flow_hdr);\n \n-\tif (segs->hdrs & ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS)\n+\tif (segs->hdrs & ~ICE_FLOW_RSS_SEG_HDR_VAL_MASKS &\n+\t ~ICE_FLOW_RSS_HDRS_INNER_MASK)\n \t\treturn ICE_ERR_PARAM;\n \n \tval = (u64)(segs->hdrs & ICE_FLOW_RSS_SEG_HDR_L3_MASKS);\n-\tif (!ice_is_pow2(val))\n+\tif (val && !ice_is_pow2(val))\n \t\treturn ICE_ERR_CFG;\n \n \tval = (u64)(segs->hdrs & ICE_FLOW_RSS_SEG_HDR_L4_MASKS);\n", "prefixes": [ "v5", "05/30" ] }