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GET /api/patches/58575/?format=api
{ "id": 58575, "url": "https://patches.dpdk.org/api/patches/58575/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1567652381-124289-4-git-send-email-andy.pei@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567652381-124289-4-git-send-email-andy.pei@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567652381-124289-4-git-send-email-andy.pei@intel.com", "date": "2019-09-05T02:59:32", "name": "[v4,03/12] raw/ifpga/base: clear pending bit", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "906c22605c78c3aa835c47c57145006bd16d778b", "submitter": { "id": 1185, "url": "https://patches.dpdk.org/api/people/1185/?format=api", "name": "Pei, Andy", "email": "andy.pei@intel.com" }, "delegate": { "id": 31221, "url": "https://patches.dpdk.org/api/users/31221/?format=api", "username": "yexl", "first_name": "xiaolong", "last_name": "ye", "email": "xiaolong.ye@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1567652381-124289-4-git-send-email-andy.pei@intel.com/mbox/", "series": [ { "id": 6243, "url": "https://patches.dpdk.org/api/series/6243/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6243", "date": "2019-09-05T02:59:29", "name": "Add PCIe AER disable and IRQ support for ipn3ke", "version": 4, "mbox": "https://patches.dpdk.org/series/6243/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/58575/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/58575/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id BA73B1EA5D;\n\tThu, 5 Sep 2019 05:12:28 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id 97F091EA4E\n\tfor <dev@dpdk.org>; Thu, 5 Sep 2019 05:12:27 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t04 Sep 2019 20:12:27 -0700", "from dpdk-dipei.sh.intel.com ([10.67.110.224])\n\tby orsmga004.jf.intel.com with ESMTP; 04 Sep 2019 20:12:25 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,469,1559545200\"; d=\"scan'208\";a=\"334419150\"", "From": "Andy Pei <andy.pei@intel.com>", "To": "dev@dpdk.org", "Cc": "rosen.xu@intel.com, tianfei.zhang@intel.com, andy.pei@intel.com,\n\txiaolong.ye@intel.com, qi.z.zhang@intel.com, david.lomartire@intel.com,\n\tferruh.yigit@intel.com", "Date": "Thu, 5 Sep 2019 10:59:32 +0800", "Message-Id": "<1567652381-124289-4-git-send-email-andy.pei@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1567652381-124289-1-git-send-email-andy.pei@intel.com>", "References": "<1565253974-183591-14-git-send-email-rosen.xu@intel.com>\n\t<1567652381-124289-1-git-send-email-andy.pei@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 03/12] raw/ifpga/base: clear pending bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Every defined bit in FME_ERROR0 is RW1C. Other reserved bits are always\n0 when readout and it will plan to be RW1C if needed in future.\nSo it is safe just write the read back value to clear all the errors.\n\nSigned-off-by: Tianfei zhang <tianfei.zhang@intel.com>\nSigned-off-by: Andy Pei <andy.pei@intel.com>\n---\n drivers/raw/ifpga/base/ifpga_defines.h | 9 ++++-----\n drivers/raw/ifpga/base/ifpga_fme_error.c | 4 ++--\n drivers/raw/ifpga/base/opae_osdep.h | 7 +++++--\n 3 files changed, 11 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/raw/ifpga/base/ifpga_defines.h b/drivers/raw/ifpga/base/ifpga_defines.h\nindex b7151ca..4216128 100644\n--- a/drivers/raw/ifpga/base/ifpga_defines.h\n+++ b/drivers/raw/ifpga/base/ifpga_defines.h\n@@ -957,25 +957,24 @@ struct feature_fme_dperf {\n };\n \n struct feature_fme_error0 {\n-#define FME_ERROR0_MASK 0xFFUL\n #define FME_ERROR0_MASK_DEFAULT 0x40UL /* pcode workaround */\n \tunion {\n \t\tu64 csr;\n \t\tstruct {\n \t\t\tu8 fabric_err:1;\t/* Fabric error */\n \t\t\tu8 fabfifo_overflow:1;\t/* Fabric fifo overflow */\n-\t\t\tu8 kticdc_parity_err:2;/* KTI CDC Parity Error */\n-\t\t\tu8 iommu_parity_err:1;\t/* IOMMU Parity error */\n+\t\t\tu8 reserved2:3;\n \t\t\t/* AFU PF/VF access mismatch detected */\n \t\t\tu8 afu_acc_mode_err:1;\n-\t\t\tu8 mbp_err:1;\t\t/* Indicates an MBP event */\n+\t\t\tu8 reserved6:1;\n \t\t\t/* PCIE0 CDC Parity Error */\n \t\t\tu8 pcie0cdc_parity_err:5;\n \t\t\t/* PCIE1 CDC Parity Error */\n \t\t\tu8 pcie1cdc_parity_err:5;\n \t\t\t/* CVL CDC Parity Error */\n \t\t\tu8 cvlcdc_parity_err:3;\n-\t\t\tu64 rsvd:44;\t\t/* Reserved */\n+\t\t\tu8 fpgaseuerr:1;\n+\t\t\tu64 rsvd:43;\t\t/* Reserved */\n \t\t};\n \t};\n };\ndiff --git a/drivers/raw/ifpga/base/ifpga_fme_error.c b/drivers/raw/ifpga/base/ifpga_fme_error.c\nindex 068f52c..a6d3dab 100644\n--- a/drivers/raw/ifpga/base/ifpga_fme_error.c\n+++ b/drivers/raw/ifpga/base/ifpga_fme_error.c\n@@ -54,7 +54,7 @@ static int fme_err_set_clear(struct ifpga_fme_hw *fme, u64 val)\n \tint ret = 0;\n \n \tspinlock_lock(&fme->lock);\n-\twriteq(FME_ERROR0_MASK, &fme_err->fme_err_mask);\n+\twriteq(GENMASK_ULL(63, 0), &fme_err->fme_err_mask);\n \n \tfme_error0.csr = readq(&fme_err->fme_err);\n \tif (val != fme_error0.csr) {\n@@ -65,7 +65,7 @@ static int fme_err_set_clear(struct ifpga_fme_hw *fme, u64 val)\n \tfme_first_err.csr = readq(&fme_err->fme_first_err);\n \tfme_next_err.csr = readq(&fme_err->fme_next_err);\n \n-\twriteq(fme_error0.csr & FME_ERROR0_MASK, &fme_err->fme_err);\n+\twriteq(fme_error0.csr, &fme_err->fme_err);\n \twriteq(fme_first_err.csr & FME_FIRST_ERROR_MASK,\n \t &fme_err->fme_first_err);\n \twriteq(fme_next_err.csr & FME_NEXT_ERROR_MASK,\ndiff --git a/drivers/raw/ifpga/base/opae_osdep.h b/drivers/raw/ifpga/base/opae_osdep.h\nindex 1596adc..416cef0 100644\n--- a/drivers/raw/ifpga/base/opae_osdep.h\n+++ b/drivers/raw/ifpga/base/opae_osdep.h\n@@ -32,10 +32,12 @@ struct uuid {\n #ifndef BITS_PER_LONG\n #define BITS_PER_LONG\t(__SIZEOF_LONG__ * 8)\n #endif\n+#ifndef BITS_PER_LONG_LONG\n+#define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)\n+#endif\n #ifndef BIT\n #define BIT(a) (1UL << (a))\n #endif /* BIT */\n-#define U64_C(x) x ## ULL\n #ifndef BIT_ULL\n #define BIT_ULL(a) (1ULL << (a))\n #endif /* BIT_ULL */\n@@ -43,7 +45,8 @@ struct uuid {\n #define GENMASK(h, l)\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n #endif /* GENMASK */\n #ifndef GENMASK_ULL\n-#define GENMASK_ULL(h, l) (((U64_C(1) << ((h) - (l) + 1)) - 1) << (l))\n+#define GENMASK_ULL(h, l) \\\n+\t(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))\n #endif /* GENMASK_ULL */\n #endif /* LINUX_MACROS */\n \n", "prefixes": [ "v4", "03/12" ] }