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GET /api/patches/58360/?format=api
{ "id": 58360, "url": "https://patches.dpdk.org/api/patches/58360/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1567392847-445709-1-git-send-email-andy.pei@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567392847-445709-1-git-send-email-andy.pei@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567392847-445709-1-git-send-email-andy.pei@intel.com", "date": "2019-09-02T02:54:07", "name": "[v3] net/ipn3ke: setup MTU when HW init", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6670e3e0ffadd977447f083d4269b21520eda0d2", "submitter": { "id": 1185, "url": "https://patches.dpdk.org/api/people/1185/?format=api", "name": "Pei, Andy", "email": "andy.pei@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1567392847-445709-1-git-send-email-andy.pei@intel.com/mbox/", "series": [ { "id": 6192, "url": "https://patches.dpdk.org/api/series/6192/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6192", "date": "2019-09-02T02:54:07", "name": "[v3] net/ipn3ke: setup MTU when HW init", "version": 3, "mbox": "https://patches.dpdk.org/series/6192/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/58360/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/58360/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E40CC1C1F5;\n\tMon, 2 Sep 2019 05:06:22 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id BEC871C1CD\n\tfor <dev@dpdk.org>; Mon, 2 Sep 2019 05:06:20 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t01 Sep 2019 20:06:19 -0700", "from dpdk-dipei.sh.intel.com ([10.67.110.224])\n\tby fmsmga005.fm.intel.com with ESMTP; 01 Sep 2019 20:06:18 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,457,1559545200\"; d=\"scan'208\";a=\"381736850\"", "From": "Andy Pei <andy.pei@intel.com>", "To": "dev@dpdk.org", "Cc": "andy.pei@intel.com, qi.z.zhang@intel.com, ferruh.yigit@intel.com,\n\trosen.xu@intel.com, xiaolong.ye@intel.com", "Date": "Mon, 2 Sep 2019 10:54:07 +0800", "Message-Id": "<1567392847-445709-1-git-send-email-andy.pei@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1565280090-344032-1-git-send-email-andy.pei@intel.com>", "References": "<1565280090-344032-1-git-send-email-andy.pei@intel.com>", "Subject": "[dpdk-dev] [PATCH v3] net/ipn3ke: setup MTU when HW init", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "set up mtu to the minimun in tx mtu, rx mtu and IPN3KE_MAC_FRAME_SIZE_MAX.\n\nSigned-off-by: Andy Pei <andy.pei@intel.com>\n---\nCc: qi.z.zhang@intel.com\nCc: ferruh.yigit@intel.com\nCc: rosen.xu@intel.com\nCc: xiaolong.ye@intel.com\n\nv2:\nmodify low bound and upper bound.\n\nv3:\nmodify according to community comments.\n\n drivers/net/ipn3ke/ipn3ke_ethdev.c | 109 +++++++++++++++++++++++++++++++++++++\n drivers/net/ipn3ke/ipn3ke_ethdev.h | 15 +++++\n 2 files changed, 124 insertions(+)", "diff": "diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.c b/drivers/net/ipn3ke/ipn3ke_ethdev.c\nindex c226d63..711d48e 100644\n--- a/drivers/net/ipn3ke/ipn3ke_ethdev.c\n+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.c\n@@ -209,6 +209,112 @@\n \treturn 0;\n }\n \n+static uint32_t\n+ipn3ke_mtu_cal(uint32_t tx, uint32_t rx)\n+{\n+\tuint32_t tmp;\n+\ttmp = RTE_MIN(tx, rx);\n+\tif (tmp < RTE_ETHER_MIN_MTU)\n+\t\ttmp = RTE_ETHER_MIN_MTU;\n+\tif (tmp > IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD)\n+\t\ttmp = IPN3KE_MAC_FRAME_SIZE_MAX - IPN3KE_ETH_OVERHEAD;\n+\treturn tmp;\n+}\n+\n+static void\n+ipn3ke_10G_mtu_setup\n+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)\n+{\n+\tuint32_t tx;\n+\tuint32_t rx;\n+\tuint32_t tmp;\n+\n+\tif (!(*hw->f_mac_read) || !(*hw->f_mac_write))\n+\t\treturn;\n+\n+\t(*hw->f_mac_read)(hw,\n+\t\t\t&tx,\n+\t\t\tIPN3KE_10G_TX_FRAME_MAXLENGTH,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+\n+\t(*hw->f_mac_read)(hw,\n+\t\t\t&rx,\n+\t\t\tIPN3KE_10G_RX_FRAME_MAXLENGTH,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+\n+\ttmp = ipn3ke_mtu_cal(tx, rx);\n+\n+\t(*hw->f_mac_write)(hw,\n+\t\t\ttmp,\n+\t\t\tIPN3KE_10G_TX_FRAME_MAXLENGTH,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+\n+\t(*hw->f_mac_write)(hw,\n+\t\t\ttmp,\n+\t\t\tIPN3KE_10G_RX_FRAME_MAXLENGTH,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+}\n+\n+static void\n+ipn3ke_25G_mtu_setup\n+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)\n+{\n+\tuint32_t tx;\n+\tuint32_t rx;\n+\tuint32_t tmp;\n+\n+\tif (!(*hw->f_mac_read) || !(*hw->f_mac_write))\n+\t\treturn;\n+\n+\t(*hw->f_mac_read)(hw,\n+\t\t\t&tx,\n+\t\t\tIPN3KE_25G_MAX_TX_SIZE_CONFIG,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+\n+\t(*hw->f_mac_read)(hw,\n+\t\t\t&rx,\n+\t\t\tIPN3KE_25G_MAX_RX_SIZE_CONFIG,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+\n+\ttmp = ipn3ke_mtu_cal(tx, rx);\n+\n+\t(*hw->f_mac_write)(hw,\n+\t\t\ttmp,\n+\t\t\tIPN3KE_25G_MAX_TX_SIZE_CONFIG,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+\n+\t(*hw->f_mac_write)(hw,\n+\t\t\ttmp,\n+\t\t\tIPN3KE_25G_MAX_RX_SIZE_CONFIG,\n+\t\t\tmac_num,\n+\t\t\teth_group_sel);\n+}\n+\n+static void\n+ipn3ke_mtu_setup(struct ipn3ke_hw *hw)\n+{\n+\tint i;\n+\tif (hw->retimer.mac_type == IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI) {\n+\t\tfor (i = 0; i < hw->port_num; i++) {\n+\t\t\tipn3ke_10G_mtu_setup(hw, i, 0);\n+\t\t\tipn3ke_10G_mtu_setup(hw, i, 1);\n+\t\t}\n+\t} else if (hw->retimer.mac_type ==\n+\t\t\tIFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI) {\n+\t\tfor (i = 0; i < hw->port_num; i++) {\n+\t\t\tipn3ke_25G_mtu_setup(hw, i, 0);\n+\t\t\tipn3ke_25G_mtu_setup(hw, i, 1);\n+\t\t}\n+\t}\n+}\n+\n static int\n ipn3ke_hw_init(struct rte_afu_device *afu_dev,\n \tstruct ipn3ke_hw *hw)\n@@ -303,6 +409,9 @@\n \t\t}\n \t}\n \n+\t/* init mtu */\n+\tipn3ke_mtu_setup(hw);\n+\n \tret = rte_eth_switch_domain_alloc(&hw->switch_domain_id);\n \tif (ret)\n \t\tIPN3KE_AFU_PMD_WARN(\"failed to allocate switch domain for device %d\",\ndiff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h\nindex c7b336b..596df08 100644\n--- a/drivers/net/ipn3ke/ipn3ke_ethdev.h\n+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h\n@@ -654,6 +654,21 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,\n #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \\\n \tIPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)\n \n+/* Additional Feature Register */\n+#define ADD_PHY_CTRL\t\t0x0\n+#define PHY_RESET\t\tBIT(0)\n+/* registers for 25G/40G mac */\n+#define MAC_CONFIG\t0x310\n+#define MAC_RESET_MASK\tGENMASK(2, 0)\n+\n+#define IPN3KE_MAX_MTU 0xffff\n+\n+#define IPN3KE_25G_MAX_TX_SIZE_CONFIG 0x407\n+#define IPN3KE_25G_MAX_RX_SIZE_CONFIG 0x506\n+\n+#define IPN3KE_10G_TX_FRAME_MAXLENGTH 0x002C\n+#define IPN3KE_10G_RX_FRAME_MAXLENGTH 0x00AE\n+\n #define IPN3KE_REGISTER_WIDTH 32\n \n /*Bits[2:0]: Configuration of TX statistics counters:\n", "prefixes": [ "v3" ] }