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GET /api/patches/58295/?format=api
{ "id": 58295, "url": "https://patches.dpdk.org/api/patches/58295/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1567146501-8224-9-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567146501-8224-9-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567146501-8224-9-git-send-email-anoobj@marvell.com", "date": "2019-08-30T06:28:18", "name": "[08/11] crypto/octeontx2: add enqueue burst", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "e39eaa733a3fd03c052a34e2a6c8a47c590ffb0d", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1567146501-8224-9-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6176, "url": "https://patches.dpdk.org/api/series/6176/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6176", "date": "2019-08-30T06:28:10", "name": "add OCTEON TX2 crypto PMD", "version": 1, "mbox": "https://patches.dpdk.org/series/6176/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/58295/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/58295/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 658111E894;\n\tFri, 30 Aug 2019 08:32:36 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id F23E41E894\n\tfor <dev@dpdk.org>; Fri, 30 Aug 2019 08:32:34 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx7U6TXx2023644; Thu, 29 Aug 2019 23:32:34 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2upmepj41c-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 29 Aug 2019 23:32:34 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 29 Aug 2019 23:32:32 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 29 Aug 2019 23:32:32 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id B10603F703F;\n\tThu, 29 Aug 2019 23:32:29 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=Xeyb05z2dsm/aCPIChDRoK7SnxOVEjEjU4Ow6Q5X6GE=;\n\tb=Av69P0gaB/lEu4j6XwPOnBfqX0+fQSIkYAGGNDvPdKj5IdDrLYOX0DAuzEtXMtd7tW1W\n\tRR+12OHAbPhGY93YBUAJf4zaNySwWJxfm3JfI44RLHCJlVbk86kWQ6eq/+9pMORDsHCI\n\tC/hJh4bSMQRkdDU5AzBh25rh39mGmIJEv+///na549XSjBez/LeaZUv4xSzUMgF2o5GA\n\tMWnwFPY9fE1qOv0M4Zt4gO8NpoeWBnBj1CZh+t18v3DlWPTfAkmVLBgtvfq1XDz+rPq8\n\tmIlNa3xU4llPj1a8hji0ZN7fdmRr0q6vTBxZWV9bnFRQoWb5beZKQRkY5Lo6TguA/clO\n\tnw== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n\tNarayana Prasad <pathreya@marvell.com>,\n\tAnkur Dwivedi <adwivedi@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Fri, 30 Aug 2019 11:58:18 +0530", "Message-ID": "<1567146501-8224-9-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "References": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0", "Subject": "[dpdk-dev] [PATCH 08/11] crypto/octeontx2: add enqueue burst", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds the enqueue burst callbacks for the OCTEON TX2\ncrypto driver. Other required functions and data structures which\nare used to enqueue the instruction to the hardware are also added.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n drivers/common/cpt/cpt_hw_types.h | 38 ++++++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 159 ++++++++++++++++++++++++++\n 2 files changed, 197 insertions(+)", "diff": "diff --git a/drivers/common/cpt/cpt_hw_types.h b/drivers/common/cpt/cpt_hw_types.h\nindex 4c2893b..4286512 100644\n--- a/drivers/common/cpt/cpt_hw_types.h\n+++ b/drivers/common/cpt/cpt_hw_types.h\n@@ -197,6 +197,44 @@ typedef union cpt_inst_s {\n \t\t};\n #endif /* Word 7 - End */\n \t} s8x;\n+\tstruct cpt_inst_s_9s {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t nixtx_addr : 60;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t nixtxl : 3;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t nixtxl : 3;\n+\t\tuint64_t doneint : 1;\n+\t\tuint64_t nixtx_addr : 60;\n+#endif /* Word 0 - End */\n+\t\tuint64_t res_addr;\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 2 - Big Endian */\n+\t\tuint64_t rvu_pf_func : 16;\n+\t\tuint64_t reserved_172_175 : 4;\n+\t\tuint64_t grp : 10;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t tag : 32;\n+#else /* Word 2 - Little Endian */\n+\t\tuint64_t tag : 32;\n+\t\tuint64_t tt : 2;\n+\t\tuint64_t grp : 10;\n+\t\tuint64_t reserved_172_175 : 4;\n+\t\tuint64_t rvu_pf_func : 16;\n+#endif /* Word 2 - End */\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 3 - Big Endian */\n+\t\tuint64_t wq_ptr : 61;\n+\t\tuint64_t reserved_194_193 : 2;\n+\t\tuint64_t qord : 1;\n+#else /* Word 3 - Little Endian */\n+\t\tuint64_t qord : 1;\n+\t\tuint64_t reserved_194_193 : 2;\n+\t\tuint64_t wq_ptr : 61;\n+#endif /* Word 3 - End */\n+\t\tuint64_t ei0;\n+\t\tuint64_t ei1;\n+\t\tuint64_t ei2;\n+\t\tuint64_t ei3;\n+\t} s9x;\n } cpt_inst_s_t;\n \n /**\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex fcfcf1a..74e6f1c 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -329,6 +329,163 @@ sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess)\n \trte_mempool_put(pool, priv);\n }\n \n+static __rte_always_inline int32_t __hot\n+otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,\n+\t\t struct pending_queue *pend_q,\n+\t\t struct cpt_request_info *req)\n+{\n+\tvoid *lmtline = qp->lmtline;\n+\tunion cpt_inst_s inst;\n+\tuint64_t lmt_status;\n+\n+\tif (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))\n+\t\treturn -EAGAIN;\n+\n+\tinst.u[0] = 0;\n+\tinst.s9x.res_addr = req->comp_baddr;\n+\tinst.u[2] = 0;\n+\tinst.u[3] = 0;\n+\n+\tinst.s9x.ei0 = req->ist.ei0;\n+\tinst.s9x.ei1 = req->ist.ei1;\n+\tinst.s9x.ei2 = req->ist.ei2;\n+\tinst.s9x.ei3 = req->ist.ei3;\n+\n+\treq->time_out = rte_get_timer_cycles() +\n+\t\t\tDEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();\n+\n+\tdo {\n+\t\t/* Copy CPT command to LMTLINE */\n+\t\tmemcpy(lmtline, &inst, sizeof(inst));\n+\n+\t\t/*\n+\t\t * Make sure compiler does not reorder memcpy and ldeor.\n+\t\t * LMTST transactions are always flushed from the write\n+\t\t * buffer immediately, a DMB is not required to push out\n+\t\t * LMTSTs.\n+\t\t */\n+\t\trte_cio_wmb();\n+\t\tlmt_status = otx2_lmt_submit(qp->lf_nq_reg);\n+\t} while (lmt_status == 0);\n+\n+\tpend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;\n+\n+\t/* We will use soft queue length here to limit requests */\n+\tMOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);\n+\tpend_q->pending_count += 1;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int __hot\n+otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n+\t\t struct pending_queue *pend_q)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct cpt_request_info *req;\n+\tstruct cpt_sess_misc *sess;\n+\tvq_cmd_word3_t *w3;\n+\tuint64_t cpt_op;\n+\tvoid *mdata;\n+\tint ret;\n+\n+\tsess = get_sym_session_private_data(sym_op->session,\n+\t\t\t\t\t otx2_cryptodev_driver_id);\n+\n+\tcpt_op = sess->cpt_op;\n+\n+\tif (cpt_op & CPT_OP_CIPHER_MASK)\n+\t\tret = fill_fc_params(op, sess, &qp->meta_info, &mdata,\n+\t\t\t\t (void **)&req);\n+\telse\n+\t\tret = fill_digest_params(op, sess, &qp->meta_info, &mdata,\n+\t\t\t\t\t (void **)&req);\n+\n+\tif (unlikely(ret)) {\n+\t\tCPT_LOG_DP_ERR(\"Crypto req : op %p, cpt_op 0x%x ret 0x%x\",\n+\t\t\t\top, (unsigned int)cpt_op, ret);\n+\t\treturn ret;\n+\t}\n+\n+\tw3 = ((vq_cmd_word3_t *)(&req->ist.ei3));\n+\tw3->s.grp = sess->egrp;\n+\n+\tret = otx2_cpt_enqueue_req(qp, pend_q, req);\n+\n+\tif (unlikely(ret)) {\n+\t\t/* Free buffer allocated by fill params routines */\n+\t\tfree_op_meta(mdata, qp->meta_info.pool);\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static __rte_always_inline int __hot\n+otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,\n+\t\t\t struct pending_queue *pend_q)\n+{\n+\tconst int driver_id = otx2_cryptodev_driver_id;\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct rte_cryptodev_sym_session *sess;\n+\tint ret;\n+\n+\t/* Create temporary session */\n+\n+\tif (rte_mempool_get(qp->sess_mp, (void **)&sess))\n+\t\treturn -ENOMEM;\n+\n+\tret = sym_session_configure(driver_id, sym_op->xform, sess,\n+\t\t\t\t qp->sess_mp_priv);\n+\tif (ret)\n+\t\tgoto sess_put;\n+\n+\tsym_op->session = sess;\n+\n+\tret = otx2_cpt_enqueue_sym(qp, op, pend_q);\n+\n+\tif (unlikely(ret))\n+\t\tgoto priv_put;\n+\n+\treturn 0;\n+\n+priv_put:\n+\tsym_session_clear(driver_id, sess);\n+sess_put:\n+\trte_mempool_put(qp->sess_mp, sess);\n+\treturn ret;\n+}\n+\n+static uint16_t\n+otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tuint16_t nb_allowed, count = 0;\n+\tstruct otx2_cpt_qp *qp = qptr;\n+\tstruct pending_queue *pend_q;\n+\tstruct rte_crypto_op *op;\n+\tint ret;\n+\n+\tpend_q = &qp->pend_q;\n+\n+\tnb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;\n+\tif (nb_ops > nb_allowed)\n+\t\tnb_ops = nb_allowed;\n+\n+\tfor (count = 0; count < nb_ops; count++) {\n+\t\top = ops[count];\n+\t\tif (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)\n+\t\t\tret = otx2_cpt_enqueue_sym(qp, op, pend_q);\n+\t\telse if (op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)\n+\t\t\tret = otx2_cpt_enqueue_sym_sessless(qp, op, pend_q);\n+\t\telse\n+\t\t\tbreak;\n+\n+\t\tif (unlikely(ret))\n+\t\t\tbreak;\n+\t}\n+\n+\treturn count;\n+}\n+\n /* PMD ops */\n \n static int\n@@ -378,6 +535,8 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev,\n \t\tgoto queues_detach;\n \t}\n \n+\tdev->enqueue_burst = otx2_cpt_enqueue_burst;\n+\n \trte_mb();\n \treturn 0;\n \n", "prefixes": [ "08/11" ] }