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GET /api/patches/58288/?format=api
{ "id": 58288, "url": "https://patches.dpdk.org/api/patches/58288/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1567146501-8224-2-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567146501-8224-2-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567146501-8224-2-git-send-email-anoobj@marvell.com", "date": "2019-08-30T06:28:11", "name": "[01/11] crypto/octeontx2: add PMD skeleton", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9ec0f26cb5bde9cd6d43bff35bfd63cfd32abb94", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1567146501-8224-2-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6176, "url": "https://patches.dpdk.org/api/series/6176/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6176", "date": "2019-08-30T06:28:10", "name": "add OCTEON TX2 crypto PMD", "version": 1, "mbox": "https://patches.dpdk.org/series/6176/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/58288/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/58288/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 162DA1E570;\n\tFri, 30 Aug 2019 08:31:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 649BB1BECA\n\tfor <dev@dpdk.org>; Fri, 30 Aug 2019 08:31:54 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx7U6UO7W027743; Thu, 29 Aug 2019 23:31:52 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg1m-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 29 Aug 2019 23:31:52 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 29 Aug 2019 23:31:50 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 29 Aug 2019 23:31:50 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id 2B0563F703F;\n\tThu, 29 Aug 2019 23:31:46 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=WcDp0ILVcGPqiiIpPNNUtESSeTlcTgXPemgymQQEzj4=;\n\tb=lCzaSRqcOrolwGOBIejVBaNX/nyYc8bVSZqiEsk3gyRuSUU6NfgC4P0WatjHK8Vcbph5\n\tDH6/cEKangKj5iPM7/jBt7VjMc2cMay1iYDa5rtEa103d/N5Uj109tXKCHAim3q7ZeNb\n\tM/iOywtQNIDKYR1wV0GhUAWVKkQ34UMyf2G3dn9MZvkgj1FCK0TMp+vJMmb48fP7Ngt3\n\tbP1GAFUUgtUH2r2sk15OjESrmo8x48lBkVAA/oTln/ldwp+CNkGdaZDsrrzsf+lRnsQM\n\tjhHm4Yq4siQ2A9qwwQINmTqfgJ1s/yhbAMUABulVbskhzsyBZ5jUWpcmvZUsZYxc4emy\n\tcw== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Ankur Dwivedi <adwivedi@marvell.com>, Jerin Jacob <jerinj@marvell.com>, \n\tNarayana Prasad <pathreya@marvell.com>, Anoob Joseph <anoobj@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Fri, 30 Aug 2019 11:58:11 +0530", "Message-ID": "<1567146501-8224-2-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "References": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0", "Subject": "[dpdk-dev] [PATCH 01/11] crypto/octeontx2: add PMD skeleton", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Ankur Dwivedi <adwivedi@marvell.com>\n\nAdding OCTEON TX2 crypto PMD skeleton. Enabling the driver by default\nin common_base.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n config/common_base | 5 +\n drivers/common/Makefile | 5 +-\n drivers/crypto/Makefile | 1 +\n drivers/crypto/meson.build | 4 +-\n drivers/crypto/octeontx2/Makefile | 37 +++++++\n drivers/crypto/octeontx2/meson.build | 29 +++++\n drivers/crypto/octeontx2/otx2_cryptodev.c | 118 +++++++++++++++++++++\n drivers/crypto/octeontx2/otx2_cryptodev.h | 25 +++++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 27 +++++\n drivers/crypto/octeontx2/otx2_cryptodev_ops.h | 12 +++\n .../octeontx2/rte_pmd_octeontx2_crypto_version.map | 4 +\n mk/rte.app.mk | 6 +-\n 12 files changed, 269 insertions(+), 4 deletions(-)\n create mode 100644 drivers/crypto/octeontx2/Makefile\n create mode 100644 drivers/crypto/octeontx2/meson.build\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.c\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev.h\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n create mode 100644 drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map", "diff": "diff --git a/config/common_base b/config/common_base\nindex 8ef75c2..b8143ea 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -593,6 +593,11 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4\n CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y\n \n #\n+# Compile PMD for Marvell OCTEON TX2 crypto device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y\n+\n+#\n # Compile PMD for QuickAssist based devices - see docs for details\n #\n CONFIG_RTE_LIBRTE_PMD_QAT=y\ndiff --git a/drivers/common/Makefile b/drivers/common/Makefile\nindex bc6f972..1ff033b 100644\n--- a/drivers/common/Makefile\n+++ b/drivers/common/Makefile\n@@ -4,7 +4,9 @@\n \n include $(RTE_SDK)/mk/rte.vars.mk\n \n-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)\n+CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)\n+CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n+ifneq (,$(findstring y,$(CPT-y)))\n DIRS-y += cpt\n endif\n \n@@ -12,6 +14,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO\n DIRS-y += octeontx\n endif\n OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)\n+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n ifeq ($(findstring y,$(OCTEONTX2-y)),y)\n DIRS-y += octeontx2\n endif\ndiff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile\nindex 009f844..0ac999c 100644\n--- a/drivers/crypto/Makefile\n+++ b/drivers/crypto/Makefile\n@@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += octeontx2\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g\ndiff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build\nindex 83e7886..3c88f3c 100644\n--- a/drivers/crypto/meson.build\n+++ b/drivers/crypto/meson.build\n@@ -2,8 +2,8 @@\n # Copyright(c) 2017 Intel Corporation\n \n drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',\n-\t'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler',\n-\t'snow3g', 'virtio', 'zuc']\n+\t'kasumi', 'mvsam', 'null', 'octeontx', 'octeontx2', 'openssl', 'qat',\n+\t'scheduler', 'snow3g', 'virtio', 'zuc']\n \n std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps\n config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'\ndiff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile\nnew file mode 100644\nindex 0000000..3273178\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/Makefile\n@@ -0,0 +1,37 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (C) 2019 Marvell International Ltd.\n+#\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+# library name\n+LIB = librte_pmd_octeontx2_crypto.a\n+\n+# library version\n+LIBABIVER := 1\n+\n+# build flags\n+CFLAGS += $(WERROR_FLAGS)\n+\n+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring\n+LDLIBS += -lrte_cryptodev\n+LDLIBS += -lrte_pci -lrte_bus_pci\n+LDLIBS += -lrte_common_cpt -lrte_common_octeontx2\n+\n+VPATH += $(RTE_SDK)/drivers/crypto/octeontx2\n+\n+CFLAGS += -O3\n+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt\n+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n+\n+# PMD code\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c\n+\n+# export include files\n+SYMLINK-y-include +=\n+\n+# versioning export map\n+EXPORT_MAP := rte_pmd_octeontx2_crypto_version.map\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build\nnew file mode 100644\nindex 0000000..2b55d2a\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/meson.build\n@@ -0,0 +1,29 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (C) 2019 Marvell International Ltd.\n+\n+if host_machine.system() != 'linux'\n+ build = false\n+endif\n+\n+deps += ['bus_pci']\n+deps += ['common_cpt']\n+deps += ['common_octeontx2']\n+name = 'octeontx2_crypto'\n+\n+sources = files('otx2_cryptodev.c',\n+\t\t'otx2_cryptodev_ops.c')\n+\n+extra_flags = []\n+# This integrated controller runs only on a arm64 machine, remove 32bit warnings\n+if not dpdk_conf.get('RTE_ARCH_64')\n+\textra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']\n+endif\n+\n+foreach flag: extra_flags\n+\tif cc.has_argument(flag)\n+\t\tcflags += flag\n+\tendif\n+endforeach\n+\n+includes += include_directories('../../common/cpt')\n+includes += include_directories('../../common/octeontx2')\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c\nnew file mode 100644\nindex 0000000..cf3a010\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c\n@@ -0,0 +1,118 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+#include <rte_dev.h>\n+#include <rte_errno.h>\n+#include <rte_mempool.h>\n+#include <rte_pci.h>\n+\n+/* CPT common headers */\n+#include \"cpt_common.h\"\n+#include \"cpt_pmd_logs.h\"\n+\n+#include \"otx2_common.h\"\n+#include \"otx2_cryptodev.h\"\n+#include \"otx2_cryptodev_ops.h\"\n+\n+static int otx2_cryptodev_logtype;\n+\n+static struct rte_pci_id pci_id_cpt_table[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\t PCI_DEVID_OCTEONTX2_RVU_CPT_VF)\n+\t},\n+\t/* sentinel */\n+\t{\n+\t\t.device_id = 0\n+\t},\n+};\n+\n+static int\n+otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\t struct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_cryptodev_pmd_init_params init_params = {\n+\t\t.name = \"\",\n+\t\t.socket_id = rte_socket_id(),\n+\t\t.private_data_size = sizeof(struct otx2_cpt_vf)\n+\t};\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\tstruct rte_cryptodev *dev;\n+\tint ret;\n+\n+\t/* Initialize logtype used in common */\n+\tcpt_logtype = otx2_cryptodev_logtype;\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\n+\tdev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params);\n+\tif (dev == NULL) {\n+\t\tret = -ENODEV;\n+\t\tgoto exit;\n+\t}\n+\n+\tdev->dev_ops = &otx2_cpt_ops;\n+\n+\tdev->driver_id = otx2_cryptodev_driver_id;\n+\n+\tdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\n+\t\t\t RTE_CRYPTODEV_FF_HW_ACCELERATED |\n+\t\t\t RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |\n+\t\t\t RTE_CRYPTODEV_FF_IN_PLACE_SGL |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |\n+\t\t\t RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;\n+\n+\treturn 0;\n+\n+exit:\n+\tCPT_LOG_ERR(\"Could not create device (vendor_id: 0x%x device_id: 0x%x)\",\n+\t\t pci_dev->id.vendor_id, pci_dev->id.device_id);\n+\treturn ret;\n+}\n+\n+static int\n+otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\tchar name[RTE_CRYPTODEV_NAME_MAX_LEN];\n+\tstruct rte_cryptodev *dev;\n+\n+\tif (pci_dev == NULL)\n+\t\treturn -EINVAL;\n+\n+\trte_pci_device_name(&pci_dev->addr, name, sizeof(name));\n+\n+\tdev = rte_cryptodev_pmd_get_named_dev(name);\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\treturn rte_cryptodev_pmd_destroy(dev);\n+}\n+\n+static struct rte_pci_driver otx2_cryptodev_pmd = {\n+\t.id_table = pci_id_cpt_table,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = otx2_cpt_pci_probe,\n+\t.remove = otx2_cpt_pci_remove,\n+};\n+\n+static struct cryptodev_driver otx2_cryptodev_drv;\n+\n+RTE_INIT(otx2_cpt_init_log);\n+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);\n+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,\n+\t\totx2_cryptodev_driver_id);\n+\n+RTE_INIT(otx2_cpt_init_log)\n+{\n+\t/* Bus level logs */\n+\totx2_cryptodev_logtype = rte_log_register(\"pmd.crypto.octeontx2\");\n+\tif (otx2_cryptodev_logtype >= 0)\n+\t\trte_log_set_level(otx2_cryptodev_logtype, RTE_LOG_NOTICE);\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h\nnew file mode 100644\nindex 0000000..da0f653\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CRYPTODEV_H_\n+#define _OTX2_CRYPTODEV_H_\n+\n+#include \"cpt_common.h\"\n+\n+/* Marvell OCTEON TX2 Crypto PMD device name */\n+#define CRYPTODEV_NAME_OCTEONTX2_PMD\tcrypto_octeontx2\n+\n+/**\n+ * Device private data\n+ */\n+struct otx2_cpt_vf {\n+\t/* To be populated */\n+};\n+\n+/*\n+ * Crypto device driver ID\n+ */\n+uint8_t otx2_cryptodev_driver_id;\n+\n+#endif /* _OTX2_CRYPTODEV_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nnew file mode 100644\nindex 0000000..18ad470\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -0,0 +1,27 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_cryptodev_pmd.h>\n+\n+#include \"otx2_cryptodev_ops.h\"\n+\n+struct rte_cryptodev_ops otx2_cpt_ops = {\n+\t/* Device control ops */\n+\t.dev_configure = NULL,\n+\t.dev_start = NULL,\n+\t.dev_stop = NULL,\n+\t.dev_close = NULL,\n+\t.dev_infos_get = NULL,\n+\n+\t.stats_get = NULL,\n+\t.stats_reset = NULL,\n+\t.queue_pair_setup = NULL,\n+\t.queue_pair_release = NULL,\n+\t.queue_pair_count = NULL,\n+\n+\t/* Symmetric crypto ops */\n+\t.sym_session_get_size = NULL,\n+\t.sym_session_configure = NULL,\n+\t.sym_session_clear = NULL,\n+};\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\nnew file mode 100644\nindex 0000000..545614e\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h\n@@ -0,0 +1,12 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _OTX2_CRYPTODEV_OPS_H_\n+#define _OTX2_CRYPTODEV_OPS_H_\n+\n+#include <rte_cryptodev_pmd.h>\n+\n+struct rte_cryptodev_ops otx2_cpt_ops;\n+\n+#endif /* _OTX2_CRYPTODEV_OPS_H_ */\ndiff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\nnew file mode 100644\nindex 0000000..9a61188\n--- /dev/null\n+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map\n@@ -0,0 +1,4 @@\n+DPDK_19.08 {\n+\n+\tlocal: *;\n+};\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex ba5c39e..f85e50e 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -101,7 +101,9 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUX),y)\n _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI) += -lrte_kni\n endif\n \n-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)\n+OTX-CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)\n+OTX-CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n+ifeq ($(findstring y,$(OTX-CPT-y)),y)\n _LDLIBS-y += -lrte_common_cpt\n endif\n \n@@ -109,6 +111,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO\n _LDLIBS-y += -lrte_common_octeontx\n endif\n OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)\n+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV)\n OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD)\n@@ -268,6 +271,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -lrte_pmd_armv8\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += -lrte_pmd_octeontx2_crypto\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler\n ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y)\n ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)\n", "prefixes": [ "01/11" ] }