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GET /api/patches/58271/?format=api
{ "id": 58271, "url": "https://patches.dpdk.org/api/patches/58271/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190829102737.13267-22-sachin.saxena@nxp.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190829102737.13267-22-sachin.saxena@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190829102737.13267-22-sachin.saxena@nxp.com", "date": "2019-08-29T10:27:28", "name": "[v2,21/30] net/dpaa2: add Tx confirmation mode support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b95229fb52fe1f0743804946b84ca47f47f4cee9", "submitter": { "id": 1054, "url": "https://patches.dpdk.org/api/people/1054/?format=api", "name": "Sachin Saxena", "email": "sachin.saxena@nxp.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190829102737.13267-22-sachin.saxena@nxp.com/mbox/", "series": [ { "id": 6169, "url": "https://patches.dpdk.org/api/series/6169/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6169", "date": "2019-08-29T10:27:07", "name": "Enhancements and fixes in NXP dpaax drivers and fsl-mc bus", "version": 2, "mbox": "https://patches.dpdk.org/series/6169/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/58271/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/58271/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F06DC1E893;\n\tThu, 29 Aug 2019 12:42:52 +0200 (CEST)", "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n\tby dpdk.org (Postfix) with ESMTP id 6314B1D426\n\tfor <dev@dpdk.org>; Thu, 29 Aug 2019 12:41:58 +0200 (CEST)", "from inva021.nxp.com (localhost [127.0.0.1])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 46B6C20032C;\n\tThu, 29 Aug 2019 12:41:58 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 0D8D1200769;\n\tThu, 29 Aug 2019 12:41:56 +0200 (CEST)", "from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 0C8A5402E7;\n\tThu, 29 Aug 2019 18:41:52 +0800 (SGT)" ], "From": "Sachin Saxena <sachin.saxena@nxp.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net,\n\tPriyanka Jain <priyanka.jain@nxp.com>", "Date": "Thu, 29 Aug 2019 15:57:28 +0530", "Message-Id": "<20190829102737.13267-22-sachin.saxena@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190829102737.13267-1-sachin.saxena@nxp.com>", "References": "<20190827070730.11206-1-sachin.saxena@nxp.com>\n\t<20190829102737.13267-1-sachin.saxena@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[dpdk-dev] [PATCH v2 21/30] net/dpaa2: add Tx confirmation mode\n\tsupport", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Priyanka Jain <priyanka.jain@nxp.com>\n\nTX confirmation mode provides dedicated confirmation\nqueues for transmitted packets. These queues are used\nby software to get the status and release\ntransmitted packets buffers.\n\nBy default TX confirmation mode is kept disabled.\n\nSigned-off-by: Priyanka Jain <priyanka.jain@nxp.com>\n---\n drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 2 +\n drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h | 22 ++++\n drivers/net/dpaa2/dpaa2_ethdev.c | 101 ++++++++++++++++--\n drivers/net/dpaa2/dpaa2_ethdev.h | 4 +-\n drivers/net/dpaa2/dpaa2_rxtx.c | 106 ++++++++++++++++++-\n 5 files changed, 227 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\nindex 7f7e2fd78..5087f68c6 100644\n--- a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n+++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h\n@@ -161,6 +161,8 @@ struct dpaa2_queue {\n \tdpaa2_queue_cb_dqrr_t *cb;\n \tdpaa2_queue_cb_eqresp_free_t *cb_eqresp_free;\n \tstruct dpaa2_bp_info *bp_array;\n+\t/*to store tx_conf_queue corresponding to tx_queue*/\n+\tstruct dpaa2_queue *tx_conf_queue;\n };\n \n struct swp_active_dqs {\ndiff --git a/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h\nindex adb730b71..0d6324183 100644\n--- a/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h\n+++ b/drivers/net/dpaa2/base/dpaa2_hw_dpni_annot.h\n@@ -253,6 +253,28 @@ struct dpaa2_annot_hdr {\n #define PARSE_ERROR_CODE(var)\t\t((uint64_t)(var) & 0xFF00000000000000)\n #define SOFT_PARSING_CONTEXT(var)\t((uint64_t)(var) & 0x00FFFFFFFFFFFFFF)\n \n+/*FAEAD offset in anmotation area*/\n+#define DPAA2_FD_HW_ANNOT_FAEAD_OFFSET\t0x58\n+\n+struct dpaa2_faead {\n+\tuint32_t fqid;\n+\tuint32_t ctrl;\n+};\n+\n+/*FAEAD bits */\n+/*A2 OMB contains valid data*/\n+#define DPAA2_ANNOT_FAEAD_A2V\t\t0x20000000\n+/*egress confirmation FQID in FAEAD contains valid data*/\n+#define DPAA2_ANNOT_FAEAD_A4V\t\t0x08000000\n+/*UPD is valid*/\n+#define DPAA2_ANNOT_FAEAD_UPDV\t\t0x00001000\n+/*EBDD is valid*/\n+#define DPAA2_ANNOT_FAEAD_EBDDV\t\t0x00002000\n+/*EBDD (External Buffer Deallocation Disable) */\n+#define DPAA2_ANNOT_FAEAD_EBDD\t\t0x00000020\n+/*UPD (Update prepended data)*/\n+#define DPAA2_ANNOT_FAEAD_UPD\t\t0x00000010\n+\n /* Debug frame, otherwise supposed to be discarded */\n #define DPAA2_ETH_FAS_DISC\t 0x80000000\n /* MACSEC frame */\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c\nindex 29f0bfdf2..a3af9588e 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.c\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.c\n@@ -290,7 +290,10 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)\n \tPMD_INIT_FUNC_TRACE();\n \n \tnum_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);\n-\ttot_queues = priv->nb_rx_queues + priv->nb_tx_queues;\n+\tif (priv->tx_conf_en)\n+\t\ttot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;\n+\telse\n+\t\ttot_queues = priv->nb_rx_queues + priv->nb_tx_queues;\n \tmc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,\n \t\t\t RTE_CACHE_LINE_SIZE);\n \tif (!mc_q) {\n@@ -325,6 +328,28 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)\n \t\t\tgoto fail_tx;\n \t}\n \n+\tif (priv->tx_conf_en) {\n+\t\t/*Setup tx confirmation queues*/\n+\t\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n+\t\t\tmc_q->eth_data = dev->data;\n+\t\t\tmc_q->tc_index = i;\n+\t\t\tmc_q->flow_id = 0;\n+\t\t\tpriv->tx_conf_vq[i] = mc_q++;\n+\t\t\tdpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];\n+\t\t\tdpaa2_q->q_storage =\n+\t\t\t\trte_malloc(\"dq_storage\",\n+\t\t\t\t\tsizeof(struct queue_storage_info_t),\n+\t\t\t\t\tRTE_CACHE_LINE_SIZE);\n+\t\t\tif (!dpaa2_q->q_storage)\n+\t\t\t\tgoto fail_tx_conf;\n+\n+\t\t\tmemset(dpaa2_q->q_storage, 0,\n+\t\t\t sizeof(struct queue_storage_info_t));\n+\t\t\tif (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))\n+\t\t\t\tgoto fail_tx_conf;\n+\t\t}\n+\t}\n+\n \tvq_id = 0;\n \tfor (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {\n \t\tmcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];\n@@ -334,6 +359,14 @@ dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)\n \t}\n \n \treturn 0;\n+fail_tx_conf:\n+\ti -= 1;\n+\twhile (i >= 0) {\n+\t\tdpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];\n+\t\trte_free(dpaa2_q->q_storage);\n+\t\tpriv->tx_conf_vq[i--] = NULL;\n+\t}\n+\ti = priv->nb_tx_queues;\n fail_tx:\n \ti -= 1;\n \twhile (i >= 0) {\n@@ -377,6 +410,14 @@ dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)\n \t\t\tdpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];\n \t\t\trte_free(dpaa2_q->cscn);\n \t\t}\n+\t\tif (priv->tx_conf_en) {\n+\t\t\t/* cleanup tx conf queue storage */\n+\t\t\tfor (i = 0; i < priv->nb_tx_queues; i++) {\n+\t\t\t\tdpaa2_q = (struct dpaa2_queue *)\n+\t\t\t\t\t\tpriv->tx_conf_vq[i];\n+\t\t\t\trte_free(dpaa2_q->q_storage);\n+\t\t\t}\n+\t\t}\n \t\t/*free memory for all queues (RX+TX) */\n \t\trte_free(priv->rx_vq[0]);\n \t\tpriv->rx_vq[0] = NULL;\n@@ -673,6 +714,8 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,\n \tstruct dpaa2_dev_priv *priv = dev->data->dev_private;\n \tstruct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)\n \t\tpriv->tx_vq[tx_queue_id];\n+\tstruct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)\n+\t\tpriv->tx_conf_vq[tx_queue_id];\n \tstruct fsl_mc_io *dpni = priv->hw;\n \tstruct dpni_queue tx_conf_cfg;\n \tstruct dpni_queue tx_flow_cfg;\n@@ -708,9 +751,14 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,\n \n \tif (tx_queue_id == 0) {\n \t\t/*Set tx-conf and error configuration*/\n-\t\tret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,\n-\t\t\t\t\t\t priv->token,\n-\t\t\t\t\t\t DPNI_CONF_DISABLE);\n+\t\tif (priv->tx_conf_en)\n+\t\t\tret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,\n+\t\t\t\t\t\t\t priv->token,\n+\t\t\t\t\t\t\t DPNI_CONF_AFFINE);\n+\t\telse\n+\t\t\tret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,\n+\t\t\t\t\t\t\t priv->token,\n+\t\t\t\t\t\t\t DPNI_CONF_DISABLE);\n \t\tif (ret) {\n \t\t\tDPAA2_PMD_ERR(\"Error in set tx conf mode settings: \"\n \t\t\t\t \"err=%d\", ret);\n@@ -761,6 +809,31 @@ dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,\n \t}\n \tdpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;\n \tdev->data->tx_queues[tx_queue_id] = dpaa2_q;\n+\n+\tif (priv->tx_conf_en) {\n+\t\tdpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;\n+\t\toptions = options | DPNI_QUEUE_OPT_USER_CTX;\n+\t\ttx_conf_cfg.user_context = (size_t)(dpaa2_q);\n+\t\tret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,\n+\t\t\t dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);\n+\t\tif (ret) {\n+\t\t\tDPAA2_PMD_ERR(\"Error in setting the tx conf flow: \"\n+\t\t\t \"tc_index=%d, flow=%d err=%d\",\n+\t\t\t dpaa2_tx_conf_q->tc_index,\n+\t\t\t dpaa2_tx_conf_q->flow_id, ret);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,\n+\t\t\t DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,\n+\t\t\t dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);\n+\t\tif (ret) {\n+\t\t\tDPAA2_PMD_ERR(\"Error in getting LFQID err=%d\", ret);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tdpaa2_tx_conf_q->fqid = qid.fqid;\n+\t}\n \treturn 0;\n }\n \n@@ -2337,7 +2410,13 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)\n \n \t/* ... tx buffer layout ... */\n \tmemset(&layout, 0, sizeof(struct dpni_buffer_layout));\n-\tlayout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;\n+\tif (priv->tx_conf_en) {\n+\t\tlayout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |\n+\t\t\t\t DPNI_BUF_LAYOUT_OPT_TIMESTAMP;\n+\t\tlayout.pass_timestamp = true;\n+\t} else {\n+\t\tlayout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;\n+\t}\n \tlayout.pass_frame_status = 1;\n \tret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,\n \t\t\t\t DPNI_QUEUE_TX, &layout);\n@@ -2348,7 +2427,13 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)\n \n \t/* ... tx-conf and error buffer layout ... */\n \tmemset(&layout, 0, sizeof(struct dpni_buffer_layout));\n-\tlayout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;\n+\tif (priv->tx_conf_en) {\n+\t\tlayout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |\n+\t\t\t\t DPNI_BUF_LAYOUT_OPT_TIMESTAMP;\n+\t\tlayout.pass_timestamp = true;\n+\t} else {\n+\t\tlayout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;\n+\t}\n \tlayout.pass_frame_status = 1;\n \tret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,\n \t\t\t\t DPNI_QUEUE_TX_CONFIRM, &layout);\n@@ -2460,6 +2545,7 @@ rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,\n \t\tstruct rte_dpaa2_device *dpaa2_dev)\n {\n \tstruct rte_eth_dev *eth_dev;\n+\tstruct dpaa2_dev_priv *priv;\n \tint diag;\n \n \tif ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >\n@@ -2507,6 +2593,9 @@ rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,\n \t\treturn 0;\n \t}\n \n+\tpriv = eth_dev->data->dev_private;\n+\tpriv->tx_conf_en = 0;\n+\n \trte_eth_dev_release_port(eth_dev);\n \treturn diag;\n }\ndiff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h\nindex 2f14a3525..04a8ef8da 100644\n--- a/drivers/net/dpaa2/dpaa2_ethdev.h\n+++ b/drivers/net/dpaa2/dpaa2_ethdev.h\n@@ -107,8 +107,9 @@ struct dpaa2_dev_priv {\n \tuint32_t options;\n \tvoid *rx_vq[MAX_RX_QUEUES];\n \tvoid *tx_vq[MAX_TX_QUEUES];\n-\n \tstruct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */\n+\tvoid *tx_conf_vq[MAX_TX_QUEUES];\n+\tuint8_t tx_conf_en;\n \tuint8_t max_mac_filters;\n \tuint8_t max_vlan_filters;\n \tuint8_t num_rx_tc;\n@@ -179,5 +180,6 @@ uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs,\n uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts);\n void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci);\n void dpaa2_flow_clean(struct rte_eth_dev *dev);\n+uint16_t dpaa2_dev_tx_conf(void *queue) __attribute__((unused));\n \n #endif /* _DPAA2_ETHDEV_H */\ndiff --git a/drivers/net/dpaa2/dpaa2_rxtx.c b/drivers/net/dpaa2/dpaa2_rxtx.c\nindex 2209b78a4..1c14b7354 100644\n--- a/drivers/net/dpaa2/dpaa2_rxtx.c\n+++ b/drivers/net/dpaa2/dpaa2_rxtx.c\n@@ -1,7 +1,7 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n *\n * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.\n- * Copyright 2016-2018 NXP\n+ * Copyright 2016-2019 NXP\n *\n */\n \n@@ -832,6 +832,110 @@ dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts)\n \treturn num_rx;\n }\n \n+uint16_t dpaa2_dev_tx_conf(void *queue)\n+{\n+\t/* Function receive frames for a given device and VQ */\n+\tstruct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue;\n+\tstruct qbman_result *dq_storage;\n+\tuint32_t fqid = dpaa2_q->fqid;\n+\tint ret, num_tx_conf = 0, num_pulled;\n+\tuint8_t pending, status;\n+\tstruct qbman_swp *swp;\n+\tconst struct qbman_fd *fd, *next_fd;\n+\tstruct qbman_pull_desc pulldesc;\n+\tstruct qbman_release_desc releasedesc;\n+\tuint32_t bpid;\n+\tuint64_t buf;\n+\n+\tif (unlikely(!DPAA2_PER_LCORE_DPIO)) {\n+\t\tret = dpaa2_affine_qbman_swp();\n+\t\tif (ret) {\n+\t\t\tDPAA2_PMD_ERR(\"Failure in affining portal\\n\");\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\tswp = DPAA2_PER_LCORE_PORTAL;\n+\n+\tdo {\n+\t\tdq_storage = dpaa2_q->q_storage->dq_storage[0];\n+\t\tqbman_pull_desc_clear(&pulldesc);\n+\t\tqbman_pull_desc_set_fq(&pulldesc, fqid);\n+\t\tqbman_pull_desc_set_storage(&pulldesc, dq_storage,\n+\t\t\t\t(size_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1);\n+\n+\t\tqbman_pull_desc_set_numframes(&pulldesc, dpaa2_dqrr_size);\n+\n+\t\twhile (1) {\n+\t\t\tif (qbman_swp_pull(swp, &pulldesc)) {\n+\t\t\t\tDPAA2_PMD_DP_DEBUG(\"VDQ command is not issued.\"\n+\t\t\t\t\t\t \"QBMAN is busy\\n\");\n+\t\t\t\t/* Portal was busy, try again */\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\trte_prefetch0((void *)((size_t)(dq_storage + 1)));\n+\t\t/* Check if the previous issued command is completed. */\n+\t\twhile (!qbman_check_command_complete(dq_storage))\n+\t\t\t;\n+\n+\t\tnum_pulled = 0;\n+\t\tpending = 1;\n+\t\tdo {\n+\t\t\t/* Loop until the dq_storage is updated with\n+\t\t\t * new token by QBMAN\n+\t\t\t */\n+\t\t\twhile (!qbman_check_new_result(dq_storage))\n+\t\t\t\t;\n+\t\t\trte_prefetch0((void *)((size_t)(dq_storage + 2)));\n+\t\t\t/* Check whether Last Pull command is Expired and\n+\t\t\t * setting Condition for Loop termination\n+\t\t\t */\n+\t\t\tif (qbman_result_DQ_is_pull_complete(dq_storage)) {\n+\t\t\t\tpending = 0;\n+\t\t\t\t/* Check for valid frame. */\n+\t\t\t\tstatus = qbman_result_DQ_flags(dq_storage);\n+\t\t\t\tif (unlikely((status &\n+\t\t\t\t\tQBMAN_DQ_STAT_VALIDFRAME) == 0))\n+\t\t\t\t\tcontinue;\n+\t\t\t}\n+\t\t\tfd = qbman_result_DQ_fd(dq_storage);\n+\n+\t\t\tnext_fd = qbman_result_DQ_fd(dq_storage + 1);\n+\t\t\t/* Prefetch Annotation address for the parse results */\n+\t\t\trte_prefetch0((void *)(size_t)\n+\t\t\t\t(DPAA2_GET_FD_ADDR(next_fd) +\n+\t\t\t\t DPAA2_FD_PTA_SIZE + 16));\n+\n+\t\t\tbpid = DPAA2_GET_FD_BPID(fd);\n+\n+\t\t\t/* Create a release descriptor required for releasing\n+\t\t\t * buffers into QBMAN\n+\t\t\t */\n+\t\t\tqbman_release_desc_clear(&releasedesc);\n+\t\t\tqbman_release_desc_set_bpid(&releasedesc, bpid);\n+\n+\t\t\tbuf = DPAA2_GET_FD_ADDR(fd);\n+\t\t\t/* feed them to bman */\n+\t\t\tdo {\n+\t\t\t\tret = qbman_swp_release(swp, &releasedesc,\n+\t\t\t\t\t\t\t&buf, 1);\n+\t\t\t} while (ret == -EBUSY);\n+\n+\t\t\tdq_storage++;\n+\t\t\tnum_tx_conf++;\n+\t\t\tnum_pulled++;\n+\t\t} while (pending);\n+\n+\t/* Last VDQ provided all packets and more packets are requested */\n+\t} while (num_pulled == dpaa2_dqrr_size);\n+\n+\tdpaa2_q->rx_pkts += num_tx_conf;\n+\n+\treturn num_tx_conf;\n+}\n+\n /*\n * Callback to handle sending packets through WRIOP based interface\n */\n", "prefixes": [ "v2", "21/30" ] }