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GET /api/patches/57953/?format=api
{ "id": 57953, "url": "https://patches.dpdk.org/api/patches/57953/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-58-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-58-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-58-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:59", "name": "[57/63] net/ice/base: delay less", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "e284899c9317a8a2d3399f457b70a4e2c1a3e493", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-58-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "https://patches.dpdk.org/api/series/6119/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "https://patches.dpdk.org/series/6119/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57953/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/57953/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 9CB6B1C113;\n\tMon, 26 Aug 2019 12:51:49 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby dpdk.org (Postfix) with ESMTP id 94E101BFE3\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:50:09 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:50:09 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:50:07 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402611\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tMitch Williams <mitch.a.williams@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:59 +0800", "Message-Id": "<20190826105105.19121-58-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 57/63] net/ice/base: delay less", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Shorten the delay for SQ responses, but increase the number of loops.\nMax delay time is unchanged, but some operations complete much more\nquickly.\n\nIn the process, add a new define to make the delay count and delay time\nmore explicit, and simplify the code so it's the same for both switch\nand NIC mode. Add comments to make things more explicit.\n\nSigned-off-by: Mitch Williams <mitch.a.williams@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_controlq.c | 2 +-\n drivers/net/ice/base/ice_controlq.h | 5 +++--\n drivers/net/ice/base/ice_osdep.h | 2 +-\n 3 files changed, 5 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c\nindex 501f986b9..1ea8f3a24 100644\n--- a/drivers/net/ice/base/ice_controlq.c\n+++ b/drivers/net/ice/base/ice_controlq.c\n@@ -982,7 +982,7 @@ ice_sq_send_cmd_nolock(struct ice_hw *hw, struct ice_ctl_q_info *cq,\n \t\tif (ice_sq_done(hw, cq))\n \t\t\tbreak;\n \n-\t\tice_msec_delay(1, false);\n+\t\tice_usec_delay(ICE_CTL_Q_SQ_CMD_USEC, false);\n \t\ttotal_delay++;\n \t} while (total_delay < cq->sq_cmd_timeout);\n \ndiff --git a/drivers/net/ice/base/ice_controlq.h b/drivers/net/ice/base/ice_controlq.h\nindex acb4ab49e..b1214f670 100644\n--- a/drivers/net/ice/base/ice_controlq.h\n+++ b/drivers/net/ice/base/ice_controlq.h\n@@ -33,8 +33,9 @@ enum ice_ctl_q {\n \tICE_CTL_Q_MAILBOX,\n };\n \n-/* Control Queue default settings */\n-#define ICE_CTL_Q_SQ_CMD_TIMEOUT\t250 /* msecs */\n+/* Control Queue timeout settings - max delay 250ms */\n+#define ICE_CTL_Q_SQ_CMD_TIMEOUT\t2500 /* Count 2500 times */\n+#define ICE_CTL_Q_SQ_CMD_USEC\t\t100 /* Check every 100usec */\n \n struct ice_ctl_q_ring {\n \tvoid *dma_head;\t\t\t/* Virtual address to DMA head */\ndiff --git a/drivers/net/ice/base/ice_osdep.h b/drivers/net/ice/base/ice_osdep.h\nindex 35a17b941..27c1830c5 100644\n--- a/drivers/net/ice/base/ice_osdep.h\n+++ b/drivers/net/ice/base/ice_osdep.h\n@@ -292,7 +292,7 @@ ice_hweight32(u32 num)\n \n #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n #define DELAY(x) rte_delay_us(x)\n-#define ice_usec_delay(x) rte_delay_us(x)\n+#define ice_usec_delay(x, y) rte_delay_us(x)\n #define ice_msec_delay(x, y) rte_delay_us(1000 * (x))\n #define udelay(x) DELAY(x)\n #define msleep(x) DELAY(1000 * (x))\n", "prefixes": [ "57/63" ] }