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GET /api/patches/57944/?format=api
{ "id": 57944, "url": "https://patches.dpdk.org/api/patches/57944/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-44-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-44-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-44-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:45", "name": "[43/63] net/ice/base: ptype group consolidation", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "68773bb3fd50651e106f61f3d61d9c0344d59bbf", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-44-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "https://patches.dpdk.org/api/series/6119/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "https://patches.dpdk.org/series/6119/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57944/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/57944/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D36C81C1EF;\n\tMon, 26 Aug 2019 12:50:57 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 8667A1C12A\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:49:44 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:49:44 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:49:42 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402433\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tDan Nowlin <dan.nowlin@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:45 +0800", "Message-Id": "<20190826105105.19121-44-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 43/63] net/ice/base: ptype group consolidation", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch is an optimization to decrease the number of TCAM entries\nused in the profile blocks, especially for RSS. To be most effective\nthis will also require a package change in order to decrease the number\nof PTYPE groups necessary to program RSS, FD and ACL rules.\n\nSigned-off-by: Dan Nowlin <dan.nowlin@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_flex_pipe.c | 214 ++++++++++++++---------------------\n drivers/net/ice/base/ice_flex_pipe.h | 2 +-\n drivers/net/ice/base/ice_flex_type.h | 8 +-\n 3 files changed, 89 insertions(+), 135 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 8161ccaec..6ae71e698 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -2121,29 +2121,6 @@ void ice_ptg_alloc_val(struct ice_hw *hw, enum ice_block blk, u8 ptg)\n \thw->blk[blk].xlt1.ptg_tbl[ptg].in_use = true;\n }\n \n-/**\n- * ice_ptg_alloc - Find a free entry and allocates a new packet type group ID\n- * @hw: pointer to the hardware structure\n- * @blk: HW block\n- *\n- * This function allocates and returns a new packet type group ID. Note\n- * that 0 is the default packet type group, so successfully created PTGs will\n- * have a non-zero ID value; which means a 0 return value indicates an error.\n- */\n-static u8 ice_ptg_alloc(struct ice_hw *hw, enum ice_block blk)\n-{\n-\tu16 i;\n-\n-\t/* Skip the default PTG of 0 */\n-\tfor (i = 1; i < ICE_MAX_PTGS; i++)\n-\t\tif (!hw->blk[blk].xlt1.ptg_tbl[i].in_use) {\n-\t\t\t/* found a free PTG ID */\n-\t\t\tice_ptg_alloc_val(hw, blk, i);\n-\t\t\treturn (u8)i;\n-\t\t}\n-\n-\treturn 0;\n-}\n \n /**\n * ice_ptg_remove_ptype - Removes ptype from a particular packet type group\n@@ -3884,43 +3861,6 @@ ice_vsig_get_ref(struct ice_hw *hw, enum ice_block blk, u16 vsig, u16 *refs)\n }\n \n /**\n- * ice_get_ptg - get or allocate a ptg for a ptype\n- * @hw: pointer to the hardware structure\n- * @blk: HW block\n- * @ptype: the ptype to retrieve the PTG for\n- * @ptg: receives the PTG of the ptype\n- * @add: receive boolean indicating whether PTG was added or not\n- */\n-static enum ice_status\n-ice_get_ptg(struct ice_hw *hw, enum ice_block blk, u16 ptype, u8 *ptg,\n-\t bool *add)\n-{\n-\tenum ice_status status;\n-\n-\t*ptg = ICE_DEFAULT_PTG;\n-\t*add = false;\n-\n-\tstatus = ice_ptg_find_ptype(hw, blk, ptype, ptg);\n-\tif (status)\n-\t\treturn status;\n-\n-\tif (*ptg == ICE_DEFAULT_PTG) {\n-\t\t/* need to allocate a PTG, and add ptype to it */\n-\t\t*ptg = ice_ptg_alloc(hw, blk);\n-\t\tif (*ptg == ICE_DEFAULT_PTG)\n-\t\t\treturn ICE_ERR_HW_TABLE;\n-\n-\t\tstatus = ice_ptg_add_mv_ptype(hw, blk, ptype, *ptg);\n-\t\tif (status)\n-\t\t\treturn ICE_ERR_HW_TABLE;\n-\n-\t\t*add = true;\n-\t}\n-\n-\treturn ICE_SUCCESS;\n-};\n-\n-/**\n * ice_has_prof_vsig - check to see if VSIG has a specific profile\n * @hw: pointer to the hardware structure\n * @blk: HW block\n@@ -4420,11 +4360,14 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,\n \t\t u8 ptypes[], struct ice_fv_word *es, u16 *masks)\n {\n \tu32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);\n+\tice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);\n \tstruct ice_prof_map *prof;\n \tenum ice_status status;\n \tu32 byte = 0;\n \tu8 prof_id;\n \n+\tice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);\n+\n \tice_acquire_lock(&hw->blk[blk].es.prof_map_lock);\n \n \t/* search for existing profile */\n@@ -4464,11 +4407,11 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,\n \n \tprof->profile_cookie = id;\n \tprof->prof_id = prof_id;\n-\tprof->ptype_count = 0;\n+\tprof->ptg_cnt = 0;\n \tprof->context = 0;\n \n \t/* build list of ptgs */\n-\twhile (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {\n+\twhile (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {\n \t\tu32 bit;\n \n \t\tif (!ptypes[byte]) {\n@@ -4480,16 +4423,27 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,\n \t\tfor (bit = 0; bit < 8; bit++) {\n \t\t\tif (ptypes[byte] & BIT(bit)) {\n \t\t\t\tu16 ptype;\n+\t\t\t\tu8 ptg;\n \t\t\t\tu8 m;\n \n \t\t\t\tptype = byte * BITS_PER_BYTE + bit;\n-\t\t\t\tif (ptype < ICE_FLOW_PTYPE_MAX) {\n-\t\t\t\t\tprof->ptype[prof->ptype_count] = ptype;\n \n-\t\t\t\t\tif (++prof->ptype_count >=\n-\t\t\t\t\t\tICE_MAX_PTYPE_PER_PROFILE)\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t}\n+\t\t\t\t/* The package should place all ptypes in a\n+\t\t\t\t * non-zero PTG, so the following call should\n+\t\t\t\t * never fail.\n+\t\t\t\t */\n+\t\t\t\tif (ice_ptg_find_ptype(hw, blk, ptype, &ptg))\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\t/* If PTG is already added, skip and continue */\n+\t\t\t\tif (ice_is_bit_set(ptgs_used, ptg))\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tice_set_bit(ptg, ptgs_used);\n+\t\t\t\tprof->ptg[prof->ptg_cnt] = ptg;\n+\n+\t\t\t\tif (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE)\n+\t\t\t\t\tbreak;\n \n \t\t\t\t/* nothing left in byte, then exit */\n \t\t\t\tm = ~((1 << (bit + 1)) - 1);\n@@ -4518,7 +4472,7 @@ ice_add_prof_with_mask(struct ice_hw *hw, enum ice_block blk, u64 id,\n * @ptypes: array of bitmaps indicating ptypes (ICE_FLOW_PTYPE_MAX bits)\n * @es: extraction sequence (length of array is determined by the block)\n *\n- * This function registers a profile, which matches a set of PTYPES with a\n+ * This function registers a profile, which matches a set of PTGs with a\n * particular extraction sequence. While the hardware profile is allocated\n * it will not be written until the first call to ice_add_flow that specifies\n * the ID value used here.\n@@ -4528,11 +4482,14 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t struct ice_fv_word *es)\n {\n \tu32 bytes = DIVIDE_AND_ROUND_UP(ICE_FLOW_PTYPE_MAX, BITS_PER_BYTE);\n+\tice_declare_bitmap(ptgs_used, ICE_XLT1_CNT);\n \tstruct ice_prof_map *prof;\n \tenum ice_status status;\n \tu32 byte = 0;\n \tu8 prof_id;\n \n+\tice_zero_bitmap(ptgs_used, ICE_XLT1_CNT);\n+\n \tice_acquire_lock(&hw->blk[blk].es.prof_map_lock);\n \n \t/* search for existing profile */\n@@ -4569,11 +4526,11 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \n \tprof->profile_cookie = id;\n \tprof->prof_id = prof_id;\n-\tprof->ptype_count = 0;\n+\tprof->ptg_cnt = 0;\n \tprof->context = 0;\n \n \t/* build list of ptgs */\n-\twhile (bytes && prof->ptype_count < ICE_MAX_PTYPE_PER_PROFILE) {\n+\twhile (bytes && prof->ptg_cnt < ICE_MAX_PTG_PER_PROFILE) {\n \t\tu32 bit;\n \n \t\tif (!ptypes[byte]) {\n@@ -4583,18 +4540,29 @@ ice_add_prof(struct ice_hw *hw, enum ice_block blk, u64 id, u8 ptypes[],\n \t\t}\n \t\t/* Examine 8 bits per byte */\n \t\tfor (bit = 0; bit < 8; bit++) {\n-\t\t\tif (ptypes[byte] & 1 << bit) {\n+\t\t\tif (ptypes[byte] & BIT(bit)) {\n \t\t\t\tu16 ptype;\n+\t\t\t\tu8 ptg;\n \t\t\t\tu8 m;\n \n \t\t\t\tptype = byte * BITS_PER_BYTE + bit;\n-\t\t\t\tif (ptype < ICE_FLOW_PTYPE_MAX) {\n-\t\t\t\t\tprof->ptype[prof->ptype_count] = ptype;\n \n-\t\t\t\t\tif (++prof->ptype_count >=\n-\t\t\t\t\t\tICE_MAX_PTYPE_PER_PROFILE)\n-\t\t\t\t\t\tbreak;\n-\t\t\t\t}\n+\t\t\t\t/* The package should place all ptypes in a\n+\t\t\t\t * non-zero PTG, so the following call should\n+\t\t\t\t * never fail.\n+\t\t\t\t */\n+\t\t\t\tif (ice_ptg_find_ptype(hw, blk, ptype, &ptg))\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\t/* If PTG is already added, skip and continue */\n+\t\t\t\tif (ice_is_bit_set(ptgs_used, ptg))\n+\t\t\t\t\tcontinue;\n+\n+\t\t\t\tice_set_bit(ptg, ptgs_used);\n+\t\t\t\tprof->ptg[prof->ptg_cnt] = ptg;\n+\n+\t\t\t\tif (++prof->ptg_cnt >= ICE_MAX_PTG_PER_PROFILE)\n+\t\t\t\t\tbreak;\n \n \t\t\t\t/* nothing left in byte, then exit */\n \t\t\t\tm = ~((1 << (bit + 1)) - 1);\n@@ -4722,10 +4690,13 @@ ice_rem_prof_id(struct ice_hw *hw, enum ice_block blk,\n \tu16 i;\n \n \tfor (i = 0; i < prof->tcam_count; i++) {\n-\t\tprof->tcam[i].in_use = false;\n-\t\tstatus = ice_rel_tcam_idx(hw, blk, prof->tcam[i].tcam_idx);\n-\t\tif (status)\n-\t\t\treturn ICE_ERR_HW_TABLE;\n+\t\tif (prof->tcam[i].in_use) {\n+\t\t\tprof->tcam[i].in_use = false;\n+\t\t\tstatus = ice_rel_tcam_idx(hw, blk,\n+\t\t\t\t\t\t prof->tcam[i].tcam_idx);\n+\t\t\tif (status)\n+\t\t\t\treturn ICE_ERR_HW_TABLE;\n+\t\t}\n \t}\n \n \treturn ICE_SUCCESS;\n@@ -4905,15 +4876,15 @@ enum ice_status ice_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 id)\n }\n \n /**\n- * ice_get_prof_ptgs - get ptgs for profile\n+ * ice_get_prof - get profile\n * @hw: pointer to the HW struct\n * @blk: hardware block\n * @hdl: profile handle\n * @chg: change list\n */\n static enum ice_status\n-ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,\n-\t\t struct LIST_HEAD_TYPE *chg)\n+ice_get_prof(struct ice_hw *hw, enum ice_block blk, u64 hdl,\n+\t struct LIST_HEAD_TYPE *chg)\n {\n \tstruct ice_prof_map *map;\n \tstruct ice_chs_chg *p;\n@@ -4924,27 +4895,19 @@ ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,\n \tif (!map)\n \t\treturn ICE_ERR_DOES_NOT_EXIST;\n \n-\tfor (i = 0; i < map->ptype_count; i++) {\n-\t\tenum ice_status status;\n-\t\tbool add;\n-\t\tu8 ptg;\n-\n-\t\tstatus = ice_get_ptg(hw, blk, map->ptype[i], &ptg, &add);\n-\t\tif (status)\n-\t\t\tgoto err_ice_get_prof_ptgs;\n-\n-\t\tif (add || !hw->blk[blk].es.written[map->prof_id]) {\n-\t\t\t/* add PTG to change list */\n+\tfor (i = 0; i < map->ptg_cnt; i++) {\n+\t\tif (!hw->blk[blk].es.written[map->prof_id]) {\n+\t\t\t/* add ES to change list */\n \t\t\tp = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));\n \t\t\tif (!p)\n-\t\t\t\tgoto err_ice_get_prof_ptgs;\n+\t\t\t\tgoto err_ice_get_prof;\n \n \t\t\tp->type = ICE_PTG_ES_ADD;\n-\t\t\tp->ptype = map->ptype[i];\n-\t\t\tp->ptg = ptg;\n-\t\t\tp->add_ptg = add;\n+\t\t\tp->ptype = 0;\n+\t\t\tp->ptg = map->ptg[i];\n+\t\t\tp->add_ptg = 0;\n \n-\t\t\tp->add_prof = !hw->blk[blk].es.written[map->prof_id];\n+\t\t\tp->add_prof = 1;\n \t\t\tp->prof_id = map->prof_id;\n \n \t\t\thw->blk[blk].es.written[map->prof_id] = true;\n@@ -4955,7 +4918,7 @@ ice_get_prof_ptgs(struct ice_hw *hw, enum ice_block blk, u64 hdl,\n \n \treturn ICE_SUCCESS;\n \n-err_ice_get_prof_ptgs:\n+err_ice_get_prof:\n \t/* let caller clean up the change list */\n \treturn ICE_ERR_NO_MEMORY;\n }\n@@ -5026,20 +4989,12 @@ ice_add_prof_to_lst(struct ice_hw *hw, enum ice_block blk,\n \n \tp->profile_cookie = map->profile_cookie;\n \tp->prof_id = map->prof_id;\n-\tp->tcam_count = map->ptype_count;\n-\n-\tfor (i = 0; i < map->ptype_count; i++) {\n-\t\tu8 ptg;\n+\tp->tcam_count = map->ptg_cnt;\n \n+\tfor (i = 0; i < map->ptg_cnt; i++) {\n \t\tp->tcam[i].prof_id = map->prof_id;\n \t\tp->tcam[i].tcam_idx = ICE_INVALID_TCAM;\n-\n-\t\tif (ice_ptg_find_ptype(hw, blk, map->ptype[i], &ptg)) {\n-\t\t\tice_free(hw, p);\n-\t\t\treturn ICE_ERR_CFG;\n-\t\t}\n-\n-\t\tp->tcam[i].ptg = ptg;\n+\t\tp->tcam[i].ptg = map->ptg[i];\n \t}\n \n \tLIST_ADD(&p->list, lst);\n@@ -5110,12 +5065,19 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,\n \tu8 nm_msk[ICE_TCAM_KEY_VAL_SZ] = { 0x00, 0x00, 0x00, 0x00, 0x00 };\n \tu8 vl_msk[ICE_TCAM_KEY_VAL_SZ] = { 0x01, 0x00, 0x00, 0x00, 0x00 };\n \n-\t/* If disabled, change the low flag bit to never match */\n+\t/* if disabling, free the tcam */\n \tif (!enable) {\n-\t\tdc_msk[0] = 0x00;\n-\t\tnm_msk[0] = 0x01;\n+\t\tstatus = ice_free_tcam_ent(hw, blk, tcam->tcam_idx);\n+\t\ttcam->tcam_idx = 0;\n+\t\ttcam->in_use = 0;\n+\t\treturn status;\n \t}\n \n+\t/* for re-enabling, reallocate a tcam */\n+\tstatus = ice_alloc_tcam_ent(hw, blk, &tcam->tcam_idx);\n+\tif (status)\n+\t\treturn status;\n+\n \t/* add TCAM to change list */\n \tp = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));\n \tif (!p)\n@@ -5127,7 +5089,7 @@ ice_prof_tcam_ena_dis(struct ice_hw *hw, enum ice_block blk, bool enable,\n \tif (status)\n \t\tgoto err_ice_prof_tcam_ena_dis;\n \n-\ttcam->in_use = enable;\n+\ttcam->in_use = 1;\n \n \tp->type = ICE_TCAM_ADD;\n \tp->add_tcam_idx = true;\n@@ -5252,21 +5214,12 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,\n \n \tt->profile_cookie = map->profile_cookie;\n \tt->prof_id = map->prof_id;\n-\tt->tcam_count = map->ptype_count;\n+\tt->tcam_count = map->ptg_cnt;\n \n \t/* create TCAM entries */\n-\tfor (i = 0; i < map->ptype_count; i++) {\n+\tfor (i = 0; i < map->ptg_cnt; i++) {\n \t\tenum ice_status status;\n \t\tu16 tcam_idx;\n-\t\tbool add;\n-\t\tu8 ptg;\n-\n-\t\t/* If properly sequenced, we should never have to allocate new\n-\t\t * PTGs\n-\t\t */\n-\t\tstatus = ice_get_ptg(hw, blk, map->ptype[i], &ptg, &add);\n-\t\tif (status)\n-\t\t\tgoto err_ice_add_prof_id_vsig;\n \n \t\t/* add TCAM to change list */\n \t\tp = (struct ice_chs_chg *)ice_malloc(hw, sizeof(*p));\n@@ -5280,7 +5233,7 @@ ice_add_prof_id_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig, u64 hdl,\n \t\t\tgoto err_ice_add_prof_id_vsig;\n \t\t}\n \n-\t\tt->tcam[i].ptg = ptg;\n+\t\tt->tcam[i].ptg = map->ptg[i];\n \t\tt->tcam[i].prof_id = map->prof_id;\n \t\tt->tcam[i].tcam_idx = tcam_idx;\n \t\tt->tcam[i].in_use = true;\n@@ -5497,7 +5450,8 @@ ice_add_prof_id_flow(struct ice_hw *hw, enum ice_block blk, u16 vsi, u64 hdl)\n \tINIT_LIST_HEAD(&chrs);\n \tINIT_LIST_HEAD(&chg);\n \n-\tstatus = ice_get_prof_ptgs(hw, blk, hdl, &chg);\n+\t/* Get profile */\n+\tstatus = ice_get_prof(hw, blk, hdl, &chg);\n \tif (status)\n \t\treturn status;\n \ndiff --git a/drivers/net/ice/base/ice_flex_pipe.h b/drivers/net/ice/base/ice_flex_pipe.h\nindex ab1663574..3b5c1c39a 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.h\n+++ b/drivers/net/ice/base/ice_flex_pipe.h\n@@ -9,7 +9,7 @@\n \n /* Package minimal version supported */\n #define ICE_PKG_SUPP_VER_MAJ\t1\n-#define ICE_PKG_SUPP_VER_MNR\t2\n+#define ICE_PKG_SUPP_VER_MNR\t3\n \n /* Package format version */\n #define ICE_PKG_FMT_VER_MAJ\t1\ndiff --git a/drivers/net/ice/base/ice_flex_type.h b/drivers/net/ice/base/ice_flex_type.h\nindex 3a70668d9..baf53d881 100644\n--- a/drivers/net/ice/base/ice_flex_type.h\n+++ b/drivers/net/ice/base/ice_flex_type.h\n@@ -518,16 +518,16 @@ struct ice_ptg_ptype {\n \tu8 ptg;\n };\n \n-#define ICE_MAX_TCAM_PER_PROFILE\t8\n-#define ICE_MAX_PTYPE_PER_PROFILE\t8\n+#define ICE_MAX_TCAM_PER_PROFILE\t32\n+#define ICE_MAX_PTG_PER_PROFILE\t\t32\n \n struct ice_prof_map {\n \tstruct LIST_ENTRY_TYPE list;\n \tu64 profile_cookie;\n \tu64 context;\n \tu8 prof_id;\n-\tu8 ptype_count;\n-\tu16 ptype[ICE_MAX_PTYPE_PER_PROFILE];\n+\tu8 ptg_cnt;\n+\tu8 ptg[ICE_MAX_PTG_PER_PROFILE];\n };\n \n #define ICE_INVALID_TCAM\t0xFFFF\n", "prefixes": [ "43/63" ] }