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{
    "id": 57920,
    "url": "https://patches.dpdk.org/api/patches/57920/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-25-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190826105105.19121-25-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-25-qi.z.zhang@intel.com",
    "date": "2019-08-26T10:50:26",
    "name": "[24/63] net/ice/base: add support for NVM access commands",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "98e3061f8a84c04d4f9148f05d885f424f0d6481",
    "submitter": {
        "id": 504,
        "url": "https://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "https://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-25-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 6119,
            "url": "https://patches.dpdk.org/api/series/6119/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6119",
            "date": "2019-08-26T10:50:02",
            "name": "net/ice/base: update base code",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/6119/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/57920/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/57920/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 13C151C12B;\n\tMon, 26 Aug 2019 12:49:57 +0200 (CEST)",
            "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 889311BFD0\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:49:09 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:49:09 -0700",
            "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:49:07 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402232\"",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com",
        "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tJacob Keller <jacob.e.keller@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>",
        "Date": "Mon, 26 Aug 2019 18:50:26 +0800",
        "Message-Id": "<20190826105105.19121-25-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.13.6",
        "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>",
        "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 24/63] net/ice/base: add support for NVM access\n\tcommands",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Add a new structure, ice_nvm_access, used to request access to read or\nwrite certain NVM related registers.\n\nThe structure is used by NVM Update to request read or write of specific\nNVM registers in order to perform updates.\n\nAdditionally, there is a command to request the driver \"features\"\nstructure which represents data about what features of the NVM access\ninterface the driver supports.\n\nImplement ice_handle_nvm_access to parse the access request and perform\nthe necessary function.\n\nThis function verifies that the access request is valid. If so, the\nfunction will delegate to perform the register read, register write, or\ncopying of the driver ice_nvm_features structure.\n\nIf the request is invalid, the function will report a suitable error\ncodition that can be propagated out.\n\nOnly a subset of registers is accessible, and all other registers will\nbe rejected with ICE_ERR_OUT_OF_RANGE.\n\nWhen reading, the contents of the variable sized data buffer will be\nused as storage for returning the register value. When writing, the\ncontents will be used as input for the value to write to the register.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.h |   1 +\n drivers/net/ice/base/ice_nvm.c    | 237 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 238 insertions(+)",
    "diff": "diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex 1fd256a42..a55f7eeba 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -6,6 +6,7 @@\n #define _ICE_COMMON_H_\n \n #include \"ice_type.h\"\n+#include \"ice_nvm.h\"\n #include \"ice_flex_pipe.h\"\n #include \"ice_switch.h\"\n #include \"ice_fdir.h\"\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 95a6c9ab6..66cfec641 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -411,3 +411,240 @@ enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)\n \n \treturn status;\n }\n+\n+/**\n+ * ice_nvm_access_get_features - Return the NVM access features structure\n+ * @cmd: NVM access command to process\n+ * @data: storage for the driver NVM features\n+ *\n+ * Fill in the data section of the NVM access request with a copy of the NVM\n+ * features structure.\n+ */\n+enum ice_status\n+ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,\n+\t\t\t    union ice_nvm_access_data *data)\n+{\n+\t/* The provided data_size must be at least as large as our NVM\n+\t * features structure. A larger size should not be treated as an\n+\t * error, to allow future extensions to to the features structure to\n+\t * work on older drivers.\n+\t */\n+\tif (cmd->data_size < sizeof(struct ice_nvm_features))\n+\t\treturn ICE_ERR_NO_MEMORY;\n+\n+\t/* Initialize the data buffer to zeros */\n+\tice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);\n+\n+\t/* Fill in the features data */\n+\tdata->drv_features.major = ICE_NVM_ACCESS_MAJOR_VER;\n+\tdata->drv_features.minor = ICE_NVM_ACCESS_MINOR_VER;\n+\tdata->drv_features.size = sizeof(struct ice_nvm_features);\n+\tdata->drv_features.features[0] = ICE_NVM_FEATURES_0_REG_ACCESS;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_nvm_access_get_module - Helper function to read module value\n+ * @cmd: NVM access command structure\n+ *\n+ * Reads the module value out of the NVM access config field.\n+ */\n+u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd)\n+{\n+\treturn ((cmd->config & ICE_NVM_CFG_MODULE_M) >> ICE_NVM_CFG_MODULE_S);\n+}\n+\n+/**\n+ * ice_nvm_access_get_flags - Helper function to read flags value\n+ * @cmd: NVM access command structure\n+ *\n+ * Reads the flags value out of the NVM access config field.\n+ */\n+u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd)\n+{\n+\treturn ((cmd->config & ICE_NVM_CFG_FLAGS_M) >> ICE_NVM_CFG_FLAGS_S);\n+}\n+\n+/**\n+ * ice_nvm_access_get_adapter - Helper function to read adapter info\n+ * @cmd: NVM access command structure\n+ *\n+ * Read the adapter info value out of the NVM access config field.\n+ */\n+u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd)\n+{\n+\treturn ((cmd->config & ICE_NVM_CFG_ADAPTER_INFO_M) >>\n+\t\tICE_NVM_CFG_ADAPTER_INFO_S);\n+}\n+\n+/**\n+ * ice_validate_nvm_rw_reg - Check than an NVM access request is valid\n+ * @cmd: NVM access command structure\n+ *\n+ * Validates that an NVM access structure is request to read or write a valid\n+ * register offset. First validates that the module and flags are correct, and\n+ * then ensures that the register offset is one of the accepted registers.\n+ */\n+static enum ice_status\n+ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)\n+{\n+\tu32 module, flags, offset;\n+\tu16 i;\n+\n+\tmodule = ice_nvm_access_get_module(cmd);\n+\tflags = ice_nvm_access_get_flags(cmd);\n+\toffset = cmd->offset;\n+\n+\t/* Make sure the module and flags indicate a read/write request */\n+\tif (module != ICE_NVM_REG_RW_MODULE ||\n+\t    flags != ICE_NVM_REG_RW_FLAGS ||\n+\t    cmd->data_size != FIELD_SIZEOF(union ice_nvm_access_data, regval))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tswitch (offset) {\n+\tcase GL_HICR:\n+\tcase GL_HICR_EN: /* Note, this register is read only */\n+\tcase GL_FWSTS:\n+\tcase GL_MNG_FWSM:\n+\tcase GLGEN_CSR_DEBUG_C:\n+\tcase GLPCI_LBARCTRL:\n+\tcase GLNVM_GENS:\n+\tcase GLNVM_FLA:\n+\tcase PF_FUNC_RID:\n+\t\treturn ICE_SUCCESS;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i <= ICE_NVM_ACCESS_GL_HIDA_MAX; i++)\n+\t\tif (offset == (u32)GL_HIDA(i))\n+\t\t\treturn ICE_SUCCESS;\n+\n+\tfor (i = 0; i <= ICE_NVM_ACCESS_GL_HIBA_MAX; i++)\n+\t\tif (offset == (u32)GL_HIBA(i))\n+\t\t\treturn ICE_SUCCESS;\n+\n+\t/* All other register offsets are not valid */\n+\treturn ICE_ERR_OUT_OF_RANGE;\n+}\n+\n+/**\n+ * ice_nvm_access_read - Handle an NVM read request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command to process\n+ * @data: storage for the register value read\n+ *\n+ * Process an NVM access request to read a register.\n+ */\n+enum ice_status\n+ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n+\t\t    union ice_nvm_access_data *data)\n+{\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n+\n+\t/* Always initialize the output data, even on failure */\n+\tice_memset(data, 0, cmd->data_size, ICE_NONDMA_MEM);\n+\n+\t/* Make sure this is a valid read/write access request */\n+\tstatus = ice_validate_nvm_rw_reg(cmd);\n+\tif (status)\n+\t\treturn status;\n+\n+\tice_debug(hw, ICE_DBG_NVM, \"NVM access: reading register %08x\\n\",\n+\t\t  cmd->offset);\n+\n+\t/* Read the register and store the contents in the data field */\n+\tdata->regval = rd32(hw, cmd->offset);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_nvm_access_write - Handle an NVM write request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command to process\n+ * @data: NVM access data to write\n+ *\n+ * Process an NVM access request to write a register.\n+ */\n+enum ice_status\n+ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n+\t\t     union ice_nvm_access_data *data)\n+{\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n+\n+\t/* Make sure this is a valid read/write access request */\n+\tstatus = ice_validate_nvm_rw_reg(cmd);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* The HICR_EN register is read-only */\n+\tif (cmd->offset == GL_HICR_EN)\n+\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\n+\tice_debug(hw, ICE_DBG_NVM,\n+\t\t  \"NVM access: writing register %08x with value %08x\\n\",\n+\t\t  cmd->offset, data->regval);\n+\n+\t/* Write the data field to the specified register */\n+\twr32(hw, cmd->offset, data->regval);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_handle_nvm_access - Handle an NVM access request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command info\n+ * @data: pointer to read or return data\n+ *\n+ * Process an NVM access request. Read the command structure information and\n+ * determine if it is valid. If not, report an error indicating the command\n+ * was invalid.\n+ *\n+ * For valid commands, perform the necessary function, copying the data into\n+ * the provided data buffer.\n+ */\n+enum ice_status\n+ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n+\t\t      union ice_nvm_access_data *data)\n+{\n+\tu32 module, flags, adapter_info;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"%s\\n\", __func__);\n+\n+\t/* Extended flags are currently reserved and must be zero */\n+\tif ((cmd->config & ICE_NVM_CFG_EXT_FLAGS_M) != 0)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* Adapter info must match the HW device ID */\n+\tadapter_info = ice_nvm_access_get_adapter(cmd);\n+\tif (adapter_info != hw->device_id)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tswitch (cmd->command) {\n+\tcase ICE_NVM_CMD_READ:\n+\t\tmodule = ice_nvm_access_get_module(cmd);\n+\t\tflags = ice_nvm_access_get_flags(cmd);\n+\n+\t\t/* Getting the driver's NVM features structure shares the same\n+\t\t * command type as reading a register. Read the config field\n+\t\t * to determine if this is a request to get features.\n+\t\t */\n+\t\tif (module == ICE_NVM_GET_FEATURES_MODULE &&\n+\t\t    flags == ICE_NVM_GET_FEATURES_FLAGS &&\n+\t\t    cmd->offset == 0)\n+\t\t\treturn ice_nvm_access_get_features(cmd, data);\n+\t\telse\n+\t\t\treturn ice_nvm_access_read(hw, cmd, data);\n+\tcase ICE_NVM_CMD_WRITE:\n+\t\treturn ice_nvm_access_write(hw, cmd, data);\n+\tdefault:\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+}\n",
    "prefixes": [
        "24/63"
    ]
}