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GET /api/patches/57919/?format=api
{ "id": 57919, "url": "https://patches.dpdk.org/api/patches/57919/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-24-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-24-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-24-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:25", "name": "[23/63] net/ice/base: update Boot Configuration Section read of NVM", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "55e0ba1c3f45c7fbd22189875a2181b73b3c6841", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-24-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "https://patches.dpdk.org/api/series/6119/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "https://patches.dpdk.org/series/6119/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57919/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/57919/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DA0241C136;\n\tMon, 26 Aug 2019 12:49:52 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 822AA1C043\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:49:07 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:49:07 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:49:05 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402210\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tMd Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:25 +0800", "Message-Id": "<20190826105105.19121-24-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 23/63] net/ice/base: update Boot Configuration\n\tSection read of NVM", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Boot Configuration Section Block has been moved to the\nPreserved Field Area (PFA) of NVM. So, this patch updates\nthe NVM reads that involve Boot Configuration Section.\n\nSigned-off-by: Md Fahad Iqbal Polash <md.fahad.iqbal.polash@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_devids.h | 6 +++\n drivers/net/ice/base/ice_nvm.c | 39 +++++++++++++-----\n drivers/net/ice/base/ice_nvm.h | 87 +++++++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_type.h | 4 +-\n 4 files changed, 124 insertions(+), 12 deletions(-)\n create mode 100644 drivers/net/ice/base/ice_nvm.h", "diff": "diff --git a/drivers/net/ice/base/ice_devids.h b/drivers/net/ice/base/ice_devids.h\nindex 5f1ac0422..c9a567fb1 100644\n--- a/drivers/net/ice/base/ice_devids.h\n+++ b/drivers/net/ice/base/ice_devids.h\n@@ -13,5 +13,11 @@\n #define ICE_DEV_ID_E810C_QSFP\t\t0x1592\n /* Intel(R) Ethernet Controller E810-C for SFP */\n #define ICE_DEV_ID_E810C_SFP\t\t0x1593\n+/* Intel(R) Ethernet Connection C822N for backplane */\n+#define ICE_DEV_ID_C822N_BACKPLANE\t0x1890\n+/* Intel(R) Ethernet Connection C822N for QSFP */\n+#define ICE_DEV_ID_C822N_QSFP\t\t0x1891\n+/* Intel(R) Ethernet Connection C822N for SFP */\n+#define ICE_DEV_ID_C822N_SFP\t\t0x1892\n \n #endif /* _ICE_DEVIDS_H_ */\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex c0f9e353e..95a6c9ab6 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -263,9 +263,9 @@ enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)\n enum ice_status ice_init_nvm(struct ice_hw *hw)\n {\n \tstruct ice_nvm_info *nvm = &hw->nvm;\n-\tu16 oem_hi, oem_lo, cfg_ptr;\n+\tu16 oem_hi, oem_lo, boot_cfg_tlv, boot_cfg_tlv_len;\n \tu16 eetrack_lo, eetrack_hi;\n-\tenum ice_status status = ICE_SUCCESS;\n+\tenum ice_status status;\n \tu32 fla, gens_stat;\n \tu8 sr_size;\n \n@@ -284,12 +284,12 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)\n \tfla = rd32(hw, GLNVM_FLA);\n \tif (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */\n \t\tnvm->blank_nvm_mode = false;\n-\t} else { /* Blank programming mode */\n+\t} else {\n+\t\t/* Blank programming mode */\n \t\tnvm->blank_nvm_mode = true;\n-\t\tstatus = ICE_ERR_NVM_BLANK_MODE;\n \t\tice_debug(hw, ICE_DBG_NVM,\n \t\t\t \"NVM init error: unsupported blank mode.\\n\");\n-\t\treturn status;\n+\t\treturn ICE_ERR_NVM_BLANK_MODE;\n \t}\n \n \tstatus = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &nvm->ver);\n@@ -312,19 +312,37 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)\n \n \tnvm->eetrack = (eetrack_hi << 16) | eetrack_lo;\n \n-\tstatus = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);\n+\t/* the following devices do not have boot_cfg_tlv yet */\n+\tif (hw->device_id == ICE_DEV_ID_C822N_BACKPLANE ||\n+\t hw->device_id == ICE_DEV_ID_C822N_QSFP ||\n+\t hw->device_id == ICE_DEV_ID_C822N_SFP)\n+\t\treturn status;\n+\n+\tstatus = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len,\n+\t\t\t\t\tICE_SR_BOOT_CFG_PTR);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read BOOT_CONFIG_PTR.\\n\");\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Failed to read Boot Configuration Block TLV.\\n\");\n \t\treturn status;\n \t}\n \n-\tstatus = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);\n+\t/* Boot Configuration Block must have length at least 2 words\n+\t * (Combo Image Version High and Combo Image Version Low)\n+\t */\n+\tif (boot_cfg_tlv_len < 2) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Invalid Boot Configuration Block TLV size.\\n\");\n+\t\treturn ICE_ERR_INVAL_SIZE;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF),\n+\t\t\t\t &oem_hi);\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read OEM_VER hi.\\n\");\n \t\treturn status;\n \t}\n \n-\tstatus = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),\n+\tstatus = ice_read_sr_word(hw, (boot_cfg_tlv + ICE_NVM_OEM_VER_OFF + 1),\n \t\t\t\t &oem_lo);\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read OEM_VER lo.\\n\");\n@@ -332,7 +350,8 @@ enum ice_status ice_init_nvm(struct ice_hw *hw)\n \t}\n \n \tnvm->oem_ver = ((u32)oem_hi << 16) | oem_lo;\n-\treturn status;\n+\n+\treturn ICE_SUCCESS;\n }\n \n \ndiff --git a/drivers/net/ice/base/ice_nvm.h b/drivers/net/ice/base/ice_nvm.h\nnew file mode 100644\nindex 000000000..da76b2674\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_nvm.h\n@@ -0,0 +1,87 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2019\n+ */\n+\n+#ifndef _ICE_NVM_H_\n+#define _ICE_NVM_H_\n+\n+#define ICE_NVM_CMD_READ\t\t0x0000000B\n+#define ICE_NVM_CMD_WRITE\t\t0x0000000C\n+\n+/* NVM Access config bits */\n+#define ICE_NVM_CFG_MODULE_M\t\tMAKEMASK(0xFF, 0)\n+#define ICE_NVM_CFG_MODULE_S\t\t0\n+#define ICE_NVM_CFG_FLAGS_M\t\tMAKEMASK(0xF, 8)\n+#define ICE_NVM_CFG_FLAGS_S\t\t8\n+#define ICE_NVM_CFG_EXT_FLAGS_M\t\tMAKEMASK(0xF, 12)\n+#define ICE_NVM_CFG_EXT_FLAGS_S\t\t12\n+#define ICE_NVM_CFG_ADAPTER_INFO_M\tMAKEMASK(0xFFFF, 16)\n+#define ICE_NVM_CFG_ADAPTER_INFO_S\t16\n+\n+/* NVM Read Get Driver Features */\n+#define ICE_NVM_GET_FEATURES_MODULE\t0xE\n+#define ICE_NVM_GET_FEATURES_FLAGS\t0xF\n+\n+/* NVM Read/Write Mapped Space */\n+#define ICE_NVM_REG_RW_MODULE\t0x0\n+#define ICE_NVM_REG_RW_FLAGS\t0x1\n+\n+#define ICE_NVM_ACCESS_MAJOR_VER\t0\n+#define ICE_NVM_ACCESS_MINOR_VER\t5\n+\n+/* NVM Access feature flags. Other bits in the features field are reserved and\n+ * should be set to zero when reporting the ice_nvm_features structure.\n+ */\n+#define ICE_NVM_FEATURES_0_REG_ACCESS\tBIT(1)\n+\n+/* NVM Access Features */\n+struct ice_nvm_features {\n+\tu8 major;\t\t/* Major version (informational only) */\n+\tu8 minor;\t\t/* Minor version (informational only) */\n+\tu16 size;\t\t/* size of ice_nvm_features structure */\n+\tu8 features[12];\t/* Array of feature bits */\n+};\n+\n+/* NVM Access command */\n+struct ice_nvm_access_cmd {\n+\tu32 command;\t\t/* NVM command: READ or WRITE */\n+\tu32 config;\t\t/* NVM command configuration */\n+\tu32 offset;\t\t/* offset to read/write, in bytes */\n+\tu32 data_size;\t\t/* size of data field, in bytes */\n+};\n+\n+/* NVM Access data */\n+union ice_nvm_access_data {\n+\tu32 regval;\t/* Storage for register value */\n+\tstruct ice_nvm_features drv_features; /* NVM features */\n+};\n+\n+/* NVM Access registers */\n+#define GL_HIDA(_i)\t\t\t(0x00082000 + ((_i) * 4))\n+#define GL_HIBA(_i)\t\t\t(0x00081000 + ((_i) * 4))\n+#define GL_HICR\t\t\t\t0x00082040\n+#define GL_HICR_EN\t\t\t0x00082044\n+#define GLGEN_CSR_DEBUG_C\t\t0x00075750\n+#define GLPCI_LBARCTRL\t\t\t0x0009DE74\n+#define GLNVM_GENS\t\t\t0x000B6100\n+#define GLNVM_FLA\t\t\t0x000B6108\n+\n+#define ICE_NVM_ACCESS_GL_HIDA_MAX\t15\n+#define ICE_NVM_ACCESS_GL_HIBA_MAX\t1023\n+\n+u32 ice_nvm_access_get_module(struct ice_nvm_access_cmd *cmd);\n+u32 ice_nvm_access_get_flags(struct ice_nvm_access_cmd *cmd);\n+u32 ice_nvm_access_get_adapter(struct ice_nvm_access_cmd *cmd);\n+enum ice_status\n+ice_nvm_access_read(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n+\t\t union ice_nvm_access_data *data);\n+enum ice_status\n+ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n+\t\t union ice_nvm_access_data *data);\n+enum ice_status\n+ice_nvm_access_get_features(struct ice_nvm_access_cmd *cmd,\n+\t\t\t union ice_nvm_access_data *data);\n+enum ice_status\n+ice_handle_nvm_access(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,\n+\t\t union ice_nvm_access_data *data);\n+#endif /* _ICE_NVM_H_ */\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 79d7bb1dd..dc041760d 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -916,9 +916,9 @@ enum ice_sw_fwd_act_type {\n #define ICE_SR_MNG_CFG_PTR\t\t\t0x0E\n #define ICE_SR_EMP_MODULE_PTR\t\t\t0x0F\n #define ICE_SR_PBA_BLOCK_PTR\t\t\t0x16\n-#define ICE_SR_BOOT_CFG_PTR\t\t\t0x17\n+#define ICE_SR_BOOT_CFG_PTR\t\t\t0x132\n #define ICE_SR_NVM_WOL_CFG\t\t\t0x19\n-#define ICE_NVM_OEM_VER_OFF\t\t\t0x83\n+#define ICE_NVM_OEM_VER_OFF\t\t\t0x02\n #define ICE_SR_NVM_DEV_STARTER_VER\t\t0x18\n #define ICE_SR_ALTERNATE_SAN_MAC_ADDR_PTR\t0x27\n #define ICE_SR_PERMANENT_SAN_MAC_ADDR_PTR\t0x28\n", "prefixes": [ "23/63" ] }