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GET /api/patches/57908/?format=api
{ "id": 57908, "url": "https://patches.dpdk.org/api/patches/57908/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-13-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-13-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-13-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:14", "name": "[12/63] net/ice/base: add helper functions for PHY caching", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "08f139e9ed3131d99dd5a91c4635bff2cf5c740b", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-13-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "https://patches.dpdk.org/api/series/6119/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "https://patches.dpdk.org/series/6119/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57908/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/57908/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id F12571C037;\n\tMon, 26 Aug 2019 12:48:59 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id 9957F1C020\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:48:47 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:48:47 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:48:45 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402119\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tTony Nguyen <anthony.l.nguyen@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:14 +0800", "Message-Id": "<20190826105105.19121-13-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 12/63] net/ice/base: add helper functions for PHY\n\tcaching", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add additional functions to aide in caching PHY\nconfiguration. In order to cache the initial modes,\nwe need to determine the operating mode based on\ncapabilities. Add helper functions for flow control\nand FEC to take a set of capabilities and return the\noperating mode matching those capabilities. Also add\na helper function to determine whether a PHY capability\nmatches a PHY configuration.\n\nIntroduce a mask for valid link speeds and unwrap\nice_copy_caps_to_cfg() for more builds so that we can utilize\nit in more places.\n\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 1 +\n drivers/net/ice/base/ice_common.c | 83 +++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_common.h | 9 +++-\n 3 files changed, 91 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 4de69dd7a..cc42180ea 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1598,6 +1598,7 @@ struct ice_aqc_get_link_status_data {\n #define ICE_AQ_LINK_PWR_QSFP_CLASS_3\t2\n #define ICE_AQ_LINK_PWR_QSFP_CLASS_4\t3\n \t__le16 link_speed;\n+#define ICE_AQ_LINK_SPEED_M\t\t0x7FF\n #define ICE_AQ_LINK_SPEED_10MB\t\tBIT(0)\n #define ICE_AQ_LINK_SPEED_100MB\t\tBIT(1)\n #define ICE_AQ_LINK_SPEED_1000MB\tBIT(2)\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 9907d9dae..6b28f6230 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2613,6 +2613,53 @@ ice_cache_phy_user_req(struct ice_port_info *pi,\n }\n \n /**\n+ * ice_caps_to_fc_mode\n+ * @caps: PHY capabilities\n+ *\n+ * Convert PHY FC capabilities to ice FC mode\n+ */\n+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps)\n+{\n+\tif (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE &&\n+\t caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)\n+\t\treturn ICE_FC_FULL;\n+\n+\tif (caps & ICE_AQC_PHY_EN_TX_LINK_PAUSE)\n+\t\treturn ICE_FC_TX_PAUSE;\n+\n+\tif (caps & ICE_AQC_PHY_EN_RX_LINK_PAUSE)\n+\t\treturn ICE_FC_RX_PAUSE;\n+\n+\treturn ICE_FC_NONE;\n+}\n+\n+/**\n+ * ice_caps_to_fec_mode\n+ * @caps: PHY capabilities\n+ * @fec_options: Link FEC options\n+ *\n+ * Convert PHY FEC capabilities to ice FEC mode\n+ */\n+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options)\n+{\n+\tif (caps & ICE_AQC_PHY_EN_AUTO_FEC)\n+\t\treturn ICE_FEC_AUTO;\n+\n+\tif (fec_options & (ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |\n+\t\t\t ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |\n+\t\t\t ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN |\n+\t\t\t ICE_AQC_PHY_FEC_25G_KR_REQ))\n+\t\treturn ICE_FEC_BASER;\n+\n+\tif (fec_options & (ICE_AQC_PHY_FEC_25G_RS_528_REQ |\n+\t\t\t ICE_AQC_PHY_FEC_25G_RS_544_REQ |\n+\t\t\t ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN))\n+\t\treturn ICE_FEC_RS;\n+\n+\treturn ICE_FEC_NONE;\n+}\n+\n+/**\n * ice_set_fc\n * @pi: port information structure\n * @aq_failures: pointer to status code, specific to ice_set_fc routine\n@@ -2719,6 +2766,42 @@ ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)\n }\n \n /**\n+ * ice_phy_caps_equals_cfg\n+ * @phy_caps: PHY capabilities\n+ * @phy_cfg: PHY configuration\n+ *\n+ * Helper function to determine if PHY capabilities matches PHY\n+ * configuration\n+ */\n+bool\n+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *phy_caps,\n+\t\t\tstruct ice_aqc_set_phy_cfg_data *phy_cfg)\n+{\n+\tu8 caps_mask, cfg_mask;\n+\n+\tif (!phy_caps || !phy_cfg)\n+\t\treturn false;\n+\n+\t/* These bits are not common between capabilities and configuration.\n+\t * Do not use them to determine equality.\n+\t */\n+\tcaps_mask = ICE_AQC_PHY_CAPS_MASK & ~(ICE_AQC_PHY_AN_MODE |\n+\t\t\t\t\t ICE_AQC_PHY_EN_MOD_QUAL);\n+\tcfg_mask = ICE_AQ_PHY_ENA_VALID_MASK & ~ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\tif (phy_caps->phy_type_low != phy_cfg->phy_type_low ||\n+\t phy_caps->phy_type_high != phy_cfg->phy_type_high ||\n+\t ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||\n+\t phy_caps->low_power_ctrl != phy_cfg->low_power_ctrl ||\n+\t phy_caps->eee_cap != phy_cfg->eee_cap ||\n+\t phy_caps->eeer_value != phy_cfg->eeer_value ||\n+\t phy_caps->link_fec_options != phy_cfg->link_fec_opt)\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+/**\n * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data\n * @caps: PHY ability structure to copy date from\n * @cfg: PHY configuration structure to copy data to\ndiff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h\nindex df1fecec5..a8104dfa2 100644\n--- a/drivers/net/ice/base/ice_common.h\n+++ b/drivers/net/ice/base/ice_common.h\n@@ -139,14 +139,19 @@ enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);\n enum ice_status\n ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,\n \t\t struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);\n+enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);\n+enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);\n enum ice_status\n ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,\n \t bool ena_auto_link_update);\n-void\n-ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);\n+bool\n+ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,\n+\t\t\tstruct ice_aqc_set_phy_cfg_data *cfg);\n void\n ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,\n \t\t\t struct ice_aqc_set_phy_cfg_data *cfg);\n+void\n+ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec);\n enum ice_status\n ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,\n \t\t\t struct ice_sq_cd *cd);\n", "prefixes": [ "12/63" ] }