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GET /api/patches/57897/?format=api
{ "id": 57897, "url": "https://patches.dpdk.org/api/patches/57897/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-2-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190826105105.19121-2-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190826105105.19121-2-qi.z.zhang@intel.com", "date": "2019-08-26T10:50:03", "name": "[01/63] net/ice/base: enhance NVM read", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f0bdc3d1459bd044d10364f3d2e93b6d26259dc8", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190826105105.19121-2-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 6119, "url": "https://patches.dpdk.org/api/series/6119/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6119", "date": "2019-08-26T10:50:02", "name": "net/ice/base: update base code", "version": 1, "mbox": "https://patches.dpdk.org/series/6119/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57897/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/57897/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 070921BFA4;\n\tMon, 26 Aug 2019 12:48:31 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n\tby dpdk.org (Postfix) with ESMTP id DCF3E1BF82\n\tfor <dev@dpdk.org>; Mon, 26 Aug 2019 12:48:27 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Aug 2019 03:48:27 -0700", "from dpdk51.sh.intel.com ([10.67.110.245])\n\tby orsmga003.jf.intel.com with ESMTP; 26 Aug 2019 03:48:25 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,431,1559545200\"; d=\"scan'208\";a=\"182402053\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang <qi.z.zhang@intel.com>,\n\tPaul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 26 Aug 2019 18:50:03 +0800", "Message-Id": "<20190826105105.19121-2-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "References": "<20190826105105.19121-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 01/63] net/ice/base: enhance NVM read", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add an option to read NVM from flash directly.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 22 ++++++++++++++++++++++\n drivers/net/ice/base/ice_dcb.h | 1 +\n drivers/net/ice/base/ice_nvm.c | 12 +++++++++---\n 3 files changed, 32 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 7afdb6578..b5faa5bf6 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -1684,6 +1684,28 @@ struct ice_aqc_nvm {\n \t__le32 addr_low;\n };\n \n+/* NVM Module_Type ID, needed offset and read_len for struct ice_aqc_nvm. */\n+#define ICE_AQC_NVM_SECTOR_UNIT\t\t\t4096 /* In Bytes */\n+#define ICE_AQC_NVM_WORD_UNIT\t\t\t2 /* In Bytes */\n+\n+#define ICE_AQC_NVM_START_POINT\t\t\t0\n+#define ICE_AQC_NVM_EMP_SR_PTR_OFFSET\t\t0x90\n+#define ICE_AQC_NVM_EMP_SR_PTR_RD_LEN\t\t2 /* In Bytes */\n+#define ICE_AQC_NVM_EMP_SR_PTR_M\t\tMAKEMASK(0x7FFF, 0)\n+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_S\t\t15\n+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_M\t\tBIT(15)\n+#define ICE_AQC_NVM_EMP_SR_PTR_TYPE_SECTOR\t1\n+\n+#define ICE_AQC_NVM_LLDP_CFG_PTR_OFFSET\t\t0x46\n+#define ICE_AQC_NVM_LLDP_CFG_HEADER_LEN\t\t2 /* In Bytes */\n+#define ICE_AQC_NVM_LLDP_CFG_PTR_RD_LEN\t\t2 /* In Bytes */\n+\n+#define ICE_AQC_NVM_LLDP_PRESERVED_MOD_ID\t0x129\n+#define ICE_AQC_NVM_CUR_LLDP_PERSIST_RD_OFFSET\t2 /* In Bytes */\n+#define ICE_AQC_NVM_LLDP_STATUS_M\t\tMAKEMASK(0xF, 0)\n+#define ICE_AQC_NVM_LLDP_STATUS_M_LEN\t\t4 /* In Bits */\n+#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN\t\t4 /* In Bytes */\n+\n \n /* Used for 0x0704 as well as for 0x0705 commands */\n struct ice_aqc_nvm_cfg {\ndiff --git a/drivers/net/ice/base/ice_dcb.h b/drivers/net/ice/base/ice_dcb.h\nindex 47127096b..9a0968f5b 100644\n--- a/drivers/net/ice/base/ice_dcb.h\n+++ b/drivers/net/ice/base/ice_dcb.h\n@@ -6,6 +6,7 @@\n #define _ICE_DCB_H_\n \n #include \"ice_type.h\"\n+#include \"ice_common.h\"\n \n #define ICE_DCBX_OFFLOAD_DIS\t\t0\n #define ICE_DCBX_OFFLOAD_ENABLED\t1\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 6178cd4ac..f4567ca8f 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -13,13 +13,15 @@\n * @length: length of the section to be read (in bytes from the offset)\n * @data: command buffer (size [bytes] = length)\n * @last_command: tells if this is the last command in a series\n+ * @read_shadow_ram: tell if this is a shadow RAM read\n * @cd: pointer to command details structure or NULL\n *\n * Read the NVM using the admin queue commands (0x0701)\n */\n static enum ice_status\n ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n-\t\tvoid *data, bool last_command, struct ice_sq_cd *cd)\n+\t\tvoid *data, bool last_command, bool read_shadow_ram,\n+\t\tstruct ice_sq_cd *cd)\n {\n \tstruct ice_aq_desc desc;\n \tstruct ice_aqc_nvm *cmd;\n@@ -34,6 +36,9 @@ ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n \n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);\n \n+\tif (!read_shadow_ram && module_typeid == ICE_AQC_NVM_START_POINT)\n+\t\tcmd->cmd_flags |= ICE_AQC_NVM_FLASH_ONLY;\n+\n \t/* If this is the last command in a series, set the proper flag. */\n \tif (last_command)\n \t\tcmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;\n@@ -104,8 +109,9 @@ ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,\n \t * So do this conversion while calling ice_aq_read_nvm.\n \t */\n \tif (!status)\n-\t\tstatus = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,\n-\t\t\t\t\t last_command, NULL);\n+\t\tstatus = ice_aq_read_nvm(hw, ICE_AQC_NVM_START_POINT,\n+\t\t\t\t\t 2 * offset, 2 * words, data,\n+\t\t\t\t\t last_command, true, NULL);\n \n \treturn status;\n }\n", "prefixes": [ "01/63" ] }