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GET /api/patches/57834/?format=api
{ "id": 57834, "url": "https://patches.dpdk.org/api/patches/57834/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190823104144.19300-5-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190823104144.19300-5-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190823104144.19300-5-rnagadheeraj@marvell.com", "date": "2019-08-23T10:42:13", "name": "[v3,04/11] crypto/nitrox: add basic symmetric cryptodev operations", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "620db082c0b6472ec6843179a82ac5f97f52c7dd", "submitter": { "id": 1365, "url": "https://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190823104144.19300-5-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 6113, "url": "https://patches.dpdk.org/api/series/6113/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6113", "date": "2019-08-23T10:42:05", "name": "add Nitrox crypto device support", "version": 3, "mbox": "https://patches.dpdk.org/series/6113/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57834/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/57834/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0B6E51BFCA;\n\tFri, 23 Aug 2019 12:42:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 64DC61BFAF\n\tfor <dev@dpdk.org>; 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SFP:1101; SCL:1; SRVR:MN2PR18MB2830;\n\tH:MN2PR18MB2797.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: marvell.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "Z7l+n9a3w/pJQVxVqSu0xGmFXhGvo3nPa8V5rs37hh/XA5MQcJUKhllUdlBH1B7vpu/WA2J3Q0EUYggoEvv/xbijkqxSmaDmx/BD0tyv1Ej9zpNZ1T9dIHU5vGoBN++OCoAThoqkyNT+07OcbQu3t4F+l2YG6bir8HJVYBujimKkOirpV5oKf1IxrFU6oaHHm29SfS6mxQ2L7a82hewfdeSbgesm5x6ypRgSdhPiS+Di7btNuiL2IT6Mfy2BBCLOYJN7Qkdzm7ik2M+G5adlT/jVWrtpZAQqQrGfiRy6PlVwzAVXSqOmsTU1AQETt81bFnPGsKETGuvzWqK4kguu+hUe0AuP+i0Y87wFhz8sU6no+kJsYRxtMwVGsw09wXJwRZL8TVeYGDVpHoJZLKgseoe1k8R1qe74G0Wr7AuYciU=", "Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-MS-Exchange-CrossTenant-Network-Message-Id": "405ce330-4222-43ca-520f-08d727b68f10", "X-MS-Exchange-CrossTenant-originalarrivaltime": "23 Aug 2019 10:42:13.5506\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "70e1fb47-1155-421d-87fc-2e58f638b6e0", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "hS6xRISMXCanOqlltFwGYP6531KnlGGGsTZBPzL2UcprndXrZAKBvogx8szMrQsjijx6QMbiobVR3R0Br+6XgY/TjS8O+PNJBaGSD0i/gPU=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB2830", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:5.22.84,1.0.8\n\tdefinitions=2019-08-23_04:2019-08-21,2019-08-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 04/11] crypto/nitrox: add basic symmetric\n\tcryptodev operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add the following cryptodev operations,\n- dev_configure\n- dev_start\n- dev_stop\n- dev_close\n- dev_infos_get\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n doc/guides/cryptodevs/features/nitrox.ini | 38 ++++++++++++\n doc/guides/cryptodevs/nitrox.rst | 37 +++++++++++\n drivers/crypto/nitrox/Makefile | 1 +\n drivers/crypto/nitrox/meson.build | 1 +\n drivers/crypto/nitrox/nitrox_sym.c | 81 ++++++++++++++++++++++++-\n drivers/crypto/nitrox/nitrox_sym_capabilities.c | 57 +++++++++++++++++\n drivers/crypto/nitrox/nitrox_sym_capabilities.h | 12 ++++\n 7 files changed, 226 insertions(+), 1 deletion(-)\n create mode 100644 doc/guides/cryptodevs/features/nitrox.ini\n create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.c\n create mode 100644 drivers/crypto/nitrox/nitrox_sym_capabilities.h", "diff": "diff --git a/doc/guides/cryptodevs/features/nitrox.ini b/doc/guides/cryptodevs/features/nitrox.ini\nnew file mode 100644\nindex 000000000..9f9e2619c\n--- /dev/null\n+++ b/doc/guides/cryptodevs/features/nitrox.ini\n@@ -0,0 +1,38 @@\n+;\n+; Supported features of the 'nitrox' crypto driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Symmetric crypto = Y\n+Sym operation chaining = Y\n+HW Accelerated = Y\n+In Place SGL = Y\n+OOP SGL In SGL Out = Y\n+OOP SGL In LB Out = Y\n+OOP LB In SGL Out = Y\n+OOP LB In LB Out = Y\n+\n+;\n+; Supported crypto algorithms of the 'nitrox' crypto driver.\n+;\n+[Cipher]\n+AES CBC (128) = Y\n+AES CBC (192) = Y\n+AES CBC (256) = Y\n+\n+;\n+; Supported authentication algorithms of the 'nitrox' crypto driver.\n+;\n+[Auth]\n+SHA1 HMAC = Y\n+\n+;\n+; Supported AEAD algorithms of the 'nitrox' crypto driver.\n+;\n+[AEAD]\n+\n+;\n+; Supported Asymmetric algorithms of the 'nitrox' crypto driver.\n+;\n+[Asymmetric]\ndiff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitrox.rst\nindex b6b86dda5..c16a5e393 100644\n--- a/doc/guides/cryptodevs/nitrox.rst\n+++ b/doc/guides/cryptodevs/nitrox.rst\n@@ -9,3 +9,40 @@ cryptographic operations to the NITROX V security processor. Detailed\n information about the NITROX V security processor can be obtained here:\n \n * https://www.marvell.com/security-solutions/nitrox-security-processors/nitrox-v/\n+\n+Features\n+--------\n+\n+Nitrox crypto PMD has support for:\n+\n+Cipher algorithms:\n+\n+* ``RTE_CRYPTO_CIPHER_AES_CBC``\n+\n+Hash algorithms:\n+\n+* ``RTE_CRYPTO_AUTH_SHA1_HMAC``\n+\n+Limitations\n+-----------\n+\n+* AES_CBC Cipher Only combination is not supported.\n+\n+Installation\n+------------\n+\n+For compiling the Nitrox crypto PMD, please check if the\n+CONFIG_RTE_LIBRTE_PMD_NITROX setting is set to `y` in config/common_base file.\n+\n+* ``CONFIG_RTE_LIBRTE_PMD_NITROX=y``\n+\n+Initialization\n+--------------\n+\n+Nitrox crypto PMD depend on Nitrox kernel PF driver being installed on the\n+platform. Nitrox PF driver is required to create VF devices which will\n+be used by the PMD. Each VF device can enable one cryptodev PMD.\n+\n+Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SDK\n+and it's installation instructions can be obtained from:\n+`Marvell Technical Documentation Portal <https://support.cavium.com/>`_.\ndiff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile\nindex 06c96ccd7..dedb74a34 100644\n--- a/drivers/crypto/nitrox/Makefile\n+++ b/drivers/crypto/nitrox/Makefile\n@@ -27,5 +27,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_logs.c\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_sym_capabilities.c\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build\nindex 1277cf58e..7c565c5a4 100644\n--- a/drivers/crypto/nitrox/meson.build\n+++ b/drivers/crypto/nitrox/meson.build\n@@ -13,4 +13,5 @@ sources = files(\n \t\t'nitrox_hal.c',\n \t\t'nitrox_logs.c',\n \t\t'nitrox_sym.c',\n+\t\t'nitrox_sym_capabilities.c',\n \t\t)\ndiff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nitrox_sym.c\nindex c72016dd0..c05042e54 100644\n--- a/drivers/crypto/nitrox/nitrox_sym.c\n+++ b/drivers/crypto/nitrox/nitrox_sym.c\n@@ -9,6 +9,7 @@\n \n #include \"nitrox_sym.h\"\n #include \"nitrox_device.h\"\n+#include \"nitrox_sym_capabilities.h\"\n #include \"nitrox_logs.h\"\n \n #define CRYPTODEV_NAME_NITROX_PMD crypto_nitrox\n@@ -25,6 +26,84 @@ static const struct rte_driver nitrox_rte_sym_drv = {\n \t.alias = nitrox_sym_drv_name\n };\n \n+static int nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev,\n+\t\t\t\t uint16_t qp_id);\n+\n+static int\n+nitrox_sym_dev_config(__rte_unused struct rte_cryptodev *cdev,\n+\t\t __rte_unused struct rte_cryptodev_config *config)\n+{\n+\treturn 0;\n+}\n+\n+static int\n+nitrox_sym_dev_start(__rte_unused struct rte_cryptodev *cdev)\n+{\n+\treturn 0;\n+}\n+\n+static void\n+nitrox_sym_dev_stop(__rte_unused struct rte_cryptodev *cdev)\n+{\n+}\n+\n+static int\n+nitrox_sym_dev_close(struct rte_cryptodev *cdev)\n+{\n+\tint i, ret;\n+\n+\tfor (i = 0; i < cdev->data->nb_queue_pairs; i++) {\n+\t\tret = nitrox_sym_dev_qp_release(cdev, i);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+nitrox_sym_dev_info_get(struct rte_cryptodev *cdev,\n+\t\t\tstruct rte_cryptodev_info *info)\n+{\n+\tstruct nitrox_sym_device *sym_dev = cdev->data->dev_private;\n+\tstruct nitrox_device *ndev = sym_dev->ndev;\n+\n+\tif (!info)\n+\t\treturn;\n+\n+\tinfo->max_nb_queue_pairs = ndev->nr_queues;\n+\tinfo->feature_flags = cdev->feature_flags;\n+\tinfo->capabilities = nitrox_get_sym_capabilities();\n+\tinfo->driver_id = nitrox_sym_drv_id;\n+\tinfo->sym.max_nb_sessions = 0;\n+}\n+\n+static int\n+nitrox_sym_dev_qp_release(struct rte_cryptodev *cdev, uint16_t qp_id)\n+{\n+\tRTE_SET_USED(cdev);\n+\tRTE_SET_USED(qp_id);\n+\treturn 0;\n+}\n+\n+static struct rte_cryptodev_ops nitrox_cryptodev_ops = {\n+\t.dev_configure\t\t= nitrox_sym_dev_config,\n+\t.dev_start\t\t= nitrox_sym_dev_start,\n+\t.dev_stop\t\t= nitrox_sym_dev_stop,\n+\t.dev_close\t\t= nitrox_sym_dev_close,\n+\t.dev_infos_get\t\t= nitrox_sym_dev_info_get,\n+\n+\t.stats_get\t\t= NULL,\n+\t.stats_reset\t\t= NULL,\n+\n+\t.queue_pair_setup\t= NULL,\n+\t.queue_pair_release = NULL,\n+\n+\t.sym_session_get_size = NULL,\n+\t.sym_session_configure = NULL,\n+\t.sym_session_clear = NULL\n+};\n+\n int\n nitrox_sym_pmd_create(struct nitrox_device *ndev)\n {\n@@ -50,7 +129,7 @@ nitrox_sym_pmd_create(struct nitrox_device *ndev)\n \n \tndev->rte_sym_dev.name = cdev->data->name;\n \tcdev->driver_id = nitrox_sym_drv_id;\n-\tcdev->dev_ops = NULL;\n+\tcdev->dev_ops = &nitrox_cryptodev_ops;\n \tcdev->enqueue_burst = NULL;\n \tcdev->dequeue_burst = NULL;\n \tcdev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_capabilities.c b/drivers/crypto/nitrox/nitrox_sym_capabilities.c\nnew file mode 100644\nindex 000000000..aa1ff2638\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_sym_capabilities.c\n@@ -0,0 +1,57 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include \"nitrox_sym_capabilities.h\"\n+\n+static const struct rte_cryptodev_capabilities nitrox_capabilities[] = {\n+\t{\t/* SHA1 HMAC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,\n+\t\t\t{.auth = {\n+\t\t\t\t.algo = RTE_CRYPTO_AUTH_SHA1_HMAC,\n+\t\t\t\t.block_size = 64,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 1,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 1,\n+\t\t\t\t\t.max = 20,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t},\n+\t\t\t\t.iv_size = { 0 }\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\t{\t/* AES CBC */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_CBC,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 8\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+const struct rte_cryptodev_capabilities *\n+nitrox_get_sym_capabilities(void)\n+{\n+\treturn nitrox_capabilities;\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_sym_capabilities.h b/drivers/crypto/nitrox/nitrox_sym_capabilities.h\nnew file mode 100644\nindex 000000000..cb2d97572\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_sym_capabilities.h\n@@ -0,0 +1,12 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_SYM_CAPABILITIES_H_\n+#define _NITROX_SYM_CAPABILITIES_H_\n+\n+#include <rte_cryptodev.h>\n+\n+const struct rte_cryptodev_capabilities *nitrox_get_sym_capabilities(void);\n+\n+#endif /* _NITROX_SYM_CAPABILITIES_H_ */\n", "prefixes": [ "v3", "04/11" ] }