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GET /api/patches/57832/?format=api
{ "id": 57832, "url": "https://patches.dpdk.org/api/patches/57832/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190823104144.19300-3-rnagadheeraj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190823104144.19300-3-rnagadheeraj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190823104144.19300-3-rnagadheeraj@marvell.com", "date": "2019-08-23T10:42:09", "name": "[v3,02/11] crypto/nitrox: add PCI probe and remove routines", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2b82ccb14f8df277b972bfb3ec48b266887a79ee", "submitter": { "id": 1365, "url": "https://patches.dpdk.org/api/people/1365/?format=api", "name": "Nagadheeraj Rottela", "email": "rnagadheeraj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190823104144.19300-3-rnagadheeraj@marvell.com/mbox/", "series": [ { "id": 6113, "url": "https://patches.dpdk.org/api/series/6113/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=6113", "date": "2019-08-23T10:42:05", "name": "add Nitrox crypto device support", "version": 3, "mbox": "https://patches.dpdk.org/series/6113/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57832/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/57832/checks/", "tags": {}, "related": [], "headers": { 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"BoMhVL52ReddqlzwPnlG3OVZLB+45ZIu4xG7ENH5kyacj5+eBukIocFaZ3Bw0U0NT+8uTImMpjw37WmR8+y8zAVw0mEZGLaZsqjDeJ8UbTM=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR18MB2830", "X-OriginatorOrg": "marvell.com", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:5.22.84,1.0.8\n\tdefinitions=2019-08-23_04:2019-08-21,2019-08-23 signatures=0", "Subject": "[dpdk-dev] [PATCH v3 02/11] crypto/nitrox: add PCI probe and remove\n\troutines", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add pci probe, remove and hardware init routines.\n\nSigned-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>\n---\n drivers/crypto/nitrox/Makefile | 1 +\n drivers/crypto/nitrox/meson.build | 1 +\n drivers/crypto/nitrox/nitrox_csr.h | 28 +++++++++\n drivers/crypto/nitrox/nitrox_device.c | 105 ++++++++++++++++++++++++++++++++++\n drivers/crypto/nitrox/nitrox_device.h | 18 ++++++\n drivers/crypto/nitrox/nitrox_hal.c | 86 ++++++++++++++++++++++++++++\n drivers/crypto/nitrox/nitrox_hal.h | 37 ++++++++++++\n 7 files changed, 276 insertions(+)\n create mode 100644 drivers/crypto/nitrox/nitrox_csr.h\n create mode 100644 drivers/crypto/nitrox/nitrox_device.h\n create mode 100644 drivers/crypto/nitrox/nitrox_hal.c\n create mode 100644 drivers/crypto/nitrox/nitrox_hal.h", "diff": "diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefile\nindex da33a1d2a..bc0220964 100644\n--- a/drivers/crypto/nitrox/Makefile\n+++ b/drivers/crypto/nitrox/Makefile\n@@ -24,5 +24,6 @@ LDLIBS += -lrte_cryptodev\n \n # library source files\n SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_device.c\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) += nitrox_hal.c\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meson.build\nindex 0afb14b00..f1c96b84d 100644\n--- a/drivers/crypto/nitrox/meson.build\n+++ b/drivers/crypto/nitrox/meson.build\n@@ -10,4 +10,5 @@ deps += ['bus_pci']\n allow_experimental_apis = true\n sources = files(\n \t\t'nitrox_device.c',\n+\t\t'nitrox_hal.c',\n \t\t)\ndiff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h\nnew file mode 100644\nindex 000000000..879104515\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_csr.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_CSR_H_\n+#define _NITROX_CSR_H_\n+\n+#include <rte_common.h>\n+#include <rte_io.h>\n+\n+#define CSR_DELAY\t30\n+\n+/* AQM Virtual Function Registers */\n+#define AQMQ_QSZX(_i)\t\t\t(0x20008 + ((_i)*0x40000))\n+\n+static inline uint64_t\n+nitrox_read_csr(uint8_t *bar_addr, uint64_t offset)\n+{\n+\treturn rte_read64(bar_addr + offset);\n+}\n+\n+static inline void\n+nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value)\n+{\n+\trte_write64(value, (bar_addr + offset));\n+}\n+\n+#endif /* _NITROX_CSR_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_device.c b/drivers/crypto/nitrox/nitrox_device.c\nindex d26535dee..5628c6d8b 100644\n--- a/drivers/crypto/nitrox/nitrox_device.c\n+++ b/drivers/crypto/nitrox/nitrox_device.c\n@@ -1,3 +1,108 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(C) 2019 Marvell International Ltd.\n */\n+\n+#include <rte_malloc.h>\n+\n+#include \"nitrox_device.h\"\n+#include \"nitrox_hal.h\"\n+\n+TAILQ_HEAD(ndev_list, nitrox_device);\n+static struct ndev_list ndev_list = TAILQ_HEAD_INITIALIZER(ndev_list);\n+\n+static struct nitrox_device *\n+ndev_allocate(struct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\tndev = rte_zmalloc_socket(\"nitrox device\", sizeof(*ndev),\n+\t\t\t\t RTE_CACHE_LINE_SIZE,\n+\t\t\t\t pdev->device.numa_node);\n+\tif (!ndev)\n+\t\treturn NULL;\n+\n+\tTAILQ_INSERT_TAIL(&ndev_list, ndev, next);\n+\treturn ndev;\n+}\n+\n+static void\n+ndev_init(struct nitrox_device *ndev, struct rte_pci_device *pdev)\n+{\n+\tenum nitrox_vf_mode vf_mode;\n+\n+\tndev->pdev = pdev;\n+\tndev->bar_addr = pdev->mem_resource[0].addr;\n+\tvf_mode = vf_get_vf_config_mode(ndev->bar_addr);\n+\tndev->nr_queues = vf_config_mode_to_nr_queues(vf_mode);\n+}\n+\n+static struct nitrox_device *\n+find_ndev(struct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\tTAILQ_FOREACH(ndev, &ndev_list, next)\n+\t\tif (ndev->pdev == pdev)\n+\t\t\treturn ndev;\n+\n+\treturn NULL;\n+}\n+\n+static void\n+ndev_release(struct nitrox_device *ndev)\n+{\n+\tif (!ndev)\n+\t\treturn;\n+\n+\tTAILQ_REMOVE(&ndev_list, ndev, next);\n+\trte_free(ndev);\n+}\n+\n+static int\n+nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t\tstruct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\t/* Nitrox CSR space */\n+\tif (!pdev->mem_resource[0].addr)\n+\t\treturn -EINVAL;\n+\n+\tndev = ndev_allocate(pdev);\n+\tif (!ndev)\n+\t\treturn -ENOMEM;\n+\n+\tndev_init(ndev, pdev);\n+\treturn 0;\n+}\n+\n+static int\n+nitrox_pci_remove(struct rte_pci_device *pdev)\n+{\n+\tstruct nitrox_device *ndev;\n+\n+\tndev = find_ndev(pdev);\n+\tif (!ndev)\n+\t\treturn -ENODEV;\n+\n+\tndev_release(ndev);\n+\treturn 0;\n+}\n+\n+static struct rte_pci_id pci_id_nitrox_map[] = {\n+\t{\n+\t\t/* Nitrox 5 VF */\n+\t\tRTE_PCI_DEVICE(0x177d, 0x13)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+static struct rte_pci_driver nitrox_pmd = {\n+\t.id_table = pci_id_nitrox_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING,\n+\t.probe = nitrox_pci_probe,\n+\t.remove = nitrox_pci_remove,\n+};\n+\n+RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map);\ndiff --git a/drivers/crypto/nitrox/nitrox_device.h b/drivers/crypto/nitrox/nitrox_device.h\nnew file mode 100644\nindex 000000000..0d0167de2\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_device.h\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_DEVICE_H_\n+#define _NITROX_DEVICE_H_\n+\n+#include <rte_bus_pci.h>\n+#include <rte_cryptodev.h>\n+\n+struct nitrox_device {\n+\tTAILQ_ENTRY(nitrox_device) next;\n+\tstruct rte_pci_device *pdev;\n+\tuint8_t *bar_addr;\n+\tuint16_t nr_queues;\n+};\n+\n+#endif /* _NITROX_DEVICE_H_ */\ndiff --git a/drivers/crypto/nitrox/nitrox_hal.c b/drivers/crypto/nitrox/nitrox_hal.c\nnew file mode 100644\nindex 000000000..3dee59215\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_hal.c\n@@ -0,0 +1,86 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_cycles.h>\n+#include <rte_memory.h>\n+#include <rte_byteorder.h>\n+\n+#include \"nitrox_hal.h\"\n+#include \"nitrox_csr.h\"\n+\n+#define MAX_VF_QUEUES\t8\n+#define MAX_PF_QUEUES\t64\n+\n+int\n+vf_get_vf_config_mode(uint8_t *bar_addr)\n+{\n+\tunion aqmq_qsz aqmq_qsz;\n+\tuint64_t reg_addr;\n+\tint q, vf_mode;\n+\n+\taqmq_qsz.u64 = 0;\n+\taqmq_qsz.s.host_queue_size = 0xDEADBEEF;\n+\n+\treg_addr = AQMQ_QSZX(0);\n+\tnitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64);\n+\trte_delay_us_block(CSR_DELAY);\n+\n+\taqmq_qsz.u64 = 0;\n+\tfor (q = 1; q < MAX_VF_QUEUES; q++) {\n+\t\treg_addr = AQMQ_QSZX(q);\n+\t\taqmq_qsz.u64 = nitrox_read_csr(bar_addr, reg_addr);\n+\t\tif (aqmq_qsz.s.host_queue_size == 0xDEADBEEF)\n+\t\t\tbreak;\n+\t}\n+\n+\tswitch (q) {\n+\tcase 1:\n+\t\tvf_mode = NITROX_MODE_VF128;\n+\t\tbreak;\n+\tcase 2:\n+\t\tvf_mode = NITROX_MODE_VF64;\n+\t\tbreak;\n+\tcase 4:\n+\t\tvf_mode = NITROX_MODE_VF32;\n+\t\tbreak;\n+\tcase 8:\n+\t\tvf_mode = NITROX_MODE_VF16;\n+\t\tbreak;\n+\tdefault:\n+\t\tvf_mode = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn vf_mode;\n+}\n+\n+int\n+vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode)\n+{\n+\tint nr_queues;\n+\n+\tswitch (vf_mode) {\n+\tcase NITROX_MODE_PF:\n+\t\tnr_queues = MAX_PF_QUEUES;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF16:\n+\t\tnr_queues = 8;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF32:\n+\t\tnr_queues = 4;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF64:\n+\t\tnr_queues = 2;\n+\t\tbreak;\n+\tcase NITROX_MODE_VF128:\n+\t\tnr_queues = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\tnr_queues = 0;\n+\t\tbreak;\n+\t}\n+\n+\treturn nr_queues;\n+}\ndiff --git a/drivers/crypto/nitrox/nitrox_hal.h b/drivers/crypto/nitrox/nitrox_hal.h\nnew file mode 100644\nindex 000000000..6184211a5\n--- /dev/null\n+++ b/drivers/crypto/nitrox/nitrox_hal.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef _NITROX_HAL_H_\n+#define _NITROX_HAL_H_\n+\n+#include <rte_cycles.h>\n+#include <rte_byteorder.h>\n+\n+#include \"nitrox_csr.h\"\n+\n+union aqmq_qsz {\n+\tuint64_t u64;\n+\tstruct {\n+#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN\n+\t\tuint64_t raz : 32;\n+\t\tuint64_t host_queue_size : 32;\n+#else\n+\t\tuint64_t host_queue_size : 32;\n+\t\tuint64_t raz : 32;\n+#endif\n+\t} s;\n+};\n+\n+enum nitrox_vf_mode {\n+\tNITROX_MODE_PF = 0x0,\n+\tNITROX_MODE_VF16 = 0x1,\n+\tNITROX_MODE_VF32 = 0x2,\n+\tNITROX_MODE_VF64 = 0x3,\n+\tNITROX_MODE_VF128 = 0x4,\n+};\n+\n+int vf_get_vf_config_mode(uint8_t *bar_addr);\n+int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode);\n+\n+#endif /* _NITROX_HAL_H_ */\n", "prefixes": [ "v3", "02/11" ] }