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GET /api/patches/57560/?format=api
{ "id": 57560, "url": "https://patches.dpdk.org/api/patches/57560/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/f48d1da56cba439783ffd9372c603cccd1135d49.1565252336.git.thierry.herbelot@6wind.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<f48d1da56cba439783ffd9372c603cccd1135d49.1565252336.git.thierry.herbelot@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/f48d1da56cba439783ffd9372c603cccd1135d49.1565252336.git.thierry.herbelot@6wind.com", "date": "2019-08-08T08:22:10", "name": "[19.11,V3,05/12] net/ixgbe: fix Tx descriptor status api", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "aeaca85ade850b4097704680a10aad42662b434f", "submitter": { "id": 897, "url": "https://patches.dpdk.org/api/people/897/?format=api", "name": "Thierry Herbelot", "email": "thierry.herbelot@6wind.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/f48d1da56cba439783ffd9372c603cccd1135d49.1565252336.git.thierry.herbelot@6wind.com/mbox/", "series": [ { "id": 5981, "url": "https://patches.dpdk.org/api/series/5981/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5981", "date": "2019-08-08T08:22:05", "name": "Miscellaneous fixes", "version": 3, "mbox": "https://patches.dpdk.org/series/5981/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/57560/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/57560/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 4B5A73253;\n\tThu, 8 Aug 2019 10:23:06 +0200 (CEST)", "from mail-wr1-f66.google.com (mail-wr1-f66.google.com\n\t[209.85.221.66]) by dpdk.org (Postfix) with ESMTP id 8DD472BA2\n\tfor <dev@dpdk.org>; Thu, 8 Aug 2019 10:22:56 +0200 (CEST)", "by mail-wr1-f66.google.com with SMTP id n9so94105683wru.0\n\tfor <dev@dpdk.org>; Thu, 08 Aug 2019 01:22:56 -0700 (PDT)", "from ascain.dev.6wind.com. (host.78.145.23.62.rev.coltfrance.com.\n\t[62.23.145.78]) by smtp.gmail.com with ESMTPSA id\n\tt13sm111437018wrr.0.2019.08.08.01.22.55\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 08 Aug 2019 01:22:55 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=6wind.com; s=google; \n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:in-reply-to:references;\n\tbh=8O5D8oaKajRKAycKCWBOPr1JPd+AjkcPPBYy+pLUd5Q=;\n\tb=Da64D8GakfVjCGz1+46dhpXw57VRQF4yJdcxD9OPXkdxX5Zw7BbhyIngAEtq75AeSZ\n\ttBlNSA8BSVgvy+chtVHfimndYDjDD2e/84iirbs2GQVLD3oHkidkLMTqyArQbSd29Qke\n\tg9IFLFP21fnusA/vVU6PY8+yOtfgKRuGZbMRMjAbvk+ChF24OmoN9rix4M5E0OnVitz6\n\tn+HP50vHpJGuxhDCL4INeJwe1JVrtM18yGj6AgugZh7eujHN+/icIplWG2/pnl/TfVoA\n\tyyStOx4aDclHTxNF3v/xxBqBvS5NxO7Lmu38LTvPQZe/Z7axTT8Q8i/nCw/WW7EecyEa\n\twFyg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:in-reply-to:references;\n\tbh=8O5D8oaKajRKAycKCWBOPr1JPd+AjkcPPBYy+pLUd5Q=;\n\tb=OHO9Vjng0RznvQjqEYRdqjmbWusPwwwmviXCh8eRSlo8L2phrsREUut1AFBYOf3/hF\n\tBcxrsLGgXG8lnA9QlTZZMBMs1yFioSmO05abFDQ1551iKvTReJ/E+kftjH1pJyar24Ke\n\tOBMndXomDptOYAP0gdWvxwA+PEl0rV6dYb8Nc4/2hDvb/vFnnILTKeCd84Y+yO0u+MSm\n\tqWszo0weiJ5eckkKbdiIFNaFDgiTEE8V/KhibFLiRYTG+HNS+e1zSc8bMVLDLWCO74zz\n\tDdWG8dOci2CcTx1kdn0oyXf1Ry7cO6cCautsywl5gNBP07huZygCD8d7V61oenYSnWp0\n\taaaw==", "X-Gm-Message-State": "APjAAAWJuI9vMv2kSmqXyTlgvYhRXD88PkBL1R4td0F5SfLoZPIyhn85\n\tXN6wVH2HE+gR+2Z/J8gCYuaBD9P4WQ==", "X-Google-Smtp-Source": "APXvYqz0G7NkO7YUKtQ8H1WN/9gHYkIhnQ9KNLp0qF9T5dZX5o1xrTYPA6lywhrPbhbc+FZ3s8OaOg==", "X-Received": "by 2002:adf:e390:: with SMTP id\n\te16mr6953998wrm.153.1565252576100; \n\tThu, 08 Aug 2019 01:22:56 -0700 (PDT)", "From": "Thierry Herbelot <thierry.herbelot@6wind.com>", "To": "dev@dpdk.org", "Cc": "Olivier Matz <olivier.matz@6wind.com>, stable@dpdk.org,\n\tThomas Monjalon <thomas@monjalon.net>", "Date": "Thu, 8 Aug 2019 10:22:10 +0200", "Message-Id": "<f48d1da56cba439783ffd9372c603cccd1135d49.1565252336.git.thierry.herbelot@6wind.com>", "X-Mailer": "git-send-email 2.11.0", "In-Reply-To": [ "<cover.1565252336.git.thierry.herbelot@6wind.com>", "<cover.1565252336.git.thierry.herbelot@6wind.com>" ], "References": [ "<cover.1565252336.git.thierry.herbelot@6wind.com>", "<cover.1565190405.git.thierry.herbelot@6wind.com>\n\t<cover.1565252336.git.thierry.herbelot@6wind.com>" ], "Subject": "[dpdk-dev] [PATCH 19.11 V3 05/12] net/ixgbe: fix Tx descriptor\n\tstatus api", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Olivier Matz <olivier.matz@6wind.com>\n\nThe Tx descriptor status api was not behaving as expected. This API is\nused to inspect the content of the descriptors in the Tx ring to\ndetermine the length of the Tx queue.\n\nSince the software advances the tail pointer and the hardware advances\nthe head pointer, the Tx queue is located before txq->tx_tail in the\nring. Therefore, a call to rte_eth_tx_descriptor_status(..., offset=20)\nshould inspect the 20th descriptor before the tail, not after.\n\nAs before, we still need to take care about only checking descriptors\nthat have the RS bit.\n\nAdditionally, we can avoid an access to the ring if offset is greater or\nequal to nb_tx_desc - nb_tx_free.\n\nFixes: 5da8b8814178 (\"net/ixgbe: implement descriptor status API\")\nCc: stable@dpdk.org\n\nSigned-off-by: Olivier Matz <olivier.matz@6wind.com>\n---\n drivers/net/ixgbe/ixgbe_rxtx.c | 45 +++++++++++++++++++++++++++++++-----------\n drivers/net/ixgbe/ixgbe_rxtx.h | 1 +\n 2 files changed, 34 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c\nindex edcfa60cec98..4abc2fe37488 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.c\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.c\n@@ -2627,10 +2627,15 @@ ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,\n \t hw->mac.type == ixgbe_mac_X540_vf ||\n \t hw->mac.type == ixgbe_mac_X550_vf ||\n \t hw->mac.type == ixgbe_mac_X550EM_x_vf ||\n-\t hw->mac.type == ixgbe_mac_X550EM_a_vf)\n+\t hw->mac.type == ixgbe_mac_X550EM_a_vf) {\n \t\ttxq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));\n-\telse\n+\t\ttxq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw,\n+\t\t\t\t\t\t IXGBE_VFTDH(queue_idx));\n+\t} else {\n \t\ttxq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));\n+\t\ttxq->tdh_reg_addr = IXGBE_PCI_REG_ADDR(hw,\n+\t\t\t\t\t\t IXGBE_TDH(txq->reg_idx));\n+\t}\n \n \ttxq->tx_ring_phys_addr = tz->iova;\n \ttxq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;\n@@ -3163,22 +3168,38 @@ ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)\n {\n \tstruct ixgbe_tx_queue *txq = tx_queue;\n \tvolatile uint32_t *status;\n-\tuint32_t desc;\n+\tint32_t desc, dd;\n \n \tif (unlikely(offset >= txq->nb_tx_desc))\n \t\treturn -EINVAL;\n+\tif (offset >= txq->nb_tx_desc - txq->nb_tx_free)\n+\t\treturn RTE_ETH_TX_DESC_DONE;\n+\n+\tdesc = txq->tx_tail - offset - 1;\n+\tif (desc < 0)\n+\t\tdesc += txq->nb_tx_desc;\n \n-\tdesc = txq->tx_tail + offset;\n-\t/* go to next desc that has the RS bit */\n-\tdesc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *\n-\t\ttxq->tx_rs_thresh;\n-\tif (desc >= txq->nb_tx_desc) {\n-\t\tdesc -= txq->nb_tx_desc;\n-\t\tif (desc >= txq->nb_tx_desc)\n-\t\t\tdesc -= txq->nb_tx_desc;\n+\t/* offset is too small, no other way than reading PCI reg */\n+\tif (unlikely(offset < txq->tx_rs_thresh)) {\n+\t\tint16_t tx_head, queue_size;\n+\t\ttx_head = ixgbe_read_addr(txq->tdh_reg_addr);\n+\t\tqueue_size = txq->tx_tail - tx_head;\n+\t\tif (queue_size < 0)\n+\t\t\tqueue_size += txq->nb_tx_desc;\n+\t\treturn queue_size > offset ? RTE_ETH_TX_DESC_FULL :\n+\t\t\tRTE_ETH_TX_DESC_DONE;\n \t}\n \n-\tstatus = &txq->tx_ring[desc].wb.status;\n+\t/* index of the dd bit to look at */\n+\tdd = (desc / txq->tx_rs_thresh + 1) * txq->tx_rs_thresh - 1;\n+\n+\t/* In full featured mode, RS bit is only set in the last descriptor */\n+\t/* of a multisegments packet */\n+\tif (!(txq->offloads == 0 &&\n+\t txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST))\n+\t\tdd = txq->sw_ring[dd].last_id;\n+\n+\tstatus = &txq->tx_ring[dd].wb.status;\n \tif (*status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD))\n \t\treturn RTE_ETH_TX_DESC_DONE;\n \ndiff --git a/drivers/net/ixgbe/ixgbe_rxtx.h b/drivers/net/ixgbe/ixgbe_rxtx.h\nindex 505d344b9cee..05fd4167576c 100644\n--- a/drivers/net/ixgbe/ixgbe_rxtx.h\n+++ b/drivers/net/ixgbe/ixgbe_rxtx.h\n@@ -201,6 +201,7 @@ struct ixgbe_tx_queue {\n \t\tstruct ixgbe_tx_entry_v *sw_ring_v; /**< address of SW ring for vector PMD */\n \t};\n \tvolatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */\n+\tvolatile uint32_t *tdh_reg_addr; /**< Address of TDH register. */\n \tuint16_t nb_tx_desc; /**< number of TX descriptors. */\n \tuint16_t tx_tail; /**< current value of TDT reg. */\n \t/**< Start freeing TX buffers if there are less free descriptors than\n", "prefixes": [ "19.11", "V3", "05/12" ] }