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GET /api/patches/56844/?format=api
{ "id": 56844, "url": "https://patches.dpdk.org/api/patches/56844/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1563786795-14027-20-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563786795-14027-20-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563786795-14027-20-git-send-email-matan@mellanox.com", "date": "2019-07-22T09:13:06", "name": "[19/28] net/mlx5: func to create Rx verbs completion queue", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "38598dcc9566bcbdb02f69dea6c11d23e1430e71", "submitter": { "id": 796, "url": "https://patches.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1563786795-14027-20-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 5639, "url": "https://patches.dpdk.org/api/series/5639/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5639", "date": "2019-07-22T09:12:48", "name": "net/mlx5: support LRO", "version": 1, "mbox": "https://patches.dpdk.org/series/5639/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/56844/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/56844/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 7A5D11BE6B;\n\tMon, 22 Jul 2019 11:14:16 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 5EFA01BDFA\n\tfor <dev@dpdk.org>; Mon, 22 Jul 2019 11:13:30 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tmatan@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 22 Jul 2019 12:13:24 +0300", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n\t[10.210.16.112])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6M9DMji010084;\n\tMon, 22 Jul 2019 12:13:24 +0300" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "Shahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "dev@dpdk.org, Dekel Peled <dekelp@mellanox.com>", "Date": "Mon, 22 Jul 2019 09:13:06 +0000", "Message-Id": "<1563786795-14027-20-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "References": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 19/28] net/mlx5: func to create Rx verbs\n\tcompletion queue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@mellanox.com>\n\nVerbs CQ for RxQ is created inside function mlx5_rxq_obj_new().\nThis patch moves the creation of CQ to dedicated function\nmlx5_ibv_cq_new().\n\nSigned-off-by: Dekel Peled <dekelp@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 159 +++++++++++++++++++++++++-------------------\n 1 file changed, 92 insertions(+), 67 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex d3bc3ee..e5015bb 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -831,6 +831,75 @@\n }\n \n /**\n+ * Create a CQ Verbs object.\n+ *\n+ * @param dev\n+ * Pointer to Ethernet device.\n+ * @param priv\n+ * Pointer to device private data.\n+ * @param rxq_data\n+ * Pointer to Rx queue data.\n+ * @param cqe_n\n+ * Number of CQEs in CQ.\n+ * @param rxq_obj\n+ * Pointer to Rx queue object data.\n+ *\n+ * @return\n+ * The Verbs object initialised, NULL otherwise and rte_errno is set.\n+ */\n+static struct ibv_cq *\n+mlx5_ibv_cq_new(struct rte_eth_dev *dev, struct mlx5_priv *priv,\n+\t\tstruct mlx5_rxq_data *rxq_data,\n+\t\tunsigned int cqe_n, struct mlx5_rxq_obj *rxq_obj)\n+{\n+\tstruct {\n+\t\tstruct ibv_cq_init_attr_ex ibv;\n+\t\tstruct mlx5dv_cq_init_attr mlx5;\n+\t} cq_attr;\n+\n+\tcq_attr.ibv = (struct ibv_cq_init_attr_ex){\n+\t\t.cqe = cqe_n,\n+\t\t.channel = rxq_obj->channel,\n+\t\t.comp_mask = 0,\n+\t};\n+\tcq_attr.mlx5 = (struct mlx5dv_cq_init_attr){\n+\t\t.comp_mask = 0,\n+\t};\n+\tif (priv->config.cqe_comp && !rxq_data->hw_timestamp) {\n+\t\tcq_attr.mlx5.comp_mask |=\n+\t\t\t\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;\n+#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n+\t\tcq_attr.mlx5.cqe_comp_res_format =\n+\t\t\t\tmlx5_rxq_mprq_enabled(rxq_data) ?\n+\t\t\t\tMLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :\n+\t\t\t\tMLX5DV_CQE_RES_FORMAT_HASH;\n+#else\n+\t\tcq_attr.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;\n+#endif\n+\t\t/*\n+\t\t * For vectorized Rx, it must not be doubled in order to\n+\t\t * make cq_ci and rq_ci aligned.\n+\t\t */\n+\t\tif (mlx5_rxq_check_vec_support(rxq_data) < 0)\n+\t\t\tcq_attr.ibv.cqe *= 2;\n+\t} else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {\n+\t\tDRV_LOG(DEBUG,\n+\t\t\t\"port %u Rx CQE compression is disabled for HW\"\n+\t\t\t\" timestamp\",\n+\t\t\tdev->data->port_id);\n+\t}\n+#ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD\n+\tif (priv->config.cqe_pad) {\n+\t\tcq_attr.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;\n+\t\tcq_attr.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;\n+\t}\n+#endif\n+\treturn mlx5_glue->cq_ex_to_cq(mlx5_glue->dv_create_cq(priv->sh->ctx,\n+\t\t\t\t\t\t\t &cq_attr.ibv,\n+\t\t\t\t\t\t\t &cq_attr.mlx5));\n+}\n+\n+/**\n * Create the Rx queue Verbs/DevX object.\n *\n * @param dev\n@@ -849,18 +918,12 @@ struct mlx5_rxq_obj *\n \tstruct mlx5_rxq_ctrl *rxq_ctrl =\n \t\tcontainer_of(rxq_data, struct mlx5_rxq_ctrl, rxq);\n \tstruct ibv_wq_attr mod;\n-\tunion {\n-\t\tstruct {\n-\t\t\tstruct ibv_cq_init_attr_ex ibv;\n-\t\t\tstruct mlx5dv_cq_init_attr mlx5;\n-\t\t} cq;\n-\t\tstruct {\n-\t\t\tstruct ibv_wq_init_attr ibv;\n+\tstruct {\n+\t\tstruct ibv_wq_init_attr ibv;\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n-\t\t\tstruct mlx5dv_wq_init_attr mlx5;\n+\t\tstruct mlx5dv_wq_init_attr mlx5;\n #endif\n-\t\t} wq;\n-\t} attr;\n+\t} wq_attr;\n \tunsigned int cqe_n;\n \tunsigned int wqe_n = 1 << rxq_data->elts_n;\n \tstruct mlx5_rxq_obj *tmpl = NULL;\n@@ -872,7 +935,7 @@ struct mlx5_rxq_obj *\n \tconst int mprq_en = mlx5_rxq_mprq_enabled(rxq_data);\n \n \tassert(rxq_data);\n-\tassert(!rxq_ctrl->ibv);\n+\tassert(!rxq_ctrl->obj);\n \tpriv->verbs_alloc_ctx.type = MLX5_VERBS_ALLOC_TYPE_RX_QUEUE;\n \tpriv->verbs_alloc_ctx.obj = rxq_ctrl;\n \ttmpl = rte_calloc_socket(__func__, 1, sizeof(*tmpl), 0,\n@@ -898,46 +961,8 @@ struct mlx5_rxq_obj *\n \t\tcqe_n = wqe_n * (1 << rxq_data->strd_num_n) - 1;\n \telse\n \t\tcqe_n = wqe_n - 1;\n-\tattr.cq.ibv = (struct ibv_cq_init_attr_ex){\n-\t\t.cqe = cqe_n,\n-\t\t.channel = tmpl->channel,\n-\t\t.comp_mask = 0,\n-\t};\n-\tattr.cq.mlx5 = (struct mlx5dv_cq_init_attr){\n-\t\t.comp_mask = 0,\n-\t};\n-\tif (config->cqe_comp && !rxq_data->hw_timestamp) {\n-\t\tattr.cq.mlx5.comp_mask |=\n-\t\t\tMLX5DV_CQ_INIT_ATTR_MASK_COMPRESSED_CQE;\n-#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n-\t\tattr.cq.mlx5.cqe_comp_res_format =\n-\t\t\tmprq_en ? MLX5DV_CQE_RES_FORMAT_CSUM_STRIDX :\n-\t\t\t\t MLX5DV_CQE_RES_FORMAT_HASH;\n-#else\n-\t\tattr.cq.mlx5.cqe_comp_res_format = MLX5DV_CQE_RES_FORMAT_HASH;\n-#endif\n-\t\t/*\n-\t\t * For vectorized Rx, it must not be doubled in order to\n-\t\t * make cq_ci and rq_ci aligned.\n-\t\t */\n-\t\tif (mlx5_rxq_check_vec_support(rxq_data) < 0)\n-\t\t\tattr.cq.ibv.cqe *= 2;\n-\t} else if (config->cqe_comp && rxq_data->hw_timestamp) {\n-\t\tDRV_LOG(DEBUG,\n-\t\t\t\"port %u Rx CQE compression is disabled for HW\"\n-\t\t\t\" timestamp\",\n-\t\t\tdev->data->port_id);\n-\t}\n-#ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD\n-\tif (config->cqe_pad) {\n-\t\tattr.cq.mlx5.comp_mask |= MLX5DV_CQ_INIT_ATTR_MASK_FLAGS;\n-\t\tattr.cq.mlx5.flags |= MLX5DV_CQ_INIT_ATTR_FLAGS_CQE_PAD;\n-\t}\n-#endif\n-\ttmpl->cq = mlx5_glue->cq_ex_to_cq\n-\t\t(mlx5_glue->dv_create_cq(priv->sh->ctx, &attr.cq.ibv,\n-\t\t\t\t\t &attr.cq.mlx5));\n-\tif (tmpl->cq == NULL) {\n+\ttmpl->cq = mlx5_ibv_cq_new(dev, priv, rxq_data, cqe_n, tmpl);\n+\tif (!tmpl->cq) {\n \t\tDRV_LOG(ERR, \"port %u Rx queue %u CQ creation failure\",\n \t\t\tdev->data->port_id, idx);\n \t\trte_errno = ENOMEM;\n@@ -947,7 +972,7 @@ struct mlx5_rxq_obj *\n \t\tdev->data->port_id, priv->sh->device_attr.orig_attr.max_qp_wr);\n \tDRV_LOG(DEBUG, \"port %u device_attr.max_sge is %d\",\n \t\tdev->data->port_id, priv->sh->device_attr.orig_attr.max_sge);\n-\tattr.wq.ibv = (struct ibv_wq_init_attr){\n+\twq_attr.ibv = (struct ibv_wq_init_attr){\n \t\t.wq_context = NULL, /* Could be useful in the future. */\n \t\t.wq_type = IBV_WQT_RQ,\n \t\t/* Max number of outstanding WRs. */\n@@ -965,37 +990,37 @@ struct mlx5_rxq_obj *\n \t};\n \t/* By default, FCS (CRC) is stripped by hardware. */\n \tif (rxq_data->crc_present) {\n-\t\tattr.wq.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;\n-\t\tattr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n+\t\twq_attr.ibv.create_flags |= IBV_WQ_FLAGS_SCATTER_FCS;\n+\t\twq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n \t}\n \tif (config->hw_padding) {\n #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)\n-\t\tattr.wq.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;\n-\t\tattr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n+\t\twq_attr.ibv.create_flags |= IBV_WQ_FLAG_RX_END_PADDING;\n+\t\twq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)\n-\t\tattr.wq.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;\n-\t\tattr.wq.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n+\t\twq_attr.ibv.create_flags |= IBV_WQ_FLAGS_PCI_WRITE_END_PADDING;\n+\t\twq_attr.ibv.comp_mask |= IBV_WQ_INIT_ATTR_FLAGS;\n #endif\n \t}\n #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT\n-\tattr.wq.mlx5 = (struct mlx5dv_wq_init_attr){\n+\twq_attr.mlx5 = (struct mlx5dv_wq_init_attr){\n \t\t.comp_mask = 0,\n \t};\n \tif (mprq_en) {\n \t\tstruct mlx5dv_striding_rq_init_attr *mprq_attr =\n-\t\t\t&attr.wq.mlx5.striding_rq_attrs;\n+\t\t\t&wq_attr.mlx5.striding_rq_attrs;\n \n-\t\tattr.wq.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;\n+\t\twq_attr.mlx5.comp_mask |= MLX5DV_WQ_INIT_ATTR_MASK_STRIDING_RQ;\n \t\t*mprq_attr = (struct mlx5dv_striding_rq_init_attr){\n \t\t\t.single_stride_log_num_of_bytes = rxq_data->strd_sz_n,\n \t\t\t.single_wqe_log_num_of_strides = rxq_data->strd_num_n,\n \t\t\t.two_byte_shift_en = MLX5_MPRQ_TWO_BYTE_SHIFT,\n \t\t};\n \t}\n-\ttmpl->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &attr.wq.ibv,\n-\t\t\t\t\t &attr.wq.mlx5);\n+\ttmpl->wq = mlx5_glue->dv_create_wq(priv->sh->ctx, &wq_attr.ibv,\n+\t\t\t\t\t &wq_attr.mlx5);\n #else\n-\ttmpl->wq = mlx5_glue->create_wq(priv->sh->ctx, &attr.wq.ibv);\n+\ttmpl->wq = mlx5_glue->create_wq(priv->sh->ctx, &wq_attr.ibv);\n #endif\n \tif (tmpl->wq == NULL) {\n \t\tDRV_LOG(ERR, \"port %u Rx queue %u WQ creation failure\",\n@@ -1007,14 +1032,14 @@ struct mlx5_rxq_obj *\n \t * Make sure number of WRs*SGEs match expectations since a queue\n \t * cannot allocate more than \"desc\" buffers.\n \t */\n-\tif (attr.wq.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||\n-\t attr.wq.ibv.max_sge != (1u << rxq_data->sges_n)) {\n+\tif (wq_attr.ibv.max_wr != (wqe_n >> rxq_data->sges_n) ||\n+\t wq_attr.ibv.max_sge != (1u << rxq_data->sges_n)) {\n \t\tDRV_LOG(ERR,\n \t\t\t\"port %u Rx queue %u requested %u*%u but got %u*%u\"\n \t\t\t\" WRs*SGEs\",\n \t\t\tdev->data->port_id, idx,\n \t\t\twqe_n >> rxq_data->sges_n, (1 << rxq_data->sges_n),\n-\t\t\tattr.wq.ibv.max_wr, attr.wq.ibv.max_sge);\n+\t\t\twq_attr.ibv.max_wr, wq_attr.ibv.max_sge);\n \t\trte_errno = EINVAL;\n \t\tgoto error;\n \t}\n", "prefixes": [ "19/28" ] }