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GET /api/patches/56824/?format=api
{ "id": 56824, "url": "https://patches.dpdk.org/api/patches/56824/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1563785065-12969-2-git-send-email-phil.yang@arm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563785065-12969-2-git-send-email-phil.yang@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563785065-12969-2-git-send-email-phil.yang@arm.com", "date": "2019-07-22T08:44:24", "name": "[v4,2/3] test/atomic: add 128b compare and swap test", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "919477ca92474ece412784869ed246a10ee8d854", "submitter": { "id": 833, "url": "https://patches.dpdk.org/api/people/833/?format=api", "name": "Phil Yang", "email": "phil.yang@arm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1563785065-12969-2-git-send-email-phil.yang@arm.com/mbox/", "series": [ { "id": 5638, "url": "https://patches.dpdk.org/api/series/5638/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5638", "date": "2019-07-22T08:44:23", "name": "[v4,1/3] eal/arm64: add 128-bit atomic compare exchange", "version": 4, "mbox": "https://patches.dpdk.org/series/5638/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/56824/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/56824/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8C14B1BDE0;\n\tMon, 22 Jul 2019 10:45:10 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n\tby dpdk.org (Postfix) with ESMTP id C83371BCB8\n\tfor <dev@dpdk.org>; Mon, 22 Jul 2019 10:45:08 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C6EF344;\n\tMon, 22 Jul 2019 01:45:08 -0700 (PDT)", "from phil-VirtualBox.shanghai.arm.com (unknown [10.169.109.155])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id\n\t695123F71F; Mon, 22 Jul 2019 01:45:06 -0700 (PDT)" ], "From": "Phil Yang <phil.yang@arm.com>", "To": "dev@dpdk.org", "Cc": "thomas@monjalon.net, jerinj@marvell.com, gage.eads@intel.com,\n\themant.agrawal@nxp.com, Honnappa.Nagarahalli@arm.com, gavin.hu@arm.com,\n\tnd@arm.com", "Date": "Mon, 22 Jul 2019 16:44:24 +0800", "Message-Id": "<1563785065-12969-2-git-send-email-phil.yang@arm.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1563785065-12969-1-git-send-email-phil.yang@arm.com>", "References": "<1561257671-10316-1-git-send-email-phil.yang@arm.com>\n\t<1563785065-12969-1-git-send-email-phil.yang@arm.com>", "Subject": "[dpdk-dev] [PATCH v4 2/3] test/atomic: add 128b compare and swap\n\ttest", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add 128b atomic compare and swap test for aarch64 and x86_64.\n\nSigned-off-by: Phil Yang <phil.yang@arm.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nAcked-by: Gage Eads <gage.eads@intel.com>\nAcked-by: Jerin Jacob <jerinj@marvell.com>\nTested-by: Jerin Jacob <jerinj@marvell.com>\n\n---\n app/test/test_atomic.c | 120 ++++++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 118 insertions(+), 2 deletions(-)", "diff": "diff --git a/app/test/test_atomic.c b/app/test/test_atomic.c\nindex 43be30e..ff6ff88 100644\n--- a/app/test/test_atomic.c\n+++ b/app/test/test_atomic.c\n@@ -1,5 +1,6 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright(c) 2010-2014 Intel Corporation\n+ * Copyright(c) 2019 Arm Limited\n */\n \n #include <stdio.h>\n@@ -20,7 +21,7 @@\n * Atomic Variables\n * ================\n *\n- * - The main test function performs three subtests. The first test\n+ * - The main test function performs four subtests. The first test\n * checks that the usual inc/dec/add/sub functions are working\n * correctly:\n *\n@@ -61,11 +62,27 @@\n * atomic_sub(&count, tmp+1);\n *\n * - At the end of the test, the *count* value must be 0.\n+ *\n+ * - Test \"128b compare and swap\" (aarch64 and x86_64 only)\n+ *\n+ * - Initialize 128-bit atomic variables to zero.\n+ *\n+ * - Invoke ``test_atomici128_cmp_exchange()`` on each lcore. Before doing\n+ * anything else, the cores are waiting a synchro. Each lcore does\n+ * these compare and swap (CAS) operations several times::\n+ *\n+ * Acquired CAS update counter.val[0] + 2; counter.val[1] + 1;\n+ * Released CAS update counter.val[0] + 2; counter.val[1] + 1;\n+ * Acquired_Released CAS update counter.val[0] + 2; counter.val[1] + 1;\n+ * Relaxed CAS update counter.val[0] + 2; counter.val[1] + 1;\n+ *\n+ * - At the end of the test, the *count128* first 64-bit value and\n+ * second 64-bit value differ by the total iterations.\n */\n \n #define NUM_ATOMIC_TYPES 3\n \n-#define N 10000\n+#define N 1000000\n \n static rte_atomic16_t a16;\n static rte_atomic32_t a32;\n@@ -216,6 +233,74 @@ test_atomic_dec_and_test(__attribute__((unused)) void *arg)\n \treturn 0;\n }\n \n+#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64)\n+static rte_int128_t count128;\n+\n+/*\n+ * rte_atomic128_cmp_exchange() should update a 128 bits counter's first 64\n+ * bits by 2 and the second 64 bits by 1 in this test. It should return true\n+ * if the compare exchange operation is successful.\n+ * This test repeats 128 bits compare and swap operations 10K rounds. In each\n+ * iteration it runs compare and swap operation with different memory models.\n+ */\n+static int\n+test_atomic128_cmp_exchange(__attribute__((unused)) void *arg)\n+{\n+\trte_int128_t expected;\n+\tint success;\n+\tunsigned int i;\n+\n+\twhile (rte_atomic32_read(&synchro) == 0)\n+\t\t;\n+\n+\texpected = count128;\n+\n+\tfor (i = 0; i < N; i++) {\n+\t\tdo {\n+\t\t\trte_int128_t desired;\n+\n+\t\t\tdesired.val[0] = expected.val[0] + 2;\n+\t\t\tdesired.val[1] = expected.val[1] + 1;\n+\n+\t\t\tsuccess = rte_atomic128_cmp_exchange(&count128, &expected,\n+\t\t\t\t\t&desired, 1, __ATOMIC_ACQUIRE, __ATOMIC_RELAXED);\n+\t\t} while (success == 0);\n+\n+\t\tdo {\n+\t\t\trte_int128_t desired;\n+\n+\t\t\tdesired.val[0] = expected.val[0] + 2;\n+\t\t\tdesired.val[1] = expected.val[1] + 1;\n+\n+\t\t\tsuccess = rte_atomic128_cmp_exchange(&count128, &expected,\n+\t\t\t\t\t&desired, 1, __ATOMIC_RELEASE, __ATOMIC_RELAXED);\n+\t\t} while (success == 0);\n+\n+\t\tdo {\n+\t\t\trte_int128_t desired;\n+\n+\t\t\tdesired.val[0] = expected.val[0] + 2;\n+\t\t\tdesired.val[1] = expected.val[1] + 1;\n+\n+\t\t\tsuccess = rte_atomic128_cmp_exchange(&count128, &expected,\n+\t\t\t\t\t&desired, 1, __ATOMIC_ACQ_REL, __ATOMIC_RELAXED);\n+\t\t} while (success == 0);\n+\n+\t\tdo {\n+\t\t\trte_int128_t desired;\n+\n+\t\t\tdesired.val[0] = expected.val[0] + 2;\n+\t\t\tdesired.val[1] = expected.val[1] + 1;\n+\n+\t\t\tsuccess = rte_atomic128_cmp_exchange(&count128, &expected,\n+\t\t\t\t\t&desired, 1, __ATOMIC_RELAXED, __ATOMIC_RELAXED);\n+\t\t} while (success == 0);\n+\t}\n+\n+\treturn 0;\n+}\n+#endif\n+\n static int\n test_atomic(void)\n {\n@@ -340,6 +425,37 @@ test_atomic(void)\n \t\treturn -1;\n \t}\n \n+#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_ARM64)\n+\t/*\n+\t * This case tests the functionality of rte_atomic128b_cmp_exchange\n+\t * API. It calls rte_atomic128b_cmp_exchange with four kinds of memory\n+\t * models successively on each slave core. Once each 128-bit atomic\n+\t * compare and swap operation is successful, it updates the global\n+\t * 128-bit counter by 2 for the first 64-bit and 1 for the second\n+\t * 64-bit. Each slave core iterates this test 10K times.\n+\t * At the end of test, verify whether the first 64-bits of the 128-bit\n+\t * counter and the second 64bits is differ by the total iterations. If\n+\t * it is, the test passes.\n+\t */\n+\tprintf(\"128b compare and swap test\\n\");\n+\tuint64_t iterations = 0;\n+\n+\trte_atomic32_clear(&synchro);\n+\tcount128.val[0] = 0;\n+\tcount128.val[1] = 0;\n+\n+\trte_eal_mp_remote_launch(test_atomic128_cmp_exchange, NULL, SKIP_MASTER);\n+\trte_atomic32_set(&synchro, 1);\n+\trte_eal_mp_wait_lcore();\n+\trte_atomic32_clear(&synchro);\n+\n+\titerations = count128.val[0] - count128.val[1];\n+\tif (iterations != 4*N*(rte_lcore_count()-1)) {\n+\t\tprintf(\"128b compare and swap failed\\n\");\n+\t\treturn -1;\n+\t}\n+#endif\n+\n \treturn 0;\n }\n \n", "prefixes": [ "v4", "2/3" ] }