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GET /api/patches/564/?format=api
{ "id": 564, "url": "https://patches.dpdk.org/api/patches/564/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411724018-7738-3-git-send-email-bjzhuc@cn.ibm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411724018-7738-3-git-send-email-bjzhuc@cn.ibm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411724018-7738-3-git-send-email-bjzhuc@cn.ibm.com", "date": "2014-09-26T09:33:33", "name": "[dpdk-dev,2/7] Split byte order operations to architecture specific", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6ccaa806d1bd4eb2a0ed1e47d6817b9187d0fb03", "submitter": { "id": 80, "url": "https://patches.dpdk.org/api/people/80/?format=api", "name": "Chao Zhu", "email": "bjzhuc@cn.ibm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411724018-7738-3-git-send-email-bjzhuc@cn.ibm.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/564/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/564/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 73E167E0C;\n\tFri, 26 Sep 2014 11:27:51 +0200 (CEST)", "from e7.ny.us.ibm.com (e7.ny.us.ibm.com [32.97.182.137])\n\tby dpdk.org (Postfix) with ESMTP id 615CC678C\n\tfor <dev@dpdk.org>; Fri, 26 Sep 2014 11:27:47 +0200 (CEST)", "from /spool/local\n\tby e7.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only!\n\tViolators will be prosecuted\n\tfor <dev@dpdk.org> from <bjzhuc@cn.ibm.com>;\n\tFri, 26 Sep 2014 05:34:08 -0400", "from d01dlp03.pok.ibm.com (9.56.250.168)\n\tby e7.ny.us.ibm.com (192.168.1.107) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tFri, 26 Sep 2014 05:34:05 -0400", "from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com\n\t[9.57.198.28])\n\tby d01dlp03.pok.ibm.com (Postfix) with ESMTP id 9AA04C90026\n\tfor <dev@dpdk.org>; Fri, 26 Sep 2014 05:22:49 -0400 (EDT)", "from d01av05.pok.ibm.com (d01av05.pok.ibm.com [9.56.224.195])\n\tby b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid\n\ts8Q9Xvn68585668 for <dev@dpdk.org>; Fri, 26 Sep 2014 09:34:05 GMT", "from d01av05.pok.ibm.com (localhost [127.0.0.1])\n\tby d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\ts8Q9XWE4000935 for <dev@dpdk.org>; Fri, 26 Sep 2014 05:33:32 -0400", "from d01hub02.pok.ibm.com (d01hub02.pok.ibm.com [9.63.10.236])\n\tby d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\ts8Q9XWET000704 for <dev@dpdk.org>; Fri, 26 Sep 2014 05:33:32 -0400", "from localhost.localdomain ([9.186.57.14])\n\tby rescrl1.research.ibm.com (IBM Domino Release 9.0.1)\n\twith ESMTP id 2014092617324308-312536 ;\n\tFri, 26 Sep 2014 17:32:43 +0800 " ], "From": "Chao Zhu <bjzhuc@cn.ibm.com>", "To": "dev@dpdk.org", "Date": "Fri, 26 Sep 2014 05:33:33 -0400", "Message-Id": "<1411724018-7738-3-git-send-email-bjzhuc@cn.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1411724018-7738-1-git-send-email-bjzhuc@cn.ibm.com>", "References": "<1411724018-7738-1-git-send-email-bjzhuc@cn.ibm.com>", "X-MIMETrack": "Itemize by SMTP Server on\n\trescrl1/Research/Affiliated/IBM(Release\n\t9.0.1|October 14, 2013) at 2014/09/26 17:32:43,\n\tSerialize by Router on D01HUB02/01/H/IBM(Release 8.5.3FP2\n\tZX853FP2HF5|February, 2013) at 09/26/2014 05:33:31,\n\tSerialize complete at 09/26/2014 05:33:31", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "14092609-5806-0000-0000-00000098F1B4", "Subject": "[dpdk-dev] [PATCH 2/7] Split byte order operations to architecture\n\tspecific", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch splits the byte order operations from DPDK and push them to\narchitecture specific arch directories, so that other processor\narchitecture to support DPDK can be easily adopted.\n\nSigned-off-by: Chao Zhu <bjzhuc@cn.ibm.com>\n---\n lib/librte_eal/common/Makefile | 2 +-\n .../common/include/i686/arch/rte_byteorder_arch.h | 95 ++++++++++++++++++++\n lib/librte_eal/common/include/rte_byteorder.h | 58 +------------\n .../include/x86_64/arch/rte_byteorder_arch.h | 95 ++++++++++++++++++++\n 4 files changed, 193 insertions(+), 57 deletions(-)\n create mode 100644 lib/librte_eal/common/include/i686/arch/rte_byteorder_arch.h\n create mode 100644 lib/librte_eal/common/include/x86_64/arch/rte_byteorder_arch.h", "diff": "diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex d730de5..d588c94 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -46,7 +46,7 @@ ifeq ($(CONFIG_RTE_INSECURE_FUNCTION_WARNING),y)\n INC += rte_warnings.h\n endif\n \n-ARCH_INC := rte_atomic.h rte_atomic_arch.h\n+ARCH_INC := rte_atomic.h rte_atomic_arch.h rte_byteorder_arch.h\n \n SYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include := $(addprefix include/,$(INC))\n SYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include/arch := \\\ndiff --git a/lib/librte_eal/common/include/i686/arch/rte_byteorder_arch.h b/lib/librte_eal/common/include/i686/arch/rte_byteorder_arch.h\nnew file mode 100644\nindex 0000000..06c1afc\n--- /dev/null\n+++ b/lib/librte_eal/common/include/i686/arch/rte_byteorder_arch.h\n@@ -0,0 +1,95 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_BYTEORDER_ARCH_H_\n+#define _RTE_BYTEORDER_ARCH_H_\n+\n+#include <stdint.h>\n+\n+/*\n+ * An architecture-optimized byte swap for a 16-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap16().\n+ */\n+static inline uint16_t rte_arch_bswap16(uint16_t _x)\n+{\n+\tregister uint16_t x = _x;\n+\tasm volatile (\"xchgb %b[x1],%h[x2]\"\n+\t\t : [x1] \"=Q\" (x)\n+\t\t : [x2] \"0\" (x)\n+\t\t );\n+\treturn x;\n+}\n+\n+/*\n+ * An architecture-optimized byte swap for a 32-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap32().\n+ */\n+static inline uint32_t rte_arch_bswap32(uint32_t _x)\n+{\n+\tregister uint32_t x = _x;\n+\tasm volatile (\"bswap %[x]\"\n+\t\t : [x] \"+r\" (x)\n+\t\t );\n+\treturn x;\n+}\n+\n+/*\n+ * An architecture-optimized byte swap for a 64-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap64().\n+ */\n+#ifdef RTE_ARCH_X86_64\n+/* 64-bit mode */\n+static inline uint64_t rte_arch_bswap64(uint64_t _x)\n+{\n+\tregister uint64_t x = _x;\n+\tasm volatile (\"bswap %[x]\"\n+\t\t : [x] \"+r\" (x)\n+\t\t );\n+\treturn x;\n+}\n+#else /* ! RTE_ARCH_X86_64 */\n+/* Compat./Leg. mode */\n+static inline uint64_t rte_arch_bswap64(uint64_t x)\n+{\n+\tuint64_t ret = 0;\n+\tret |= ((uint64_t)rte_arch_bswap32(x & 0xffffffffUL) << 32);\n+\tret |= ((uint64_t)rte_arch_bswap32((x >> 32) & 0xffffffffUL));\n+\treturn ret;\n+}\n+#endif /* RTE_ARCH_X86_64 */\n+\n+#endif /* _RTE_BYTEORDER_ARCH_H_ */\n+\ndiff --git a/lib/librte_eal/common/include/rte_byteorder.h b/lib/librte_eal/common/include/rte_byteorder.h\nindex 30fbd56..98e3764 100644\n--- a/lib/librte_eal/common/include/rte_byteorder.h\n+++ b/lib/librte_eal/common/include/rte_byteorder.h\n@@ -34,6 +34,8 @@\n #ifndef _RTE_BYTEORDER_H_\n #define _RTE_BYTEORDER_H_\n \n+#include \"arch/rte_byteorder_arch.h\"\n+\n /**\n * @file\n *\n@@ -96,62 +98,6 @@ rte_constant_bswap64(uint64_t x)\n \t\t((x & 0xff00000000000000ULL) >> 56);\n }\n \n-/*\n- * An architecture-optimized byte swap for a 16-bit value.\n- *\n- * Do not use this function directly. The preferred function is rte_bswap16().\n- */\n-static inline uint16_t rte_arch_bswap16(uint16_t _x)\n-{\n-\tregister uint16_t x = _x;\n-\tasm volatile (\"xchgb %b[x1],%h[x2]\"\n-\t\t : [x1] \"=Q\" (x)\n-\t\t : [x2] \"0\" (x)\n-\t\t );\n-\treturn x;\n-}\n-\n-/*\n- * An architecture-optimized byte swap for a 32-bit value.\n- *\n- * Do not use this function directly. The preferred function is rte_bswap32().\n- */\n-static inline uint32_t rte_arch_bswap32(uint32_t _x)\n-{\n-\tregister uint32_t x = _x;\n-\tasm volatile (\"bswap %[x]\"\n-\t\t : [x] \"+r\" (x)\n-\t\t );\n-\treturn x;\n-}\n-\n-/*\n- * An architecture-optimized byte swap for a 64-bit value.\n- *\n- * Do not use this function directly. The preferred function is rte_bswap64().\n- */\n-#ifdef RTE_ARCH_X86_64\n-/* 64-bit mode */\n-static inline uint64_t rte_arch_bswap64(uint64_t _x)\n-{\n-\tregister uint64_t x = _x;\n-\tasm volatile (\"bswap %[x]\"\n-\t\t : [x] \"+r\" (x)\n-\t\t );\n-\treturn x;\n-}\n-#else /* ! RTE_ARCH_X86_64 */\n-/* Compat./Leg. mode */\n-static inline uint64_t rte_arch_bswap64(uint64_t x)\n-{\n-\tuint64_t ret = 0;\n-\tret |= ((uint64_t)rte_arch_bswap32(x & 0xffffffffUL) << 32);\n-\tret |= ((uint64_t)rte_arch_bswap32((x >> 32) & 0xffffffffUL));\n-\treturn ret;\n-}\n-#endif /* RTE_ARCH_X86_64 */\n-\n-\n #ifndef RTE_FORCE_INTRINSICS\n /**\n * Swap bytes in a 16-bit value.\ndiff --git a/lib/librte_eal/common/include/x86_64/arch/rte_byteorder_arch.h b/lib/librte_eal/common/include/x86_64/arch/rte_byteorder_arch.h\nnew file mode 100644\nindex 0000000..06c1afc\n--- /dev/null\n+++ b/lib/librte_eal/common/include/x86_64/arch/rte_byteorder_arch.h\n@@ -0,0 +1,95 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_BYTEORDER_ARCH_H_\n+#define _RTE_BYTEORDER_ARCH_H_\n+\n+#include <stdint.h>\n+\n+/*\n+ * An architecture-optimized byte swap for a 16-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap16().\n+ */\n+static inline uint16_t rte_arch_bswap16(uint16_t _x)\n+{\n+\tregister uint16_t x = _x;\n+\tasm volatile (\"xchgb %b[x1],%h[x2]\"\n+\t\t : [x1] \"=Q\" (x)\n+\t\t : [x2] \"0\" (x)\n+\t\t );\n+\treturn x;\n+}\n+\n+/*\n+ * An architecture-optimized byte swap for a 32-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap32().\n+ */\n+static inline uint32_t rte_arch_bswap32(uint32_t _x)\n+{\n+\tregister uint32_t x = _x;\n+\tasm volatile (\"bswap %[x]\"\n+\t\t : [x] \"+r\" (x)\n+\t\t );\n+\treturn x;\n+}\n+\n+/*\n+ * An architecture-optimized byte swap for a 64-bit value.\n+ *\n+ * Do not use this function directly. The preferred function is rte_bswap64().\n+ */\n+#ifdef RTE_ARCH_X86_64\n+/* 64-bit mode */\n+static inline uint64_t rte_arch_bswap64(uint64_t _x)\n+{\n+\tregister uint64_t x = _x;\n+\tasm volatile (\"bswap %[x]\"\n+\t\t : [x] \"+r\" (x)\n+\t\t );\n+\treturn x;\n+}\n+#else /* ! RTE_ARCH_X86_64 */\n+/* Compat./Leg. mode */\n+static inline uint64_t rte_arch_bswap64(uint64_t x)\n+{\n+\tuint64_t ret = 0;\n+\tret |= ((uint64_t)rte_arch_bswap32(x & 0xffffffffUL) << 32);\n+\tret |= ((uint64_t)rte_arch_bswap32((x >> 32) & 0xffffffffUL));\n+\treturn ret;\n+}\n+#endif /* RTE_ARCH_X86_64 */\n+\n+#endif /* _RTE_BYTEORDER_ARCH_H_ */\n+\n", "prefixes": [ "dpdk-dev", "2/7" ] }