Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/561/?format=api
{ "id": 561, "url": "https://patches.dpdk.org/api/patches/561/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411724018-7738-6-git-send-email-bjzhuc@cn.ibm.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411724018-7738-6-git-send-email-bjzhuc@cn.ibm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411724018-7738-6-git-send-email-bjzhuc@cn.ibm.com", "date": "2014-09-26T09:33:36", "name": "[dpdk-dev,5/7] Split spinlock operations to architecture specific", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6e8c567791838b388d8fa61a16a5c471c1b00890", "submitter": { "id": 80, "url": "https://patches.dpdk.org/api/people/80/?format=api", "name": "Chao Zhu", "email": "bjzhuc@cn.ibm.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411724018-7738-6-git-send-email-bjzhuc@cn.ibm.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/561/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 682AE7DEB;\n\tFri, 26 Sep 2014 11:27:48 +0200 (CEST)", "from e9.ny.us.ibm.com (e9.ny.us.ibm.com [32.97.182.139])\n\tby dpdk.org (Postfix) with ESMTP id 48ACA678C\n\tfor <dev@dpdk.org>; Fri, 26 Sep 2014 11:27:46 +0200 (CEST)", "from /spool/local\n\tby e9.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only!\n\tViolators will be prosecuted\n\tfor <dev@dpdk.org> from <bjzhuc@cn.ibm.com>;\n\tFri, 26 Sep 2014 05:34:07 -0400", "from d01dlp02.pok.ibm.com (9.56.250.167)\n\tby e9.ny.us.ibm.com (192.168.1.109) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tFri, 26 Sep 2014 05:34:05 -0400", "from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com\n\t[9.57.198.24])\n\tby d01dlp02.pok.ibm.com (Postfix) with ESMTP id 29C8E6E8041\n\tfor <dev@dpdk.org>; Fri, 26 Sep 2014 05:22:50 -0400 (EDT)", "from d01av05.pok.ibm.com (d01av05.pok.ibm.com [9.56.224.195])\n\tby b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP\n\tid\n\ts8Q9Xvh65243382 for <dev@dpdk.org>; Fri, 26 Sep 2014 09:34:05 GMT", "from d01av05.pok.ibm.com (localhost [127.0.0.1])\n\tby d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\ts8Q9XWbi000944 for <dev@dpdk.org>; Fri, 26 Sep 2014 05:33:32 -0400", "from d01hub02.pok.ibm.com (d01hub02.pok.ibm.com [9.63.10.236])\n\tby d01av05.pok.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\ts8Q9XWEW000704 for <dev@dpdk.org>; Fri, 26 Sep 2014 05:33:32 -0400", "from localhost.localdomain ([9.186.57.14])\n\tby rescrl1.research.ibm.com (IBM Domino Release 9.0.1)\n\twith ESMTP id 2014092617324658-312539 ;\n\tFri, 26 Sep 2014 17:32:46 +0800 " ], "From": "Chao Zhu <bjzhuc@cn.ibm.com>", "To": "dev@dpdk.org", "Date": "Fri, 26 Sep 2014 05:33:36 -0400", "Message-Id": "<1411724018-7738-6-git-send-email-bjzhuc@cn.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1411724018-7738-1-git-send-email-bjzhuc@cn.ibm.com>", "References": "<1411724018-7738-1-git-send-email-bjzhuc@cn.ibm.com>", "X-MIMETrack": "Itemize by SMTP Server on\n\trescrl1/Research/Affiliated/IBM(Release\n\t9.0.1|October 14, 2013) at 2014/09/26 17:32:46,\n\tSerialize by Router on D01HUB02/01/H/IBM(Release 8.5.3FP2\n\tZX853FP2HF5|February, 2013) at 09/26/2014 05:33:32,\n\tSerialize complete at 09/26/2014 05:33:32", "X-TM-AS-MML": "disable", "X-Content-Scanned": "Fidelis XPS MAILER", "x-cbid": "14092609-7182-0000-0000-0000008E3760", "Subject": "[dpdk-dev] [PATCH 5/7] Split spinlock operations to architecture\n\tspecific", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch splits the spinlock operations from DPDK and push them to\narchitecture specific arch directories, so that other processor\narchitecture to support DPDK can be easily adopted.\n\nSigned-off-by: Chao Zhu <bjzhuc@cn.ibm.com>\n---\n lib/librte_eal/common/Makefile | 2 +-\n .../common/include/i686/arch/rte_spinlock_arch.h | 128 ++++++++++++++++++++\n lib/librte_eal/common/include/rte_spinlock.h | 55 +--------\n .../common/include/x86_64/arch/rte_spinlock_arch.h | 128 ++++++++++++++++++++\n 4 files changed, 261 insertions(+), 52 deletions(-)\n create mode 100644 lib/librte_eal/common/include/i686/arch/rte_spinlock_arch.h\n create mode 100644 lib/librte_eal/common/include/x86_64/arch/rte_spinlock_arch.h\n\n\\ No newline at end of file", "diff": "diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile\nindex bb175ca..249ea2f 100644\n--- a/lib/librte_eal/common/Makefile\n+++ b/lib/librte_eal/common/Makefile\n@@ -46,7 +46,7 @@ ifeq ($(CONFIG_RTE_INSECURE_FUNCTION_WARNING),y)\n INC += rte_warnings.h\n endif\n \n-ARCH_INC := rte_atomic.h rte_atomic_arch.h rte_byteorder_arch.h rte_cycles_arch.h rte_prefetch_arch.h\n+ARCH_INC := rte_atomic.h rte_atomic_arch.h rte_byteorder_arch.h rte_cycles_arch.h rte_prefetch_arch.h rte_spinlock_arch.h\n \n SYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include := $(addprefix include/,$(INC))\n SYMLINK-$(CONFIG_RTE_LIBRTE_EAL)-include/arch := \\\ndiff --git a/lib/librte_eal/common/include/i686/arch/rte_spinlock_arch.h b/lib/librte_eal/common/include/i686/arch/rte_spinlock_arch.h\nnew file mode 100644\nindex 0000000..2b13dcd\n--- /dev/null\n+++ b/lib/librte_eal/common/include/i686/arch/rte_spinlock_arch.h\n@@ -0,0 +1,128 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_SPINLOCK_ARCH_H_\n+#define _RTE_SPINLOCK_ARCH_H_\n+\n+#include <rte_lcore.h>\n+#ifdef RTE_FORCE_INTRINSICS\n+#include <rte_common.h>\n+#endif\n+\n+/**\n+ * The rte_spinlock_t type.\n+ */\n+typedef struct {\n+\tvolatile int locked; /**< lock status 0 = unlocked, 1 = locked */\n+} rte_spinlock_t;\n+\n+/**\n+ * Take the spinlock.\n+ *\n+ * @param sl\n+ * A pointer to the spinlock.\n+ */\n+static inline void\n+rte_arch_spinlock_lock(rte_spinlock_t *sl)\n+{\n+#ifndef RTE_FORCE_INTRINSICS\n+\tint lock_val = 1;\n+\tasm volatile (\n+\t\t\t\"1:\\n\"\n+\t\t\t\"xchg %[locked], %[lv]\\n\"\n+\t\t\t\"test %[lv], %[lv]\\n\"\n+\t\t\t\"jz 3f\\n\"\n+\t\t\t\"2:\\n\"\n+\t\t\t\"pause\\n\"\n+\t\t\t\"cmpl $0, %[locked]\\n\"\n+\t\t\t\"jnz 2b\\n\"\n+\t\t\t\"jmp 1b\\n\"\n+\t\t\t\"3:\\n\"\n+\t\t\t: [locked] \"=m\" (sl->locked), [lv] \"=q\" (lock_val)\n+\t\t\t: \"[lv]\" (lock_val)\n+\t\t\t: \"memory\");\n+#else\n+\twhile (__sync_lock_test_and_set(&sl->locked, 1))\n+\t\twhile(sl->locked)\n+\t\t\trte_pause();\n+#endif\n+}\n+\n+/**\n+ * Release the spinlock.\n+ *\n+ * @param sl\n+ * A pointer to the spinlock.\n+ */\n+static inline void\n+rte_arch_spinlock_unlock (rte_spinlock_t *sl)\n+{\n+#ifndef RTE_FORCE_INTRINSICS\n+\tint unlock_val = 0;\n+\tasm volatile (\n+\t\t\t\"xchg %[locked], %[ulv]\\n\"\n+\t\t\t: [locked] \"=m\" (sl->locked), [ulv] \"=q\" (unlock_val)\n+\t\t\t: \"[ulv]\" (unlock_val)\n+\t\t\t: \"memory\");\n+#else\n+\t__sync_lock_release(&sl->locked);\n+#endif\n+}\n+\n+/**\n+ * Try to take the lock.\n+ *\n+ * @param sl\n+ * A pointer to the spinlock.\n+ * @return\n+ * 1 if the lock is successfully taken; 0 otherwise.\n+ */\n+static inline int\n+rte_arch_spinlock_trylock (rte_spinlock_t *sl)\n+{\n+#ifndef RTE_FORCE_INTRINSICS\n+\tint lockval = 1;\n+\n+\tasm volatile (\n+\t\t\t\"xchg %[locked], %[lockval]\"\n+\t\t\t: [locked] \"=m\" (sl->locked), [lockval] \"=q\" (lockval)\n+\t\t\t: \"[lockval]\" (lockval)\n+\t\t\t: \"memory\");\n+\n+\treturn (lockval == 0);\n+#else\n+\treturn (__sync_lock_test_and_set(&sl->locked,1) == 0);\n+#endif\n+}\n+\n+#endif /* _RTE_SPINLOCK_ARCH_H_ */\n\\ No newline at end of file\ndiff --git a/lib/librte_eal/common/include/rte_spinlock.h b/lib/librte_eal/common/include/rte_spinlock.h\nindex 661908d..1cab17f 100644\n--- a/lib/librte_eal/common/include/rte_spinlock.h\n+++ b/lib/librte_eal/common/include/rte_spinlock.h\n@@ -55,13 +55,7 @@ extern \"C\" {\n #ifdef RTE_FORCE_INTRINSICS\n #include <rte_common.h>\n #endif\n-\n-/**\n- * The rte_spinlock_t type.\n- */\n-typedef struct {\n-\tvolatile int locked; /**< lock status 0 = unlocked, 1 = locked */\n-} rte_spinlock_t;\n+#include <arch/rte_spinlock_arch.h>\n \n /**\n * A static spinlock initializer.\n@@ -89,27 +83,7 @@ rte_spinlock_init(rte_spinlock_t *sl)\n static inline void\n rte_spinlock_lock(rte_spinlock_t *sl)\n {\n-#ifndef RTE_FORCE_INTRINSICS\n-\tint lock_val = 1;\n-\tasm volatile (\n-\t\t\t\"1:\\n\"\n-\t\t\t\"xchg %[locked], %[lv]\\n\"\n-\t\t\t\"test %[lv], %[lv]\\n\"\n-\t\t\t\"jz 3f\\n\"\n-\t\t\t\"2:\\n\"\n-\t\t\t\"pause\\n\"\n-\t\t\t\"cmpl $0, %[locked]\\n\"\n-\t\t\t\"jnz 2b\\n\"\n-\t\t\t\"jmp 1b\\n\"\n-\t\t\t\"3:\\n\"\n-\t\t\t: [locked] \"=m\" (sl->locked), [lv] \"=q\" (lock_val)\n-\t\t\t: \"[lv]\" (lock_val)\n-\t\t\t: \"memory\");\n-#else\n-\twhile (__sync_lock_test_and_set(&sl->locked, 1))\n-\t\twhile(sl->locked)\n-\t\t\trte_pause();\n-#endif\n+\trte_arch_spinlock_lock(sl);\n }\n \n /**\n@@ -121,16 +95,7 @@ rte_spinlock_lock(rte_spinlock_t *sl)\n static inline void\n rte_spinlock_unlock (rte_spinlock_t *sl)\n {\n-#ifndef RTE_FORCE_INTRINSICS\n-\tint unlock_val = 0;\n-\tasm volatile (\n-\t\t\t\"xchg %[locked], %[ulv]\\n\"\n-\t\t\t: [locked] \"=m\" (sl->locked), [ulv] \"=q\" (unlock_val)\n-\t\t\t: \"[ulv]\" (unlock_val)\n-\t\t\t: \"memory\");\n-#else\n-\t__sync_lock_release(&sl->locked);\n-#endif\n+\trte_arch_spinlock_unlock(sl);\n }\n \n /**\n@@ -144,19 +109,7 @@ rte_spinlock_unlock (rte_spinlock_t *sl)\n static inline int\n rte_spinlock_trylock (rte_spinlock_t *sl)\n {\n-#ifndef RTE_FORCE_INTRINSICS\n-\tint lockval = 1;\n-\n-\tasm volatile (\n-\t\t\t\"xchg %[locked], %[lockval]\"\n-\t\t\t: [locked] \"=m\" (sl->locked), [lockval] \"=q\" (lockval)\n-\t\t\t: \"[lockval]\" (lockval)\n-\t\t\t: \"memory\");\n-\n-\treturn (lockval == 0);\n-#else\n-\treturn (__sync_lock_test_and_set(&sl->locked,1) == 0);\n-#endif\n+\treturn rte_arch_spinlock_trylock(sl);\n }\n \n /**\ndiff --git a/lib/librte_eal/common/include/x86_64/arch/rte_spinlock_arch.h b/lib/librte_eal/common/include/x86_64/arch/rte_spinlock_arch.h\nnew file mode 100644\nindex 0000000..2b13dcd\n--- /dev/null\n+++ b/lib/librte_eal/common/include/x86_64/arch/rte_spinlock_arch.h\n@@ -0,0 +1,128 @@\n+/*-\n+ * BSD LICENSE\n+ *\n+ * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions\n+ * are met:\n+ *\n+ * * Redistributions of source code must retain the above copyright\n+ * notice, this list of conditions and the following disclaimer.\n+ * * Redistributions in binary form must reproduce the above copyright\n+ * notice, this list of conditions and the following disclaimer in\n+ * the documentation and/or other materials provided with the\n+ * distribution.\n+ * * Neither the name of Intel Corporation nor the names of its\n+ * contributors may be used to endorse or promote products derived\n+ * from this software without specific prior written permission.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\n+ * \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\n+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\n+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\n+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\n+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\n+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#ifndef _RTE_SPINLOCK_ARCH_H_\n+#define _RTE_SPINLOCK_ARCH_H_\n+\n+#include <rte_lcore.h>\n+#ifdef RTE_FORCE_INTRINSICS\n+#include <rte_common.h>\n+#endif\n+\n+/**\n+ * The rte_spinlock_t type.\n+ */\n+typedef struct {\n+\tvolatile int locked; /**< lock status 0 = unlocked, 1 = locked */\n+} rte_spinlock_t;\n+\n+/**\n+ * Take the spinlock.\n+ *\n+ * @param sl\n+ * A pointer to the spinlock.\n+ */\n+static inline void\n+rte_arch_spinlock_lock(rte_spinlock_t *sl)\n+{\n+#ifndef RTE_FORCE_INTRINSICS\n+\tint lock_val = 1;\n+\tasm volatile (\n+\t\t\t\"1:\\n\"\n+\t\t\t\"xchg %[locked], %[lv]\\n\"\n+\t\t\t\"test %[lv], %[lv]\\n\"\n+\t\t\t\"jz 3f\\n\"\n+\t\t\t\"2:\\n\"\n+\t\t\t\"pause\\n\"\n+\t\t\t\"cmpl $0, %[locked]\\n\"\n+\t\t\t\"jnz 2b\\n\"\n+\t\t\t\"jmp 1b\\n\"\n+\t\t\t\"3:\\n\"\n+\t\t\t: [locked] \"=m\" (sl->locked), [lv] \"=q\" (lock_val)\n+\t\t\t: \"[lv]\" (lock_val)\n+\t\t\t: \"memory\");\n+#else\n+\twhile (__sync_lock_test_and_set(&sl->locked, 1))\n+\t\twhile(sl->locked)\n+\t\t\trte_pause();\n+#endif\n+}\n+\n+/**\n+ * Release the spinlock.\n+ *\n+ * @param sl\n+ * A pointer to the spinlock.\n+ */\n+static inline void\n+rte_arch_spinlock_unlock (rte_spinlock_t *sl)\n+{\n+#ifndef RTE_FORCE_INTRINSICS\n+\tint unlock_val = 0;\n+\tasm volatile (\n+\t\t\t\"xchg %[locked], %[ulv]\\n\"\n+\t\t\t: [locked] \"=m\" (sl->locked), [ulv] \"=q\" (unlock_val)\n+\t\t\t: \"[ulv]\" (unlock_val)\n+\t\t\t: \"memory\");\n+#else\n+\t__sync_lock_release(&sl->locked);\n+#endif\n+}\n+\n+/**\n+ * Try to take the lock.\n+ *\n+ * @param sl\n+ * A pointer to the spinlock.\n+ * @return\n+ * 1 if the lock is successfully taken; 0 otherwise.\n+ */\n+static inline int\n+rte_arch_spinlock_trylock (rte_spinlock_t *sl)\n+{\n+#ifndef RTE_FORCE_INTRINSICS\n+\tint lockval = 1;\n+\n+\tasm volatile (\n+\t\t\t\"xchg %[locked], %[lockval]\"\n+\t\t\t: [locked] \"=m\" (sl->locked), [lockval] \"=q\" (lockval)\n+\t\t\t: \"[lockval]\" (lockval)\n+\t\t\t: \"memory\");\n+\n+\treturn (lockval == 0);\n+#else\n+\treturn (__sync_lock_test_and_set(&sl->locked,1) == 0);\n+#endif\n+}\n+\n+#endif /* _RTE_SPINLOCK_ARCH_H_ */\n", "prefixes": [ "dpdk-dev", "5/7" ] }