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GET /api/patches/55641/?format=api
{ "id": 55641, "url": "https://patches.dpdk.org/api/patches/55641/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190628182354.228-37-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628182354.228-37-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-37-pbhagavatula@marvell.com", "date": "2019-06-28T18:23:47", "name": "[v3,36/42] event/octeontx2: add event timer arm routine", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "57366467ade057339e3b7a7871636ffe3175be6b", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190628182354.228-37-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5227, "url": "https://patches.dpdk.org/api/series/5227/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5227", "date": "2019-06-28T18:23:11", "name": "OCTEONTX2 event device driver", "version": 3, "mbox": "https://patches.dpdk.org/series/5227/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/55641/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/55641/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 52C611BB7A;\n\tFri, 28 Jun 2019 20:25:46 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id ED6F01BA83\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:25:24 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIKhoZ010889 for <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:24 -0700", "from sc-exch02.marvell.com ([199.233.58.182])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agqn-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:24 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH02.marvell.com\n\t(10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:25:22 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:25:22 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id 76B6E3F7040;\n\tFri, 28 Jun 2019 11:25:21 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=BQwxjAA0nBTmNWMKC+5B2YEG+iyfLR02ZmJbjTNp7CI=;\n\tb=lqgqHb+GaphQ4ou/LuwOlBm4fVryNTdhuhq6hOWQESQeUVaMiVBmCLnKkL1oMHdao3uv\n\tQesF28+asXYqJ+kVoh9mwiA9cMOIGwIiAZtkjDLB61dWgOK+9fW5XWcOdwcpC2T2Oeb2\n\tQurtl3SQ3xTC+SsjZ/ZbK7qM6BlaZJE96h6Fozc6xtrhJAAjXZqTyiqXN45/eWVoeEQG\n\tjzR0fT94TKYocHuFU+Z1A5qFCVktEdJQb5VFUqjrouQ9uEQlHQWyB+l7B34Q0nHWDs8S\n\tyX0v4sgizEDVeEQnK0ACVTNPhSpfyOIsPdkR8PrGwh9n0GU6bH4Y5eT6ZTWdOLE/MYqg\n\twQ== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 28 Jun 2019 23:53:47 +0530", "Message-ID": "<20190628182354.228-37-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>", "References": "<20190628182354.228-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v3 36/42] event/octeontx2: add event timer arm\n\troutine", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd event timer arm routine.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 20 +++\n drivers/event/octeontx2/otx2_tim_evdev.h | 33 ++++\n drivers/event/octeontx2/otx2_tim_worker.c | 77 ++++++++\n drivers/event/octeontx2/otx2_tim_worker.h | 204 ++++++++++++++++++++++\n 4 files changed, 334 insertions(+)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex f2c14faaa..f4651c281 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -29,6 +29,23 @@ tim_get_msix_offsets(void)\n \treturn rc;\n }\n \n+static void\n+tim_set_fp_ops(struct otx2_tim_ring *tim_ring)\n+{\n+\tuint8_t prod_flag = !tim_ring->prod_type_sp;\n+\n+\t/* [MOD/AND] [DFB/FB] [SP][MP]*/\n+\tconst rte_event_timer_arm_burst_t arm_burst[2][2][2] = {\n+#define FP(_name, _f3, _f2, _f1, flags) \\\n+\t\t[_f3][_f2][_f1] = otx2_tim_arm_burst_ ## _name,\n+TIM_ARM_FASTPATH_MODES\n+#undef FP\n+\t};\n+\n+\totx2_tim_ops.arm_burst = arm_burst[tim_ring->optimized]\n+\t\t\t\t[tim_ring->ena_dfb][prod_flag];\n+}\n+\n static void\n otx2_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,\n \t\t struct rte_event_timer_adapter_info *adptr_info)\n@@ -326,6 +343,9 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n \t\t tim_ring->base + TIM_LF_RING_BASE);\n \totx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);\n \n+\t/* Set fastpath ops. */\n+\ttim_set_fp_ops(tim_ring);\n+\n \t/* Update SSO xae count. */\n \tsso_updt_xae_cnt(sso_pmd_priv(dev->event_dev), (void *)&nb_timers,\n \t\t\t RTE_EVENT_TYPE_TIMER);\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex 2be5d5f07..01b271507 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -7,6 +7,7 @@\n \n #include <rte_event_timer_adapter.h>\n #include <rte_event_timer_adapter_pmd.h>\n+#include <rte_reciprocal.h>\n \n #include \"otx2_dev.h\"\n \n@@ -70,6 +71,13 @@\n #define OTX2_TIM_MAX_CHUNK_SLOTS\t(0x1FFE)\n #define OTX2_TIM_MIN_TMO_TKS\t\t(256)\n \n+#define OTX2_TIM_SP 0x1\n+#define OTX2_TIM_MP 0x2\n+#define OTX2_TIM_BKT_AND 0x4\n+#define OTX2_TIM_BKT_MOD 0x8\n+#define OTX2_TIM_ENA_FB 0x10\n+#define OTX2_TIM_ENA_DFB 0x20\n+\n enum otx2_tim_clk_src {\n \tOTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,\n \tOTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,\n@@ -95,6 +103,11 @@ struct otx2_tim_bkt {\n \tuint64_t pad;\n } __rte_packed __rte_aligned(32);\n \n+struct otx2_tim_ent {\n+\tuint64_t w0;\n+\tuint64_t wqe;\n+} __rte_packed;\n+\n struct otx2_tim_evdev {\n \tstruct rte_pci_device *pci_dev;\n \tstruct rte_eventdev *event_dev;\n@@ -111,8 +124,10 @@ struct otx2_tim_evdev {\n \n struct otx2_tim_ring {\n \tuintptr_t base;\n+\tstruct rte_reciprocal_u64 fast_div;\n \tuint16_t nb_chunk_slots;\n \tuint32_t nb_bkts;\n+\tuint64_t ring_start_cyc;\n \tstruct otx2_tim_bkt *bkt;\n \tstruct rte_mempool *chunk_pool;\n \tuint64_t tck_int;\n@@ -142,6 +157,24 @@ tim_priv_get(void)\n \treturn mz->addr;\n }\n \n+#define TIM_ARM_FASTPATH_MODES\t\t\t\t\t\t \\\n+FP(mod_sp, 0, 0, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \\\n+FP(mod_mp, 0, 0, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \\\n+FP(mod_fb_sp, 0, 1, 0, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \\\n+FP(mod_fb_mp, 0, 1, 1, OTX2_TIM_BKT_MOD | OTX2_TIM_ENA_FB | OTX2_TIM_MP) \\\n+FP(and_sp, 1, 0, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB | OTX2_TIM_SP) \\\n+FP(and_mp, 1, 0, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_DFB | OTX2_TIM_MP) \\\n+FP(and_fb_sp, 1, 1, 0, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB | OTX2_TIM_SP) \\\n+FP(and_fb_mp, 1, 1, 1, OTX2_TIM_BKT_AND | OTX2_TIM_ENA_FB | OTX2_TIM_MP) \\\n+\n+#define FP(_name, _f3, _f2, _f1, flags)\t\t\t\t\t \\\n+uint16_t otx2_tim_arm_burst_ ## _name(\t\t\t\t\t \\\n+\t\t\tconst struct rte_event_timer_adapter *adptr,\t \\\n+\t\t\t\t struct rte_event_timer **tim,\t \\\n+\t\t\t\t const uint16_t nb_timers);\n+TIM_ARM_FASTPATH_MODES\n+#undef FP\n+\n int otx2_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,\n \t\t uint32_t *caps,\n \t\t const struct rte_event_timer_adapter_ops **ops);\ndiff --git a/drivers/event/octeontx2/otx2_tim_worker.c b/drivers/event/octeontx2/otx2_tim_worker.c\nindex 29ed1fd5a..409575ec4 100644\n--- a/drivers/event/octeontx2/otx2_tim_worker.c\n+++ b/drivers/event/octeontx2/otx2_tim_worker.c\n@@ -5,3 +5,80 @@\n #include \"otx2_tim_evdev.h\"\n #include \"otx2_tim_worker.h\"\n \n+static inline int\n+tim_arm_checks(const struct otx2_tim_ring * const tim_ring,\n+\t struct rte_event_timer * const tim)\n+{\n+\tif (unlikely(tim->state)) {\n+\t\ttim->state = RTE_EVENT_TIMER_ERROR;\n+\t\trte_errno = EALREADY;\n+\t\tgoto fail;\n+\t}\n+\n+\tif (unlikely(!tim->timeout_ticks ||\n+\t\t tim->timeout_ticks >= tim_ring->nb_bkts)) {\n+\t\ttim->state = tim->timeout_ticks ? RTE_EVENT_TIMER_ERROR_TOOLATE\n+\t\t\t: RTE_EVENT_TIMER_ERROR_TOOEARLY;\n+\t\trte_errno = EINVAL;\n+\t\tgoto fail;\n+\t}\n+\n+\treturn 0;\n+\n+fail:\n+\treturn -EINVAL;\n+}\n+\n+static inline void\n+tim_format_event(const struct rte_event_timer * const tim,\n+\t\t struct otx2_tim_ent * const entry)\n+{\n+\tentry->w0 = (tim->ev.event & 0xFFC000000000) >> 6 |\n+\t\t(tim->ev.event & 0xFFFFFFFFF);\n+\tentry->wqe = tim->ev.u64;\n+}\n+\n+static __rte_always_inline uint16_t\n+tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr,\n+\t\t struct rte_event_timer **tim,\n+\t\t const uint16_t nb_timers,\n+\t\t const uint8_t flags)\n+{\n+\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n+\tstruct otx2_tim_ent entry;\n+\tuint16_t index;\n+\tint ret;\n+\n+\tfor (index = 0; index < nb_timers; index++) {\n+\t\tif (tim_arm_checks(tim_ring, tim[index]))\n+\t\t\tbreak;\n+\n+\t\ttim_format_event(tim[index], &entry);\n+\t\tif (flags & OTX2_TIM_SP)\n+\t\t\tret = tim_add_entry_sp(tim_ring,\n+\t\t\t\t\t tim[index]->timeout_ticks,\n+\t\t\t\t\t tim[index], &entry, flags);\n+\t\tif (flags & OTX2_TIM_MP)\n+\t\t\tret = tim_add_entry_mp(tim_ring,\n+\t\t\t\t\t tim[index]->timeout_ticks,\n+\t\t\t\t\t tim[index], &entry, flags);\n+\n+\t\tif (unlikely(ret)) {\n+\t\t\trte_errno = -ret;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn index;\n+}\n+\n+#define FP(_name, _f3, _f2, _f1, _flags)\t\t\t\t \\\n+uint16_t __rte_noinline\t\t\t\t\t\t\t \\\n+otx2_tim_arm_burst_ ## _name(const struct rte_event_timer_adapter *adptr, \\\n+\t\t\t struct rte_event_timer **tim,\t\t \\\n+\t\t\t const uint16_t nb_timers)\t\t\t \\\n+{\t\t\t\t\t\t\t\t\t \\\n+\treturn tim_timer_arm_burst(adptr, tim, nb_timers, _flags);\t \\\n+}\n+TIM_ARM_FASTPATH_MODES\n+#undef FP\ndiff --git a/drivers/event/octeontx2/otx2_tim_worker.h b/drivers/event/octeontx2/otx2_tim_worker.h\nindex ccb137d13..a5e0d56bc 100644\n--- a/drivers/event/octeontx2/otx2_tim_worker.h\n+++ b/drivers/event/octeontx2/otx2_tim_worker.h\n@@ -108,4 +108,208 @@ tim_bkt_clr_nent(struct otx2_tim_bkt *bktp)\n \treturn __atomic_and_fetch(&bktp->w1, v, __ATOMIC_ACQ_REL);\n }\n \n+static __rte_always_inline struct otx2_tim_bkt *\n+tim_get_target_bucket(struct otx2_tim_ring * const tim_ring,\n+\t\t const uint32_t rel_bkt, const uint8_t flag)\n+{\n+\tconst uint64_t bkt_cyc = rte_rdtsc() - tim_ring->ring_start_cyc;\n+\tuint32_t bucket = rte_reciprocal_divide_u64(bkt_cyc,\n+\t\t\t&tim_ring->fast_div) + rel_bkt;\n+\n+\tif (flag & OTX2_TIM_BKT_MOD)\n+\t\tbucket = bucket % tim_ring->nb_bkts;\n+\tif (flag & OTX2_TIM_BKT_AND)\n+\t\tbucket = bucket & (tim_ring->nb_bkts - 1);\n+\n+\treturn &tim_ring->bkt[bucket];\n+}\n+\n+static struct otx2_tim_ent *\n+tim_clr_bkt(struct otx2_tim_ring * const tim_ring,\n+\t struct otx2_tim_bkt * const bkt)\n+{\n+\tstruct otx2_tim_ent *chunk;\n+\tstruct otx2_tim_ent *pnext;\n+\n+\tchunk = ((struct otx2_tim_ent *)(uintptr_t)bkt->first_chunk);\n+\tchunk = (struct otx2_tim_ent *)(uintptr_t)(chunk +\n+\t\t\ttim_ring->nb_chunk_slots)->w0;\n+\twhile (chunk) {\n+\t\tpnext = (struct otx2_tim_ent *)(uintptr_t)\n+\t\t\t((chunk + tim_ring->nb_chunk_slots)->w0);\n+\t\trte_mempool_put(tim_ring->chunk_pool, chunk);\n+\t\tchunk = pnext;\n+\t}\n+\n+\treturn (struct otx2_tim_ent *)(uintptr_t)bkt->first_chunk;\n+}\n+\n+static struct otx2_tim_ent *\n+tim_refill_chunk(struct otx2_tim_bkt * const bkt,\n+\t\t struct otx2_tim_ring * const tim_ring)\n+{\n+\tstruct otx2_tim_ent *chunk;\n+\n+\tif (bkt->nb_entry || !bkt->first_chunk) {\n+\t\tif (unlikely(rte_mempool_get(tim_ring->chunk_pool,\n+\t\t\t\t\t (void **)&chunk)))\n+\t\t\treturn NULL;\n+\t\tif (bkt->nb_entry) {\n+\t\t\t*(uint64_t *)(((struct otx2_tim_ent *)(uintptr_t)\n+\t\t\t\t\t\tbkt->current_chunk) +\n+\t\t\t\t\ttim_ring->nb_chunk_slots) =\n+\t\t\t\t(uintptr_t)chunk;\n+\t\t} else {\n+\t\t\tbkt->first_chunk = (uintptr_t)chunk;\n+\t\t}\n+\t} else {\n+\t\tchunk = tim_clr_bkt(tim_ring, bkt);\n+\t\tbkt->first_chunk = (uintptr_t)chunk;\n+\t}\n+\t*(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0;\n+\n+\treturn chunk;\n+}\n+\n+static struct otx2_tim_ent *\n+tim_insert_chunk(struct otx2_tim_bkt * const bkt,\n+\t\t struct otx2_tim_ring * const tim_ring)\n+{\n+\tstruct otx2_tim_ent *chunk;\n+\n+\tif (unlikely(rte_mempool_get(tim_ring->chunk_pool, (void **)&chunk)))\n+\t\treturn NULL;\n+\n+\t*(uint64_t *)(chunk + tim_ring->nb_chunk_slots) = 0;\n+\tif (bkt->nb_entry) {\n+\t\t*(uint64_t *)(((struct otx2_tim_ent *)(uintptr_t)\n+\t\t\t\t\tbkt->current_chunk) +\n+\t\t\t\ttim_ring->nb_chunk_slots) = (uintptr_t)chunk;\n+\t} else {\n+\t\tbkt->first_chunk = (uintptr_t)chunk;\n+\t}\n+\n+\treturn chunk;\n+}\n+\n+static __rte_always_inline int\n+tim_add_entry_sp(struct otx2_tim_ring * const tim_ring,\n+\t\t const uint32_t rel_bkt,\n+\t\t struct rte_event_timer * const tim,\n+\t\t const struct otx2_tim_ent * const pent,\n+\t\t const uint8_t flags)\n+{\n+\tstruct otx2_tim_ent *chunk;\n+\tstruct otx2_tim_bkt *bkt;\n+\tuint64_t lock_sema;\n+\tint16_t rem;\n+\n+\tbkt = tim_get_target_bucket(tim_ring, rel_bkt, flags);\n+\n+__retry:\n+\t/* Get Bucket sema*/\n+\tlock_sema = tim_bkt_fetch_sema(bkt);\n+\n+\t/* Bucket related checks. */\n+\tif (unlikely(tim_bkt_get_hbt(lock_sema)))\n+\t\tgoto __retry;\n+\n+\t/* Insert the work. */\n+\trem = tim_bkt_fetch_rem(lock_sema);\n+\n+\tif (!rem) {\n+\t\tif (flags & OTX2_TIM_ENA_FB)\n+\t\t\tchunk = tim_refill_chunk(bkt, tim_ring);\n+\t\tif (flags & OTX2_TIM_ENA_DFB)\n+\t\t\tchunk = tim_insert_chunk(bkt, tim_ring);\n+\n+\t\tif (unlikely(chunk == NULL)) {\n+\t\t\ttim_bkt_set_rem(bkt, 0);\n+\t\t\ttim->impl_opaque[0] = 0;\n+\t\t\ttim->impl_opaque[1] = 0;\n+\t\t\ttim->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tbkt->current_chunk = (uintptr_t)chunk;\n+\t\ttim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - 1);\n+\t} else {\n+\t\tchunk = (struct otx2_tim_ent *)(uintptr_t)bkt->current_chunk;\n+\t\tchunk += tim_ring->nb_chunk_slots - rem;\n+\t}\n+\n+\t/* Copy work entry. */\n+\t*chunk = *pent;\n+\n+\ttim_bkt_inc_nent(bkt);\n+\n+\ttim->impl_opaque[0] = (uintptr_t)chunk;\n+\ttim->impl_opaque[1] = (uintptr_t)bkt;\n+\ttim->state = RTE_EVENT_TIMER_ARMED;\n+\n+\treturn 0;\n+}\n+\n+static __rte_always_inline int\n+tim_add_entry_mp(struct otx2_tim_ring * const tim_ring,\n+\t\t const uint32_t rel_bkt,\n+\t\t struct rte_event_timer * const tim,\n+\t\t const struct otx2_tim_ent * const pent,\n+\t\t const uint8_t flags)\n+{\n+\tstruct otx2_tim_ent *chunk;\n+\tstruct otx2_tim_bkt *bkt;\n+\tuint64_t lock_sema;\n+\tint16_t rem;\n+\n+__retry:\n+\tbkt = tim_get_target_bucket(tim_ring, rel_bkt, flags);\n+\n+\t/* Get Bucket sema*/\n+\tlock_sema = tim_bkt_fetch_sema_lock(bkt);\n+\n+\t/* Bucket related checks. */\n+\tif (unlikely(tim_bkt_get_hbt(lock_sema))) {\n+\t\ttim_bkt_dec_lock(bkt);\n+\t\tgoto __retry;\n+\t}\n+\n+\trem = tim_bkt_fetch_rem(lock_sema);\n+\n+\tif (rem < 0) {\n+\t\t/* Goto diff bucket. */\n+\t\ttim_bkt_dec_lock(bkt);\n+\t\tgoto __retry;\n+\t} else if (!rem) {\n+\t\t/* Only one thread can be here*/\n+\t\tif (flags & OTX2_TIM_ENA_FB)\n+\t\t\tchunk = tim_refill_chunk(bkt, tim_ring);\n+\t\tif (flags & OTX2_TIM_ENA_DFB)\n+\t\t\tchunk = tim_insert_chunk(bkt, tim_ring);\n+\n+\t\tif (unlikely(chunk == NULL)) {\n+\t\t\ttim_bkt_set_rem(bkt, 0);\n+\t\t\ttim_bkt_dec_lock(bkt);\n+\t\t\ttim->impl_opaque[0] = 0;\n+\t\t\ttim->impl_opaque[1] = 0;\n+\t\t\ttim->state = RTE_EVENT_TIMER_ERROR;\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tbkt->current_chunk = (uintptr_t)chunk;\n+\t\ttim_bkt_set_rem(bkt, tim_ring->nb_chunk_slots - 1);\n+\t} else {\n+\t\tchunk = (struct otx2_tim_ent *)(uintptr_t)bkt->current_chunk;\n+\t\tchunk += tim_ring->nb_chunk_slots - rem;\n+\t}\n+\n+\t/* Copy work entry. */\n+\t*chunk = *pent;\n+\ttim_bkt_dec_lock(bkt);\n+\ttim_bkt_inc_nent(bkt);\n+\ttim->impl_opaque[0] = (uintptr_t)chunk;\n+\ttim->impl_opaque[1] = (uintptr_t)bkt;\n+\ttim->state = RTE_EVENT_TIMER_ARMED;\n+\n+\treturn 0;\n+}\n+\n #endif /* __OTX2_TIM_WORKER_H__ */\n", "prefixes": [ "v3", "36/42" ] }