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GET /api/patches/55633/?format=api
{ "id": 55633, "url": "https://patches.dpdk.org/api/patches/55633/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190628182354.228-29-pbhagavatula@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190628182354.228-29-pbhagavatula@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-29-pbhagavatula@marvell.com", "date": "2019-06-28T18:23:39", "name": "[v3,28/42] event/octeontx2: create and free timer adapter", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6b5406ababae58275b0525deec91ec1b14278837", "submitter": { "id": 1183, "url": "https://patches.dpdk.org/api/people/1183/?format=api", "name": "Pavan Nikhilesh Bhagavatula", "email": "pbhagavatula@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190628182354.228-29-pbhagavatula@marvell.com/mbox/", "series": [ { "id": 5227, "url": "https://patches.dpdk.org/api/series/5227/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5227", "date": "2019-06-28T18:23:11", "name": "OCTEONTX2 event device driver", "version": 3, "mbox": "https://patches.dpdk.org/series/5227/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/55633/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/55633/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 573D41BB0B;\n\tFri, 28 Jun 2019 20:25:31 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id F18481B9F0\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:25:05 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SILsKR011627 for <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:05 -0700", "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agpb-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 11:25:05 -0700", "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:25:03 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:25:03 -0700", "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id B05823F7053;\n\tFri, 28 Jun 2019 11:25:02 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=AmhWeoXuLyW9K92jth8g8FG3BnEXL4ulZG3NpHQckf8=;\n\tb=DPDBmJ8DNBITHX01jeWruv0AMR9KFZwFuMkxU7tAHf7BSPjFoC8wHGFSjiUsaLc/k2Cr\n\tP0BB8sjqvkh2C5RFM3DEhH5aSQzJu6Itpzsghkq/wv1/BPKA3zrwFS0ltHbVSUaEqLge\n\tCoiIn71rLVTf/UtcUZ2JQptoi6MtGijI82Hghbu/6leAL2Bu2aLlDIeGRhGkjk5lpVA5\n\tNGf3hQrnfN/2GSa0ZjdUD4Y/Ou9cO/CseriPliRqmk7LVX1wAZyP06UPJI8oLmcTWcpL\n\tf/bmlGgEZQraDH3Q7LM4tOAlrU7FldokVkHlDbw/vlQXUIIaVVES+y+gp9oQKY8lmNex\n\tqQ== ", "From": "<pbhagavatula@marvell.com>", "To": "<jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>", "CC": "<dev@dpdk.org>", "Date": "Fri, 28 Jun 2019 23:53:39 +0530", "Message-ID": "<20190628182354.228-29-pbhagavatula@marvell.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>", "References": "<20190628182354.228-1-pbhagavatula@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0", "Subject": "[dpdk-dev] [PATCH v3 28/42] event/octeontx2: create and free timer\n\tadapter", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nWhen the application calls timer adapter create the following is used:\n- Allocate a TIM lf based on number of lf's provisioned.\n- Verify the config parameters supplied.\n- Allocate memory required for\n\t* Buckets based on min and max timeout supplied.\n\t* Allocate the chunk pool based on the number of timers.\n\nOn Free:\n- Free the allocated bucket and chunk memory.\n- Free the TIM lf allocated.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\n---\n drivers/event/octeontx2/otx2_tim_evdev.c | 259 ++++++++++++++++++++++-\n drivers/event/octeontx2/otx2_tim_evdev.h | 55 +++++\n 2 files changed, 313 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c\nindex 0f20c163b..e24f7ce9e 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.c\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.c\n@@ -2,9 +2,263 @@\n * Copyright(C) 2019 Marvell International Ltd.\n */\n \n+#include <rte_malloc.h>\n+#include <rte_mbuf_pool_ops.h>\n+\n #include \"otx2_evdev.h\"\n #include \"otx2_tim_evdev.h\"\n \n+static struct rte_event_timer_adapter_ops otx2_tim_ops;\n+\n+static int\n+tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,\n+\t\t struct rte_event_timer_adapter_conf *rcfg)\n+{\n+\tunsigned int cache_sz = (tim_ring->nb_chunks / 1.5);\n+\tunsigned int mp_flags = 0;\n+\tchar pool_name[25];\n+\tint rc;\n+\n+\t/* Create chunk pool. */\n+\tif (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {\n+\t\tmp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;\n+\t\totx2_tim_dbg(\"Using single producer mode\");\n+\t\ttim_ring->prod_type_sp = true;\n+\t}\n+\n+\tsnprintf(pool_name, sizeof(pool_name), \"otx2_tim_chunk_pool%d\",\n+\t\t tim_ring->ring_id);\n+\n+\tif (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)\n+\t\tcache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;\n+\n+\t/* NPA need not have cache as free is not visible to SW */\n+\ttim_ring->chunk_pool = rte_mempool_create_empty(pool_name,\n+\t\t\t\t\t\t\ttim_ring->nb_chunks,\n+\t\t\t\t\t\t\ttim_ring->chunk_sz,\n+\t\t\t\t\t\t\t0, 0, rte_socket_id(),\n+\t\t\t\t\t\t\tmp_flags);\n+\n+\tif (tim_ring->chunk_pool == NULL) {\n+\t\totx2_err(\"Unable to create chunkpool.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\trc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,\n+\t\t\t\t\trte_mbuf_platform_mempool_ops(), NULL);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Unable to set chunkpool ops\");\n+\t\tgoto free;\n+\t}\n+\n+\trc = rte_mempool_populate_default(tim_ring->chunk_pool);\n+\tif (rc < 0) {\n+\t\totx2_err(\"Unable to set populate chunkpool.\");\n+\t\tgoto free;\n+\t}\n+\ttim_ring->aura = npa_lf_aura_handle_to_aura(\n+\t\t\t\t\t\ttim_ring->chunk_pool->pool_id);\n+\ttim_ring->ena_dfb = 0;\n+\n+\treturn 0;\n+\n+free:\n+\trte_mempool_free(tim_ring->chunk_pool);\n+\treturn rc;\n+}\n+\n+static void\n+tim_err_desc(int rc)\n+{\n+\tswitch (rc) {\n+\tcase TIM_AF_NO_RINGS_LEFT:\n+\t\totx2_err(\"Unable to allocat new TIM ring.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_NPA_PF_FUNC:\n+\t\totx2_err(\"Invalid NPA pf func.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_SSO_PF_FUNC:\n+\t\totx2_err(\"Invalid SSO pf func.\");\n+\t\tbreak;\n+\tcase TIM_AF_RING_STILL_RUNNING:\n+\t\totx2_tim_dbg(\"Ring busy.\");\n+\t\tbreak;\n+\tcase TIM_AF_LF_INVALID:\n+\t\totx2_err(\"Invalid Ring id.\");\n+\t\tbreak;\n+\tcase TIM_AF_CSIZE_NOT_ALIGNED:\n+\t\totx2_err(\"Chunk size specified needs to be multiple of 16.\");\n+\t\tbreak;\n+\tcase TIM_AF_CSIZE_TOO_SMALL:\n+\t\totx2_err(\"Chunk size too small.\");\n+\t\tbreak;\n+\tcase TIM_AF_CSIZE_TOO_BIG:\n+\t\totx2_err(\"Chunk size too big.\");\n+\t\tbreak;\n+\tcase TIM_AF_INTERVAL_TOO_SMALL:\n+\t\totx2_err(\"Bucket traversal interval too small.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_BIG_ENDIAN_VALUE:\n+\t\totx2_err(\"Invalid Big endian value.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_CLOCK_SOURCE:\n+\t\totx2_err(\"Invalid Clock source specified.\");\n+\t\tbreak;\n+\tcase TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:\n+\t\totx2_err(\"GPIO clock source not enabled.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_BSIZE:\n+\t\totx2_err(\"Invalid bucket size.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_ENABLE_PERIODIC:\n+\t\totx2_err(\"Invalid bucket size.\");\n+\t\tbreak;\n+\tcase TIM_AF_INVALID_ENABLE_DONTFREE:\n+\t\totx2_err(\"Invalid Don't free value.\");\n+\t\tbreak;\n+\tcase TIM_AF_ENA_DONTFRE_NSET_PERIODIC:\n+\t\totx2_err(\"Don't free bit not set when periodic is enabled.\");\n+\t\tbreak;\n+\tcase TIM_AF_RING_ALREADY_DISABLED:\n+\t\totx2_err(\"Ring already stopped\");\n+\t\tbreak;\n+\tdefault:\n+\t\totx2_err(\"Unknown Error.\");\n+\t}\n+}\n+\n+static int\n+otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)\n+{\n+\tstruct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;\n+\tstruct otx2_tim_evdev *dev = tim_priv_get();\n+\tstruct otx2_tim_ring *tim_ring;\n+\tstruct tim_config_req *cfg_req;\n+\tstruct tim_ring_req *free_req;\n+\tstruct tim_lf_alloc_req *req;\n+\tstruct tim_lf_alloc_rsp *rsp;\n+\tuint64_t nb_timers;\n+\tint rc;\n+\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\tif (adptr->data->id >= dev->nb_rings)\n+\t\treturn -ENODEV;\n+\n+\treq = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);\n+\treq->npa_pf_func = otx2_npa_pf_func_get();\n+\treq->sso_pf_func = otx2_sso_pf_func_get();\n+\treq->ring = adptr->data->id;\n+\n+\trc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tif (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),\n+\t\t rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {\n+\t\trc = -ERANGE;\n+\t\tgoto rng_mem_err;\n+\t}\n+\n+\ttim_ring = rte_zmalloc(\"otx2_tim_prv\", sizeof(struct otx2_tim_ring), 0);\n+\tif (tim_ring == NULL) {\n+\t\trc = -ENOMEM;\n+\t\tgoto rng_mem_err;\n+\t}\n+\n+\tadptr->data->adapter_priv = tim_ring;\n+\n+\ttim_ring->tenns_clk_freq = rsp->tenns_clk;\n+\ttim_ring->clk_src = (int)rcfg->clk_src;\n+\ttim_ring->ring_id = adptr->data->id;\n+\ttim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);\n+\ttim_ring->max_tout = rcfg->max_tmo_ns;\n+\ttim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);\n+\ttim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;\n+\tnb_timers = rcfg->nb_timers;\n+\ttim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(\n+\t\t\t\t\t\t\ttim_ring->chunk_sz);\n+\ttim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);\n+\n+\t/* Create buckets. */\n+\ttim_ring->bkt = rte_zmalloc(\"otx2_tim_bucket\", (tim_ring->nb_bkts) *\n+\t\t\t\t sizeof(struct otx2_tim_bkt),\n+\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tif (tim_ring->bkt == NULL)\n+\t\tgoto bkt_mem_err;\n+\n+\trc = tim_chnk_pool_create(tim_ring, rcfg);\n+\tif (rc < 0)\n+\t\tgoto chnk_mem_err;\n+\n+\tcfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);\n+\n+\tcfg_req->ring = tim_ring->ring_id;\n+\tcfg_req->bigendian = false;\n+\tcfg_req->clocksource = tim_ring->clk_src;\n+\tcfg_req->enableperiodic = false;\n+\tcfg_req->enabledontfreebuffer = tim_ring->ena_dfb;\n+\tcfg_req->bucketsize = tim_ring->nb_bkts;\n+\tcfg_req->chunksize = tim_ring->chunk_sz;\n+\tcfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,\n+\t\t\t\t tim_ring->tenns_clk_freq);\n+\n+\trc = otx2_mbox_process(dev->mbox);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\tgoto chnk_mem_err;\n+\t}\n+\n+\ttim_ring->base = dev->bar2 +\n+\t\t(RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);\n+\n+\totx2_write64((uint64_t)tim_ring->bkt,\n+\t\t tim_ring->base + TIM_LF_RING_BASE);\n+\totx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);\n+\n+\treturn rc;\n+\n+chnk_mem_err:\n+\trte_free(tim_ring->bkt);\n+bkt_mem_err:\n+\trte_free(tim_ring);\n+rng_mem_err:\n+\tfree_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);\n+\tfree_req->ring = adptr->data->id;\n+\totx2_mbox_process(dev->mbox);\n+\treturn rc;\n+}\n+\n+static int\n+otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)\n+{\n+\tstruct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;\n+\tstruct otx2_tim_evdev *dev = tim_priv_get();\n+\tstruct tim_ring_req *req;\n+\tint rc;\n+\n+\tif (dev == NULL)\n+\t\treturn -ENODEV;\n+\n+\treq = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);\n+\treq->ring = tim_ring->ring_id;\n+\n+\trc = otx2_mbox_process(dev->mbox);\n+\tif (rc < 0) {\n+\t\ttim_err_desc(rc);\n+\t\treturn -EBUSY;\n+\t}\n+\n+\trte_free(tim_ring->bkt);\n+\trte_mempool_free(tim_ring->chunk_pool);\n+\trte_free(adptr->data->adapter_priv);\n+\n+\treturn 0;\n+}\n+\n int\n otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \t\t uint32_t *caps,\n@@ -13,13 +267,16 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,\n \tstruct otx2_tim_evdev *dev = tim_priv_get();\n \n \tRTE_SET_USED(flags);\n-\tRTE_SET_USED(ops);\n \tif (dev == NULL)\n \t\treturn -ENODEV;\n \n+\totx2_tim_ops.init = otx2_tim_ring_create;\n+\totx2_tim_ops.uninit = otx2_tim_ring_free;\n+\n \t/* Store evdev pointer for later use. */\n \tdev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;\n \t*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;\n+\t*ops = &otx2_tim_ops;\n \n \treturn 0;\n }\ndiff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h\nindex e94c61b1a..aaa4d93f5 100644\n--- a/drivers/event/octeontx2/otx2_tim_evdev.h\n+++ b/drivers/event/octeontx2/otx2_tim_evdev.h\n@@ -6,11 +6,47 @@\n #define __OTX2_TIM_EVDEV_H__\n \n #include <rte_event_timer_adapter.h>\n+#include <rte_event_timer_adapter_pmd.h>\n \n #include \"otx2_dev.h\"\n \n #define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev\n \n+#define otx2_tim_func_trace otx2_tim_dbg\n+\n+#define TIM_LF_RING_AURA\t\t(0x0)\n+#define TIM_LF_RING_BASE\t\t(0x130)\n+\n+#define OTX2_TIM_RING_DEF_CHUNK_SZ\t(4096)\n+#define OTX2_TIM_CHUNK_ALIGNMENT\t(16)\n+#define OTX2_TIM_NB_CHUNK_SLOTS(sz)\t(((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)\n+#define OTX2_TIM_MIN_TMO_TKS\t\t(256)\n+\n+enum otx2_tim_clk_src {\n+\tOTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,\n+\tOTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,\n+\tOTX2_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,\n+\tOTX2_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,\n+};\n+\n+struct otx2_tim_bkt {\n+\tuint64_t first_chunk;\n+\tunion {\n+\t\tuint64_t w1;\n+\t\tstruct {\n+\t\t\tuint32_t nb_entry;\n+\t\t\tuint8_t sbt:1;\n+\t\t\tuint8_t hbt:1;\n+\t\t\tuint8_t bsk:1;\n+\t\t\tuint8_t rsvd:5;\n+\t\t\tuint8_t lock;\n+\t\t\tint16_t chunk_remainder;\n+\t\t};\n+\t};\n+\tuint64_t current_chunk;\n+\tuint64_t pad;\n+} __rte_packed __rte_aligned(32);\n+\n struct otx2_tim_evdev {\n \tstruct rte_pci_device *pci_dev;\n \tstruct rte_eventdev *event_dev;\n@@ -19,6 +55,25 @@ struct otx2_tim_evdev {\n \tuintptr_t bar2;\n };\n \n+struct otx2_tim_ring {\n+\tuintptr_t base;\n+\tuint16_t nb_chunk_slots;\n+\tuint32_t nb_bkts;\n+\tstruct otx2_tim_bkt *bkt;\n+\tstruct rte_mempool *chunk_pool;\n+\tuint64_t tck_int;\n+\tuint8_t prod_type_sp;\n+\tuint8_t ena_dfb;\n+\tuint16_t ring_id;\n+\tuint32_t aura;\n+\tuint64_t tck_nsec;\n+\tuint64_t max_tout;\n+\tuint64_t nb_chunks;\n+\tuint64_t chunk_sz;\n+\tuint64_t tenns_clk_freq;\n+\tenum otx2_tim_clk_src clk_src;\n+} __rte_cache_aligned;\n+\n static inline struct otx2_tim_evdev *\n tim_priv_get(void)\n {\n", "prefixes": [ "v3", "28/42" ] }