get:
Show a patch.

patch:
Update a patch.

put:
Update a patch.

GET /api/patches/55606/
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55606,
    "url": "https://patches.dpdk.org/api/patches/55606/",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190628182354.228-2-pbhagavatula@marvell.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190628182354.228-2-pbhagavatula@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190628182354.228-2-pbhagavatula@marvell.com",
    "date": "2019-06-28T18:23:12",
    "name": "[v3,01/42] event/octeontx2: add build infra and device probe",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "7681d011aff3aafdee3f7b0cb318f58b1b2635fe",
    "submitter": {
        "id": 1183,
        "url": "https://patches.dpdk.org/api/people/1183/",
        "name": "Pavan Nikhilesh Bhagavatula",
        "email": "pbhagavatula@marvell.com"
    },
    "delegate": {
        "id": 310,
        "url": "https://patches.dpdk.org/api/users/310/",
        "username": "jerin",
        "first_name": "Jerin",
        "last_name": "Jacob",
        "email": "jerin.jacob@caviumnetworks.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190628182354.228-2-pbhagavatula@marvell.com/mbox/",
    "series": [
        {
            "id": 5227,
            "url": "https://patches.dpdk.org/api/series/5227/",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5227",
            "date": "2019-06-28T18:23:11",
            "name": "OCTEONTX2 event device driver",
            "version": 3,
            "mbox": "https://patches.dpdk.org/series/5227/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/55606/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/55606/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Subject": "[dpdk-dev] [PATCH v3 01/42] event/octeontx2: add build infra and\n\tdevice probe",
        "List-Post": "<mailto:dev@dpdk.org>",
        "X-Mailer": "git-send-email 2.17.1",
        "X-Original-To": "patchwork@dpdk.org",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-28_08:, , signatures=0",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "From": "<pbhagavatula@marvell.com>",
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-BeenThere": "dev@dpdk.org",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "CC": "<dev@dpdk.org>",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=SLTxBUBKs1lklErGj8+5jm4GybOgX3rp1CSD6lfaRMg=;\n\tb=kc3k/Dwmy84UuFovENnVTPhSr6PpzytG1tEjUF5TZjGVRdJOldmIjEQiHFr2BmDh1UHP\n\t0PKPF03Rosm8tzLyaxV3r5jz6SpzSf8KK8RWLSj3de0UUJ67c39UqsHfxKnFYOTlKxDP\n\tT+PtKpdsmRCRA+eUL5QyI6FJ3K/kCzMQZPvm8XgITKje4mjNYyBAnXoMVRddLaOpcLeM\n\tmRCuGvcRsVFDEt8MHjAAsEqsA7eiDFzpp8GXEwRrKLKPq60UMN5K3HSJEgzpH5I1GqXq\n\tqHgcsTXIMwGG4uVsbcRmauofXLyj0AsEjM/z9CdXZoYBeSdRn5+lvzN4Pjd2bNgOT2R9\n\t8g== ",
        "Date": "Fri, 28 Jun 2019 23:53:12 +0530",
        "In-Reply-To": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "X-Mailman-Version": "2.1.15",
        "Errors-To": "dev-bounces@dpdk.org",
        "References": "<20190628182354.228-1-pbhagavatula@marvell.com>",
        "Delivered-To": "patchwork@dpdk.org",
        "Precedence": "list",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 3701E4CC0;\n\tFri, 28 Jun 2019 20:24:03 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 23F6C4C8B\n\tfor <dev@dpdk.org>; Fri, 28 Jun 2019 20:24:01 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5SIKhtg010886; Fri, 28 Jun 2019 11:24:01 -0700",
            "from sc-exch01.marvell.com ([199.233.58.181])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2tdd77agh0-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tFri, 28 Jun 2019 11:24:01 -0700",
            "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tFri, 28 Jun 2019 11:23:59 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Fri, 28 Jun 2019 11:23:59 -0700",
            "from BG-LT7430.marvell.com (unknown [10.28.17.12])\n\tby maili.marvell.com (Postfix) with ESMTP id 2E3583F7040;\n\tFri, 28 Jun 2019 11:23:56 -0700 (PDT)"
        ],
        "MIME-Version": "1.0",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "To": "<jerinj@marvell.com>, Thomas Monjalon <thomas@monjalon.net>,\n\tJohn McNamara\n\t<john.mcnamara@intel.com>, Marko Kovacevic <marko.kovacevic@intel.com>,\n\t\"Pavan Nikhilesh\" <pbhagavatula@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>,\n\t\"Anatoly Burakov\" <anatoly.burakov@intel.com>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>",
        "Message-ID": "<20190628182354.228-2-pbhagavatula@marvell.com>",
        "Content-Type": "text/plain",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "Content-Transfer-Encoding": "8bit"
    },
    "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nAdd the make and meson based build infrastructure along with the\neventdev(SSO) device probe.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n MAINTAINERS                                   |  6 ++\n config/common_base                            |  5 ++\n doc/guides/eventdevs/index.rst                |  1 +\n doc/guides/eventdevs/octeontx2.rst            | 60 ++++++++++++++++\n doc/guides/platform/octeontx2.rst             |  3 +\n drivers/event/Makefile                        |  1 +\n drivers/event/meson.build                     |  2 +-\n drivers/event/octeontx2/Makefile              | 39 +++++++++++\n drivers/event/octeontx2/meson.build           | 21 ++++++\n drivers/event/octeontx2/otx2_evdev.c          | 70 +++++++++++++++++++\n drivers/event/octeontx2/otx2_evdev.h          | 26 +++++++\n .../rte_pmd_octeontx2_event_version.map       |  4 ++\n mk/rte.app.mk                                 |  2 +\n 13 files changed, 239 insertions(+), 1 deletion(-)\n create mode 100644 doc/guides/eventdevs/octeontx2.rst\n create mode 100644 drivers/event/octeontx2/Makefile\n create mode 100644 drivers/event/octeontx2/meson.build\n create mode 100644 drivers/event/octeontx2/otx2_evdev.c\n create mode 100644 drivers/event/octeontx2/otx2_evdev.h\n create mode 100644 drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map",
    "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex bbec1982c..39f12a1f2 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1034,6 +1034,12 @@ Cavium OCTEON TX timvf\n M: Pavan Nikhilesh <pbhagavatula@marvell.com>\n F: drivers/event/octeontx/timvf_*\n \n+Marvell OCTEON TX2\n+M: Pavan Nikhilesh <pbhagavatula@marvell.com>\n+M: Jerin Jacob <jerinj@marvell.com>\n+F: drivers/event/octeontx2/\n+F: doc/guides/eventdevs/octeontx2.rst\n+\n NXP DPAA eventdev\n M: Hemant Agrawal <hemant.agrawal@nxp.com>\n M: Sunil Kumar Kori <sunil.kori@nxp.com>\ndiff --git a/config/common_base b/config/common_base\nindex fa1ae249a..b3bcb4c4f 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -709,6 +709,11 @@ CONFIG_RTE_LIBRTE_PMD_DSW_EVENTDEV=y\n #\n CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF=y\n \n+#\n+# Compile PMD for octeontx2 sso event device\n+#\n+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV=y\n+\n #\n # Compile PMD for OPDL event device\n #\ndiff --git a/doc/guides/eventdevs/index.rst b/doc/guides/eventdevs/index.rst\nindex f7382dc8a..570905b81 100644\n--- a/doc/guides/eventdevs/index.rst\n+++ b/doc/guides/eventdevs/index.rst\n@@ -16,4 +16,5 @@ application trough the eventdev API.\n     dsw\n     sw\n     octeontx\n+    octeontx2\n     opdl\ndiff --git a/doc/guides/eventdevs/octeontx2.rst b/doc/guides/eventdevs/octeontx2.rst\nnew file mode 100644\nindex 000000000..341c5b21d\n--- /dev/null\n+++ b/doc/guides/eventdevs/octeontx2.rst\n@@ -0,0 +1,60 @@\n+..  SPDX-License-Identifier: BSD-3-Clause\n+    Copyright(c) 2019 Marvell International Ltd.\n+\n+OCTEON TX2 SSO Eventdev Driver\n+===============================\n+\n+The OCTEON TX2 SSO PMD (**librte_pmd_octeontx2_event**) provides poll mode\n+eventdev driver support for the inbuilt event device found in the **Marvell OCTEON TX2**\n+SoC family.\n+\n+More information about OCTEON TX2 SoC can be found at `Marvell Official Website\n+<https://www.marvell.com/embedded-processors/infrastructure-processors/>`_.\n+\n+Features\n+--------\n+\n+Features of the OCTEON TX2 SSO PMD are:\n+\n+- 256 Event queues\n+- 26 (dual) and 52 (single) Event ports\n+- HW event scheduler\n+- Supports 1M flows per event queue\n+- Flow based event pipelining\n+- Flow pinning support in flow based event pipelining\n+- Queue based event pipelining\n+- Supports ATOMIC, ORDERED, PARALLEL schedule types per flow\n+- Event scheduling QoS based on event queue priority\n+- Open system with configurable amount of outstanding events limited only by\n+  DRAM\n+- HW accelerated dequeue timeout support to enable power management\n+\n+Prerequisites and Compilation procedure\n+---------------------------------------\n+\n+   See :doc:`../platform/octeontx2` for setup information.\n+\n+Pre-Installation Configuration\n+------------------------------\n+\n+Compile time Config Options\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The following option can be modified in the ``config`` file.\n+\n+- ``CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV`` (default ``y``)\n+\n+  Toggle compilation of the ``librte_pmd_octeontx2_event`` driver.\n+\n+Debugging Options\n+~~~~~~~~~~~~~~~~~\n+\n+.. _table_octeontx2_event_debug_options:\n+\n+.. table:: OCTEON TX2 event device debug options\n+\n+   +---+------------+-------------------------------------------------------+\n+   | # | Component  | EAL log command                                       |\n+   +===+============+=======================================================+\n+   | 1 | SSO        | --log-level='pmd\\.event\\.octeontx2,8'                 |\n+   +---+------------+-------------------------------------------------------+\ndiff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst\nindex c9ea45647..fbf1193e7 100644\n--- a/doc/guides/platform/octeontx2.rst\n+++ b/doc/guides/platform/octeontx2.rst\n@@ -101,6 +101,9 @@ This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.\n #. **Mempool Driver**\n    See :doc:`../mempool/octeontx2` for NPA mempool driver information.\n \n+#. **Event Device Driver**\n+   See :doc:`../eventdevs/octeontx2` for SSO event device driver information.\n+\n Procedure to Setup Platform\n ---------------------------\n \ndiff --git a/drivers/event/Makefile b/drivers/event/Makefile\nindex 03ad1b6cb..86be41b9e 100644\n--- a/drivers/event/Makefile\n+++ b/drivers/event/Makefile\n@@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV) += skeleton\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV) += sw\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_DSW_EVENTDEV) += dsw\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF) += octeontx\n+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += octeontx2\n ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y)\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_EVENTDEV) += dpaa\n endif\ndiff --git a/drivers/event/meson.build b/drivers/event/meson.build\nindex fb723f727..50d30c53f 100644\n--- a/drivers/event/meson.build\n+++ b/drivers/event/meson.build\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: BSD-3-Clause\n # Copyright(c) 2017 Intel Corporation\n \n-drivers = ['dpaa', 'dpaa2', 'opdl', 'skeleton', 'sw', 'dsw']\n+drivers = ['dpaa', 'dpaa2', 'octeontx2', 'opdl', 'skeleton', 'sw', 'dsw']\n if not (toolchain == 'gcc' and cc.version().version_compare('<4.8.6') and\n \tdpdk_conf.has('RTE_ARCH_ARM64'))\n \tdrivers += 'octeontx'\ndiff --git a/drivers/event/octeontx2/Makefile b/drivers/event/octeontx2/Makefile\nnew file mode 100644\nindex 000000000..dbf6ec22d\n--- /dev/null\n+++ b/drivers/event/octeontx2/Makefile\n@@ -0,0 +1,39 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+#\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_pmd_octeontx2_event.a\n+\n+CFLAGS += $(WERROR_FLAGS)\n+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/mempool/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/event/octeontx2\n+CFLAGS += -I$(RTE_SDK)/drivers/net/octeontx2\n+CFLAGS += -O3\n+CFLAGS += -DALLOW_EXPERIMENTAL_API\n+\n+ifneq ($(CONFIG_RTE_ARCH_64),y)\n+CFLAGS += -Wno-int-to-pointer-cast\n+CFLAGS += -Wno-pointer-to-int-cast\n+endif\n+\n+EXPORT_MAP := rte_pmd_octeontx2_event_version.map\n+\n+LIBABIVER := 1\n+\n+#\n+# all source are stored in SRCS-y\n+#\n+\n+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += otx2_evdev.c\n+\n+LDLIBS += -lrte_eal -lrte_bus_pci -lrte_pci\n+LDLIBS += -lrte_eventdev\n+LDLIBS += -lrte_common_octeontx2\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/event/octeontx2/meson.build b/drivers/event/octeontx2/meson.build\nnew file mode 100644\nindex 000000000..c4f442174\n--- /dev/null\n+++ b/drivers/event/octeontx2/meson.build\n@@ -0,0 +1,21 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(C) 2019 Marvell International Ltd.\n+#\n+\n+sources = files('otx2_evdev.c')\n+\n+allow_experimental_apis = true\n+\n+extra_flags = []\n+# This integrated controller runs only on a arm64 machine, remove 32bit warnings\n+if not dpdk_conf.get('RTE_ARCH_64')\n+\textra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']\n+endif\n+\n+foreach flag: extra_flags\n+\tif cc.has_argument(flag)\n+\t\tcflags += flag\n+\tendif\n+endforeach\n+\n+deps += ['bus_pci', 'common_octeontx2']\ndiff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c\nnew file mode 100644\nindex 000000000..faffd3f0c\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev.c\n@@ -0,0 +1,70 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#include <inttypes.h>\n+\n+#include <rte_bus_pci.h>\n+#include <rte_common.h>\n+#include <rte_eal.h>\n+#include <rte_eventdev_pmd_pci.h>\n+#include <rte_pci.h>\n+\n+#include \"otx2_evdev.h\"\n+\n+static int\n+otx2_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_event_pmd_pci_probe(pci_drv, pci_dev,\n+\t\t\t\t       sizeof(struct otx2_sso_evdev),\n+\t\t\t\t       otx2_sso_init);\n+}\n+\n+static int\n+otx2_sso_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_event_pmd_pci_remove(pci_dev, otx2_sso_fini);\n+}\n+\n+static const struct rte_pci_id pci_sso_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,\n+\t\t\t       PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF)\n+\t},\n+\t{\n+\t\t.vendor_id = 0,\n+\t},\n+};\n+\n+static struct rte_pci_driver pci_sso = {\n+\t.id_table = pci_sso_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,\n+\t.probe = otx2_sso_probe,\n+\t.remove = otx2_sso_remove,\n+};\n+\n+int\n+otx2_sso_init(struct rte_eventdev *event_dev)\n+{\n+\tRTE_SET_USED(event_dev);\n+\t/* For secondary processes, the primary has done all the work */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_sso_fini(struct rte_eventdev *event_dev)\n+{\n+\tRTE_SET_USED(event_dev);\n+\t/* For secondary processes, nothing to be done */\n+\tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n+\t\treturn 0;\n+\n+\treturn 0;\n+}\n+\n+RTE_PMD_REGISTER_PCI(event_octeontx2, pci_sso);\n+RTE_PMD_REGISTER_PCI_TABLE(event_octeontx2, pci_sso_map);\n+RTE_PMD_REGISTER_KMOD_DEP(event_octeontx2, \"vfio-pci\");\ndiff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h\nnew file mode 100644\nindex 000000000..1df233293\n--- /dev/null\n+++ b/drivers/event/octeontx2/otx2_evdev.h\n@@ -0,0 +1,26 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2019 Marvell International Ltd.\n+ */\n+\n+#ifndef __OTX2_EVDEV_H__\n+#define __OTX2_EVDEV_H__\n+\n+#include <rte_eventdev.h>\n+\n+#include \"otx2_common.h\"\n+\n+#define EVENTDEV_NAME_OCTEONTX2_PMD otx2_eventdev\n+\n+#define sso_func_trace otx2_sso_dbg\n+\n+#define OTX2_SSO_MAX_VHGRP                  RTE_EVENT_MAX_QUEUES_PER_DEV\n+#define OTX2_SSO_MAX_VHWS                   (UINT8_MAX)\n+\n+struct otx2_sso_evdev {\n+};\n+\n+/* Init and Fini API's */\n+int otx2_sso_init(struct rte_eventdev *event_dev);\n+int otx2_sso_fini(struct rte_eventdev *event_dev);\n+\n+#endif /* __OTX2_EVDEV_H__ */\ndiff --git a/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map b/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map\nnew file mode 100644\nindex 000000000..41c65c8c9\n--- /dev/null\n+++ b/drivers/event/octeontx2/rte_pmd_octeontx2_event_version.map\n@@ -0,0 +1,4 @@\n+DPDK_19.08 {\n+\tlocal: *;\n+};\n+\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 81be289a8..503cecca2 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -109,6 +109,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO\n _LDLIBS-y += -lrte_common_octeontx\n endif\n OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)\n+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)\n ifeq ($(findstring y,$(OCTEONTX2-y)),y)\n _LDLIBS-y += -lrte_common_octeontx2\n endif\n@@ -292,6 +293,7 @@ endif # CONFIG_RTE_LIBRTE_FSLMC_BUS\n \n _LDLIBS-$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL) += -lrte_mempool_octeontx\n _LDLIBS-$(CONFIG_RTE_LIBRTE_OCTEONTX_PMD) += -lrte_pmd_octeontx\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV) += -lrte_pmd_octeontx2_event\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OPDL_EVENTDEV) += -lrte_pmd_opdl_event\n endif # CONFIG_RTE_LIBRTE_EVENTDEV\n \n",
    "prefixes": [
        "v3",
        "01/42"
    ]
}