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GET /api/patches/553/?format=api
{ "id": 553, "url": "https://patches.dpdk.org/api/patches/553/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411711418-12881-17-git-send-email-jingjing.wu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411711418-12881-17-git-send-email-jingjing.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411711418-12881-17-git-send-email-jingjing.wu@intel.com", "date": "2014-09-26T06:03:34", "name": "[dpdk-dev,v316/20] i40e: implement operations to configure flexible payload", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cf38447752e16a9b8a1f94b3a4190c3eb90de412", "submitter": { "id": 47, "url": "https://patches.dpdk.org/api/people/47/?format=api", "name": "Jingjing Wu", "email": "jingjing.wu@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411711418-12881-17-git-send-email-jingjing.wu@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/553/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/553/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 60D9B7DFC;\n\tFri, 26 Sep 2014 07:58:04 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id DD46F7DEB\n\tfor <dev@dpdk.org>; Fri, 26 Sep 2014 07:58:01 +0200 (CEST)", "from azsmga001.ch.intel.com ([10.2.17.19])\n\tby orsmga102.jf.intel.com with ESMTP; 25 Sep 2014 22:58:06 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby azsmga001.ch.intel.com with ESMTP; 25 Sep 2014 23:04:20 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8Q64IJl029347;\n\tFri, 26 Sep 2014 14:04:18 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8Q64FA9013033; Fri, 26 Sep 2014 14:04:17 +0800", "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8Q64FKS013029; \n\tFri, 26 Sep 2014 14:04:15 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,603,1406617200\"; d=\"scan'208\";a=\"480127264\"", "From": "Jingjing Wu <jingjing.wu@intel.com>", "To": "dev@dpdk.org", "Date": "Fri, 26 Sep 2014 14:03:34 +0800", "Message-Id": "<1411711418-12881-17-git-send-email-jingjing.wu@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411711418-12881-1-git-send-email-jingjing.wu@intel.com>", "References": "<1411711418-12881-1-git-send-email-jingjing.wu@intel.com>", "Subject": "[dpdk-dev] [PATCH v316/20] i40e: implement operations to configure\n\tflexible payload", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "implement operation to flexible payload in i40e pmd driver\n\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\nAcked-by: Chen Jing D(Mark) <jing.d.chen@intel.com>\nAcked-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/i40e_fdir.c | 101 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 101 insertions(+)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c\nindex 973c8e0..01693a2 100644\n--- a/lib/librte_pmd_i40e/i40e_fdir.c\n+++ b/lib/librte_pmd_i40e/i40e_fdir.c\n@@ -80,8 +80,11 @@\n #define I40E_COUNTER_PF 2\n /* Statistic counter index for one pf */\n #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)\n+#define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50\n \n static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);\n+static int i40e_set_flx_pld_cfg(struct i40e_pf *pf,\n+\t\t\t struct rte_eth_flex_payload_cfg *cfg);\n static int i40e_fdir_construct_pkt(struct i40e_pf *pf,\n \t\t\t\t struct rte_eth_fdir_input *fdir_input,\n \t\t\t\t unsigned char *raw_pkt);\n@@ -325,6 +328,97 @@ i40e_fdir_teardown(struct i40e_pf *pf)\n \treturn;\n }\n \n+/*\n+ * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload\n+ * @pf: board private structure\n+ * @cfg: the rule how bytes stream is extracted as flexible payload\n+ */\n+static int\n+i40e_set_flx_pld_cfg(struct i40e_pf *pf,\n+\t\t\t struct rte_eth_flex_payload_cfg *cfg)\n+{\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\tstruct rte_eth_fdir_info fdir;\n+\tuint32_t flx_pit;\n+\tuint16_t min_next_off = 0;\n+\tuint8_t idx = 0;\n+\tint i = 0;\n+\tint num_word = 0;\n+\tint ret;\n+\n+\tif (cfg == NULL || cfg->nb_field > 3)\n+\t\treturn -EINVAL;\n+\n+\tif (cfg->type == RTE_ETH_L2_PAYLOAD)\n+\t\tidx = 0;\n+\telse if (cfg->type == RTE_ETH_L3_PAYLOAD)\n+\t\tidx = 1;\n+\telse if (cfg->type == RTE_ETH_L4_PAYLOAD)\n+\t\tidx = 2;\n+\telse {\n+\t\tPMD_DRV_LOG(ERR, \"unknown payload type.\");\n+\t\treturn -EINVAL;\n+\t}\n+\t/*\n+\t * flexible payload need to be configured before\n+\t * flow director filters are added\n+\t * If filters exist, flush them.\n+\t */\n+\tmemset(&fdir, 0, sizeof(fdir));\n+\ti40e_fdir_info_get(pf, &fdir);\n+\tif (fdir.info_ext.best_cnt + fdir.info_ext.guarant_cnt > 0) {\n+\t\tret = i40e_fdir_flush(pf);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(ERR, \" failed to flush fdir table.\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < cfg->nb_field; i++) {\n+\t\t/*\n+\t\t * check register's constrain\n+\t\t * Current Offset >= previous offset + previous FSIZE.\n+\t\t */\n+\t\tif (cfg->field[i].offset < min_next_off) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Offset should be larger than\"\n+\t\t\t\t\"previous offset + previous FSIZE.\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tflx_pit = (cfg->field[i].offset <<\n+\t\t\tI40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) &\n+\t\t\tI40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK;\n+\t\tflx_pit |= (cfg->field[i].size <<\n+\t\t\t\tI40E_PRTQF_FLX_PIT_FSIZE_SHIFT) &\n+\t\t\t\tI40E_PRTQF_FLX_PIT_FSIZE_MASK;\n+\t\tflx_pit |= ((num_word + I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<\n+\t\t\t\tI40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) &\n+\t\t\t\tI40E_PRTQF_FLX_PIT_DEST_OFF_MASK;\n+\t\t/* support no more than 8 words flexible payload*/\n+\t\tnum_word += cfg->field[i].size;\n+\t\tif (num_word > 8)\n+\t\t\treturn -EINVAL;\n+\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(idx * 3 + i), flx_pit);\n+\t\t/* record the info in fdir structure */\n+\t\tpf->fdir.flex_set[idx][i].offset = cfg->field[i].offset;\n+\t\tpf->fdir.flex_set[idx][i].size = cfg->field[i].size;\n+\t\tmin_next_off = cfg->field[i].offset + cfg->field[i].size;\n+\t}\n+\n+\tfor (; i < 3; i++) {\n+\t\t/* set the non-used register obeying register's constrain */\n+\t\tflx_pit = (min_next_off << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) &\n+\t\t\tI40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK;\n+\t\tflx_pit |= (1 << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) &\n+\t\t\tI40E_PRTQF_FLX_PIT_FSIZE_MASK;\n+\t\tflx_pit |= (63 << I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) &\n+\t\t\tI40E_PRTQF_FLX_PIT_DEST_OFF_MASK;\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(idx * 3 + i), flx_pit);\n+\t\tmin_next_off++;\n+\t}\n+\n+\treturn 0;\n+}\n static int\n i40e_fdir_construct_pkt(struct i40e_pf *pf,\n \t\t\t struct rte_eth_fdir_input *fdir_input,\n@@ -944,6 +1038,7 @@ i40e_fdir_info_get(struct i40e_pf *pf, struct rte_eth_fdir_info *fdir)\n int\n i40e_fdir_ctrl_func(struct i40e_pf *pf, enum rte_filter_op filter_op, void *arg)\n {\n+\tstruct rte_eth_fdir_cfg *fdir_cfg = NULL;\n \tint ret = I40E_SUCCESS;\n \n \tif (arg == NULL && filter_op != RTE_ETH_FILTER_OP_NONE &&\n@@ -968,6 +1063,12 @@ i40e_fdir_ctrl_func(struct i40e_pf *pf, enum rte_filter_op filter_op, void *arg)\n \tcase RTE_ETH_FILTER_OP_FLUSH:\n \t\tret = i40e_fdir_flush(pf);\n \t\tbreak;\n+\tcase RTE_ETH_FILTER_OP_SET:\n+\t\tfdir_cfg = (struct rte_eth_fdir_cfg *)arg;\n+\t\tif (fdir_cfg->cmd == RTE_ETH_FDIR_CFG_FLX)\n+\t\t\tret = i40e_set_flx_pld_cfg(pf,\n+\t\t\t\t(struct rte_eth_flex_payload_cfg *)fdir_cfg->cfg);\n+\t\tbreak;\n \tcase RTE_ETH_FILTER_OP_GET_INFO:\n \t\ti40e_fdir_info_get(pf, (struct rte_eth_fdir_info *)arg);\n \t\tbreak;\n", "prefixes": [ "dpdk-dev", "v316/20" ] }