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GET /api/patches/55287/?format=api
{ "id": 55287, "url": "https://patches.dpdk.org/api/patches/55287/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1561449018-26218-1-git-send-email-andy.pei@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1561449018-26218-1-git-send-email-andy.pei@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1561449018-26218-1-git-send-email-andy.pei@intel.com", "date": "2019-06-25T07:50:15", "name": "[v4,1/4] net/ipn3ke: add new register address", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "980d66b714356b9d8ac01a60709dbc5a9fcd9639", "submitter": { "id": 1185, "url": "https://patches.dpdk.org/api/people/1185/?format=api", "name": "Pei, Andy", "email": "andy.pei@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1561449018-26218-1-git-send-email-andy.pei@intel.com/mbox/", "series": [ { "id": 5146, "url": "https://patches.dpdk.org/api/series/5146/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5146", "date": "2019-06-25T07:50:15", "name": "[v4,1/4] net/ipn3ke: add new register address", "version": 4, "mbox": "https://patches.dpdk.org/series/5146/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/55287/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/55287/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DA2FA1BBE5;\n\tTue, 25 Jun 2019 09:57:22 +0200 (CEST)", "from mga05.intel.com (mga05.intel.com [192.55.52.43])\n\tby dpdk.org (Postfix) with ESMTP id CE7A81BB9D\n\tfor <dev@dpdk.org>; Tue, 25 Jun 2019 09:57:20 +0200 (CEST)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Jun 2019 00:57:19 -0700", "from dipei-st-npg.sh.intel.com ([10.67.110.220])\n\tby orsmga003.jf.intel.com with ESMTP; 25 Jun 2019 00:57:18 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.63,415,1557212400\"; d=\"scan'208\";a=\"163900469\"", "From": "Andy Pei <andy.pei@intel.com>", "To": "dev@dpdk.org", "Cc": "andy.pei@intel.com,\n\trosen.xu@intel.com", "Date": "Tue, 25 Jun 2019 15:50:15 +0800", "Message-Id": "<1561449018-26218-1-git-send-email-andy.pei@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1560934174-408632-4-git-send-email-andy.pei@intel.com>", "References": "<1560934174-408632-4-git-send-email-andy.pei@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 1/4] net/ipn3ke: add new register address", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "ipn3ke can work on 10G mode and 25G mode.\n10G mode and 25G mode has different MAC register address for statistics.\nThis patch implemente statistics registers for 10G mode and 25G mode.\n\nFixes: c01c748e4ae6 (\"net/ipn3ke: add new driver\")\nCc: rosen.xu@intel.com\n\nSigned-off-by: Andy Pei <andy.pei@intel.com>\n---\n drivers/net/ipn3ke/ipn3ke_ethdev.h | 590 ++++++++++++++++++++++---------------\n 1 file changed, 345 insertions(+), 245 deletions(-)", "diff": "diff --git a/drivers/net/ipn3ke/ipn3ke_ethdev.h b/drivers/net/ipn3ke/ipn3ke_ethdev.h\nindex af2da05..61a5dbb 100644\n--- a/drivers/net/ipn3ke/ipn3ke_ethdev.h\n+++ b/drivers/net/ipn3ke/ipn3ke_ethdev.h\n@@ -650,239 +650,298 @@ static inline void _ipn3ke_indrct_write(struct ipn3ke_hw *hw,\n #define IPN3KE_MAC_RX_FRAME_MAXLENGTH_MASK \\\n \tIPN3KE_MASK(0xFFFF, IPN3KE_MAC_RX_FRAME_MAXLENGTH_SHIFT)\n \n-#define IPN3KE_MAC_TX_STATS_CLR 0x0140\n-#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT 0\n-#define IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK \\\n-\tIPN3KE_MASK(0x1, IPN3KE_MAC_TX_STATS_CLR_CLEAR_SHIFT)\n-\n-#define IPN3KE_MAC_RX_STATS_CLR 0x01C0\n-#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT 0\n-#define IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK \\\n-\tIPN3KE_MASK(0x1, IPN3KE_MAC_RX_STATS_CLR_CLEAR_SHIFT)\n-\n-/*tx_stats_framesOK*/\n-#define IPN3KE_MAC_TX_STATS_FRAMESOK_HI 0x0142\n-#define IPN3KE_MAC_TX_STATS_FRAMESOK_LOW 0x0143\n-\n-/*rx_stats_framesOK*/\n-#define IPN3KE_MAC_RX_STATS_FRAMESOK_HI 0x01C2\n-#define IPN3KE_MAC_RX_STATS_FRAMESOK_LOW 0x01C3\n-\n-/*tx_stats_framesErr*/\n-#define IPN3KE_MAC_TX_STATS_FRAMESERR_HI 0x0144\n-#define IPN3KE_MAC_TX_STATS_FRAMESERR_LOW 0x0145\n-\n-/*rx_stats_framesErr*/\n-#define IPN3KE_MAC_RX_STATS_FRAMESERR_HI 0x01C4\n-#define IPN3KE_MAC_RX_STATS_FRAMESERR_LOW 0x01C5\n-\n-/*rx_stats_framesCRCErr*/\n-#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_HI 0x01C6\n-#define IPN3KE_MAC_RX_STATS_FRAMESCRCERR_LOW 0x01C7\n-\n-/*tx_stats_octetsOK 64b*/\n-#define IPN3KE_MAC_TX_STATS_OCTETSOK_HI 0x0148\n-#define IPN3KE_MAC_TX_STATS_OCTETSOK_LOW 0x0149\n-\n-/*rx_stats_octetsOK 64b*/\n-#define IPN3KE_MAC_RX_STATS_OCTETSOK_HI 0x01C8\n-#define IPN3KE_MAC_RX_STATS_OCTETSOK_LOW 0x01C9\n-\n-/*tx_stats_pauseMACCtrl_Frames*/\n-#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_HI 0x014A\n-#define IPN3KE_MAC_TX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x014B\n-\n-/*rx_stats_pauseMACCtrl_Frames*/\n-#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_HI 0x01CA\n-#define IPN3KE_MAC_RX_STATS_PAUSEMACCTRL_FRAMES_LOW 0x01CB\n-\n-/*tx_stats_ifErrors*/\n-#define IPN3KE_MAC_TX_STATS_IFERRORS_HI 0x014C\n-#define IPN3KE_MAC_TX_STATS_IFERRORS_LOW 0x014D\n-\n-/*rx_stats_ifErrors*/\n-#define IPN3KE_MAC_RX_STATS_IFERRORS_HI 0x01CC\n-#define IPN3KE_MAC_RX_STATS_IFERRORS_LOW 0x01CD\n-\n-/*tx_stats_unicast_FramesOK*/\n-#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_HI 0x014E\n-#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESOK_LOW 0x014F\n-\n-/*rx_stats_unicast_FramesOK*/\n-#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_HI 0x01CE\n-#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESOK_LOW 0x01CF\n-\n-/*tx_stats_unicast_FramesErr*/\n-#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_HI 0x0150\n-#define IPN3KE_MAC_TX_STATS_UNICAST_FRAMESERR_LOW 0x0151\n-\n-/*rx_stats_unicast_FramesErr*/\n-#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_HI 0x01D0\n-#define IPN3KE_MAC_RX_STATS_UNICAST_FRAMESERR_LOW 0x01D1\n-\n-/*tx_stats_multicast_FramesOK*/\n-#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_HI 0x0152\n-#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESOK_LOW 0x0153\n-\n-/*rx_stats_multicast_FramesOK*/\n-#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_HI 0x01D2\n-#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESOK_LOW 0x01D3\n-\n-/*tx_stats_multicast_FramesErr*/\n-#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_HI 0x0154\n-#define IPN3KE_MAC_TX_STATS_MULTICAST_FRAMESERR_LOW 0x0155\n-\n-/*rx_stats_multicast_FramesErr*/\n-#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_HI 0x01D4\n-#define IPN3KE_MAC_RX_STATS_MULTICAST_FRAMESERR_LOW 0x01D5\n-\n-/*tx_stats_broadcast_FramesOK*/\n-#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_HI 0x0156\n-#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESOK_LOW 0x0157\n-\n-/*rx_stats_broadcast_FramesOK*/\n-#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_HI 0x01D6\n-#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESOK_LOW 0x01D7\n-\n-/*tx_stats_broadcast_FramesErr*/\n-#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_HI 0x0158\n-#define IPN3KE_MAC_TX_STATS_BROADCAST_FRAMESERR_LOW 0x0159\n-\n-/*rx_stats_broadcast_FramesErr*/\n-#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_HI 0x01D8\n-#define IPN3KE_MAC_RX_STATS_BROADCAST_FRAMESERR_LOW 0x01D9\n-\n-/*tx_stats_etherStatsOctets 64b*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_HI 0x015A\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSOCTETS_LOW 0x015B\n-\n-/*rx_stats_etherStatsOctets 64b*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_HI 0x01DA\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSOCTETS_LOW 0x01DB\n-\n-/*tx_stats_etherStatsPkts*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_HI 0x015C\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS_LOW 0x015D\n-\n-/*rx_stats_etherStatsPkts*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_HI 0x01DC\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS_LOW 0x01DD\n-\n-/*tx_stats_etherStatsUndersizePkts*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x015E\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x015F\n-\n-/*rx_stats_etherStatsUndersizePkts*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_HI 0x01DE\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSUNDERSIZEPKTS_LOW 0x01DF\n-\n-/*tx_stats_etherStatsOversizePkts*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x0160\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x0161\n-\n-/*rx_stats_etherStatsOversizePkts*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_HI 0x01E0\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSOVERSIZEPKTS_LOW 0x01E1\n-\n-/*tx_stats_etherStatsPkts64Octets*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x0162\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x0163\n-\n-/*rx_stats_etherStatsPkts64Octets*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_HI 0x01E2\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS64OCTETS_LOW 0x01E3\n-\n-/*tx_stats_etherStatsPkts65to127Octets*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x0164\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x0165\n-\n-/*rx_stats_etherStatsPkts65to127Octets*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_HI 0x01E4\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS65TO127OCTETS_LOW 0x01E5\n-\n-/*tx_stats_etherStatsPkts128to255Octets*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x0166\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x0167\n-\n-/*rx_stats_etherStatsPkts128to255Octets*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_HI 0x01E6\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS128TO255OCTETS_LOW 0x01E7\n-\n-/*tx_stats_etherStatsPkts256to511Octet*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_HI 0x0168\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS256TO511OCTET_LOW 0x0169\n-\n-/*rx_stats_etherStatsPkts256to511Octets*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_HI 0x01E8\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS256TO511OCTETS_LOW 0x01E9\n-\n-/*tx_stats_etherStatsPkts512to1023Octets*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x016A\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x016B\n-\n-/*rx_stats_etherStatsPkts512to1023Octets*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_HI 0x01EA\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS512TO1023OCTETS_LOW 0x01EB\n-\n-/*tx_stats_etherStatPkts1024to1518Octets*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x016C\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x016D\n-\n-/*rx_stats_etherStatPkts1024to1518Octets*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_HI 0x01EC\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATPKTS1024TO1518OCTETS_LOW 0x01ED\n-\n-/*tx_stats_etherStatsPkts1519toXOctets*/\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x016E\n-#define IPN3KE_MAC_TX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x016F\n-\n-/*rx_stats_etherStatsPkts1519toXOctets*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_HI 0x01EE\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSPKTS1519TOXOCTETS_LOW 0x01EF\n-\n-/*rx_stats_etherStatsFragments*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_HI 0x01F0\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSFRAGMENTS_LOW 0x01F1\n-\n-/*rx_stats_etherStatsJabbers*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_HI 0x01F2\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSJABBERS_LOW 0x01F3\n-\n-/*rx_stats_etherStatsCRCErr*/\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_HI 0x01F4\n-#define IPN3KE_MAC_RX_STATS_ETHERSTATSCRCERR_LOW 0x01F5\n-\n-/*tx_stats_unicastMACCtrlFrames*/\n-#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_HI 0x0176\n-#define IPN3KE_MAC_TX_STATS_UNICASTMACCTRLFRAMES_LOW 0x0177\n-\n-/*rx_stats_unicastMACCtrlFrames*/\n-#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_HI 0x01F6\n-#define IPN3KE_MAC_RX_STATS_UNICASTMACCTRLFRAMES_LOW 0x01F7\n-\n-/*tx_stats_multicastMACCtrlFrames*/\n-#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_HI 0x0178\n-#define IPN3KE_MAC_TX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x0179\n-\n-/*rx_stats_multicastMACCtrlFrames*/\n-#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_HI 0x01F8\n-#define IPN3KE_MAC_RX_STATS_MULTICASTMACCTRLFRAMES_LOW 0x01F9\n-\n-/*tx_stats_broadcastMACCtrlFrames*/\n-#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_HI 0x017A\n-#define IPN3KE_MAC_TX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x017B\n-\n-/*rx_stats_broadcastMACCtrlFrames*/\n-#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_HI 0x01FA\n-#define IPN3KE_MAC_RX_STATS_BROADCASTMACCTRLFRAMES_LOW 0x01FB\n-\n-/*tx_stats_PFCMACCtrlFrames*/\n-#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_HI 0x017C\n-#define IPN3KE_MAC_TX_STATS_PFCMACCTRLFRAMES_LOW 0x017D\n-\n-/*rx_stats_PFCMACCtrlFrames*/\n-#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_HI 0x01FC\n-#define IPN3KE_MAC_RX_STATS_PFCMACCTRLFRAMES_LOW 0x01FD\n+#define IPN3KE_REGISTER_WIDTH 32\n+\n+/*Bits[2:0]: Configuration of TX statistics counters:\n+ *Bit[2]: Shadow request (active high): When set to the value of 1,\n+ *TX statistics collection is paused. The underlying counters\n+ *continue to operate, but the readable values reflect a snapshot at\n+ *the time the pause flag was activated. Write a 0 to release.\n+ *Bit[1]: Parity-error clear. When software sets this bit, the IP core\n+ *clears the parity bit CNTR_TX_STATUS[0]. This bit\n+ *(CNTR_TX_CONFIG[1]) is self-clearing.\n+ *Bit[0]: Software can set this bit to the value of 1 to reset all of\n+ *the TX statistics registers at the same time. This bit is selfclearing.\n+ *Bits[31:3] are Reserved\n+ */\n+#define IPN3KE_25G_TX_STATISTICS_CONFIG 0x845\n+#define IPN3KE_25G_TX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK 0x00000004\n+\n+/*Bit[1]: Indicates that the TX statistics registers are paused (while\n+ *CNTR_TX_CONFIG[2] is asserted).\n+ *Bit[0]: Indicates the presence of at least one parity error in the\n+ *TX statistics counters.\n+ *Bits[31:2] are Reserved.\n+ */\n+#define IPN3KE_25G_TX_STATISTICS_STATUS 0x846\n+#define IPN3KE_25G_TX_STATISTICS_STATUS_SHADOW_REQUEST_MASK 0x00000002\n+\n+#define IPN3KE_25G_CNTR_TX_FRAGMENTS_LO 0x800\n+#define IPN3KE_25G_CNTR_TX_FRAGMENTS_HI 0x801\n+#define IPN3KE_25G_CNTR_TX_JABBERS_LO 0x802\n+#define IPN3KE_25G_CNTR_TX_JABBERS_HI 0x803\n+#define IPN3KE_25G_CNTR_TX_FCS_LO 0x804\n+#define IPN3KE_25G_CNTR_TX_FCS_HI 0x805\n+#define IPN3KE_25G_CNTR_TX_CRCERR_LO 0x806\n+#define IPN3KE_25G_CNTR_TX_CRCERR_HI 0x807\n+#define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_LO 0x808\n+#define IPN3KE_25G_CNTR_TX_MCAST_DATA_ERR_HI 0x809\n+#define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_LO 0x80A\n+#define IPN3KE_25G_CNTR_TX_BCAST_DATA_ERR_HI 0x80B\n+#define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_LO 0x80C\n+#define IPN3KE_25G_CNTR_TX_UCAST_DATA_ERR_HI 0x80D\n+#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_LO 0x80E\n+#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_ERR_HI 0x80F\n+#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_LO 0x810\n+#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_ERR_HI 0x811\n+#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_LO 0x812\n+#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_ERR_HI 0x813\n+#define IPN3KE_25G_CNTR_TX_PAUSE_ERR_LO 0x814\n+#define IPN3KE_25G_CNTR_TX_PAUSE_ERR_HI 0x815\n+#define IPN3KE_25G_CNTR_TX_64B_LO 0x816\n+#define IPN3KE_25G_CNTR_TX_64B_HI 0x817\n+#define IPN3KE_25G_CNTR_TX_65_127B_LO 0x818\n+#define IPN3KE_25G_CNTR_TX_65_127B_HI 0x819\n+#define IPN3KE_25G_CNTR_TX_128_255B_LO 0x81A\n+#define IPN3KE_25G_CNTR_TX_128_255B_HI 0x81B\n+#define IPN3KE_25G_CNTR_TX_256_511B_LO 0x81C\n+#define IPN3KE_25G_CNTR_TX_256_511B_HI 0x81D\n+#define IPN3KE_25G_CNTR_TX_512_1023B_LO 0x81E\n+#define IPN3KE_25G_CNTR_TX_512_1023B_HI 0x81F\n+#define IPN3KE_25G_CNTR_TX_1024_1518B_LO 0x820\n+#define IPN3KE_25G_CNTR_TX_1024_1518B_HI 0x821\n+#define IPN3KE_25G_CNTR_TX_1519_MAXB_LO 0x822\n+#define IPN3KE_25G_CNTR_TX_1519_MAXB_HI 0x823\n+#define IPN3KE_25G_CNTR_TX_OVERSIZE_LO 0x824\n+#define IPN3KE_25G_CNTR_TX_OVERSIZE_HI 0x825\n+#define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_LO 0x826\n+#define IPN3KE_25G_CNTR_TX_MCAST_DATA_OK_HI 0x827\n+#define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_LO 0x828\n+#define IPN3KE_25G_CNTR_TX_BCAST_DATA_OK_HI 0x829\n+#define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_LO 0x82A\n+#define IPN3KE_25G_CNTR_TX_UCAST_DATA_OK_HI 0x82B\n+#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_LO 0x82C\n+#define IPN3KE_25G_CNTR_TX_MCAST_CTRL_HI 0x82D\n+#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_LO 0x82E\n+#define IPN3KE_25G_CNTR_TX_BCAST_CTRL_HI 0x82F\n+#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_LO 0x830\n+#define IPN3KE_25G_CNTR_TX_UCAST_CTRL_HI 0x831\n+#define IPN3KE_25G_CNTR_TX_PAUSE_LO 0x832\n+#define IPN3KE_25G_CNTR_TX_PAUSE_HI 0x833\n+#define IPN3KE_25G_CNTR_TX_RUNT_LO 0x834\n+#define IPN3KE_25G_CNTR_TX_RUNT_HI 0x835\n+#define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_LO 0x860\n+#define IPN3KE_25G_TX_PAYLOAD_OCTETS_OK_HI 0x861\n+#define IPN3KE_25G_TX_FRAME_OCTETS_OK_LO 0x862\n+#define IPN3KE_25G_TX_FRAME_OCTETS_OK_HI 0x863\n+\n+/*Bits[2:0]: Configuration of RX statistics counters:\n+ *Bit[2]: Shadow request (active high): When set to the value of 1,\n+ *RX statistics collection is paused. The underlying counters\n+ *continue to operate, but the readable values reflect a snapshot\n+ *at the time the pause flag was activated. Write a 0 to release.\n+ *Bit[1]: Parity-error clear. When software sets this bit, the IP\n+ *core clears the parity bit CNTR_RX_STATUS[0]. This bit\n+ *(CNTR_RX_CONFIG[1]) is self-clearing.\n+ *Bit[0]: Software can set this bit to the value of 1 to reset all of\n+ *the RX statistics registers at the same time. This bit is selfclearing.\n+ *Bits[31:3] are Reserved.\n+ */\n+#define IPN3KE_25G_RX_STATISTICS_CONFIG 0x945\n+#define IPN3KE_25G_RX_STATISTICS_CONFIG_SHADOW_REQUEST_MASK 0x00000004\n+\n+/*Bit[1]: Indicates that the RX statistics registers are paused\n+ *(while CNTR_RX_CONFIG[2] is asserted).\n+ *Bit[0]: Indicates the presence of at least one parity error in the\n+ *RX statistics counters.\n+ *Bits [31:2] are Reserved\n+ */\n+#define IPN3KE_25G_RX_STATISTICS_STATUS 0x946\n+#define IPN3KE_25G_RX_STATISTICS_STATUS_SHADOW_REQUEST_MASK 0x00000002\n+\n+#define IPN3KE_25G_CNTR_RX_FRAGMENTS_LO 0x900\n+#define IPN3KE_25G_CNTR_RX_FRAGMENTS_HI 0x901\n+#define IPN3KE_25G_CNTR_RX_JABBERS_LO 0x902\n+#define IPN3KE_25G_CNTR_RX_JABBERS_HI 0x903\n+#define IPN3KE_25G_CNTR_RX_FCS_LO 0x904\n+#define IPN3KE_25G_CNTR_RX_FCS_HI 0x905\n+#define IPN3KE_25G_CNTR_RX_CRCERR_LO 0x906\n+#define IPN3KE_25G_CNTR_RX_CRCERR_HI 0x907\n+#define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_LO 0x908\n+#define IPN3KE_25G_CNTR_RX_MCAST_DATA_ERR_HI 0x909\n+#define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_LO 0x90A\n+#define IPN3KE_25G_CNTR_RX_BCAST_DATA_ERR_HI 0x90B\n+#define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_LO 0x90C\n+#define IPN3KE_25G_CNTR_RX_UCAST_DATA_ERR_HI 0x90D\n+#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_LO 0x90E\n+#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_ERR_HI 0x90F\n+#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_LO 0x910\n+#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_ERR_HI 0x911\n+#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_LO 0x912\n+#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_ERR_HI 0x913\n+#define IPN3KE_25G_CNTR_RX_PAUSE_ERR_LO 0x914\n+#define IPN3KE_25G_CNTR_RX_PAUSE_ERR_HI 0x915\n+#define IPN3KE_25G_CNTR_RX_64B_LO 0x916\n+#define IPN3KE_25G_CNTR_RX_64B_HI 0x917\n+#define IPN3KE_25G_CNTR_RX_65_127B_LO 0x918\n+#define IPN3KE_25G_CNTR_RX_65_127B_HI 0x919\n+#define IPN3KE_25G_CNTR_RX_128_255B_LO 0x91A\n+#define IPN3KE_25G_CNTR_RX_128_255B_HI 0x91B\n+#define IPN3KE_25G_CNTR_RX_256_511B_LO 0x91C\n+#define IPN3KE_25G_CNTR_RX_256_511B_HI 0x91D\n+#define IPN3KE_25G_CNTR_RX_512_1023B_LO 0x91E\n+#define IPN3KE_25G_CNTR_RX_512_1023B_HI 0x91F\n+#define IPN3KE_25G_CNTR_RX_1024_1518B_LO 0x920\n+#define IPN3KE_25G_CNTR_RX_1024_1518B_HI 0x921\n+#define IPN3KE_25G_CNTR_RX_1519_MAXB_LO 0x922\n+#define IPN3KE_25G_CNTR_RX_1519_MAXB_HI 0x923\n+#define IPN3KE_25G_CNTR_RX_OVERSIZE_LO 0x924\n+#define IPN3KE_25G_CNTR_RX_OVERSIZE_HI 0x925\n+#define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_LO 0x926\n+#define IPN3KE_25G_CNTR_RX_MCAST_DATA_OK_HI 0x927\n+#define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_LO 0x928\n+#define IPN3KE_25G_CNTR_RX_BCAST_DATA_OK_HI 0x929\n+#define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_LO 0x92A\n+#define IPN3KE_25G_CNTR_RX_UCAST_DATA_OK_HI 0x92B\n+#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_LO 0x92C\n+#define IPN3KE_25G_CNTR_RX_MCAST_CTRL_HI 0x92D\n+#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_LO 0x92E\n+#define IPN3KE_25G_CNTR_RX_BCAST_CTRL_HI 0x92F\n+#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_LO 0x930\n+#define IPN3KE_25G_CNTR_RX_UCAST_CTRL_HI 0x931\n+#define IPN3KE_25G_CNTR_RX_PAUSE_LO 0x932\n+#define IPN3KE_25G_CNTR_RX_PAUSE_HI 0x933\n+#define IPN3KE_25G_CNTR_RX_RUNT_LO 0x934\n+#define IPN3KE_25G_CNTR_RX_RUNT_HI 0x935\n+#define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_LO 0x960\n+#define IPN3KE_25G_RX_PAYLOAD_OCTETS_OK_HI 0x961\n+#define IPN3KE_25G_RX_FRAME_OCTETS_OK_LO 0x962\n+#define IPN3KE_25G_RX_FRAME_OCTETS_OK_HI 0x963\n+\n+#define IPN3KE_10G_STATS_HI_VALID_MASK 0x0000000F\n+\n+#define IPN3KE_10G_TX_STATS_CLR 0x0140\n+#define IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT 0\n+#define IPN3KE_10G_TX_STATS_CLR_CLEAR_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_10G_TX_STATS_CLR_CLEAR_SHIFT)\n+\n+#define IPN3KE_10G_RX_STATS_CLR 0x01C0\n+#define IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT 0\n+#define IPN3KE_10G_RX_STATS_CLR_CLEAR_MASK \\\n+\tIPN3KE_MASK(0x1, IPN3KE_10G_RX_STATS_CLR_CLEAR_SHIFT)\n+\n+#define IPN3KE_10G_TX_STATS_FRAME_OK_LO 0x0142\n+#define IPN3KE_10G_TX_STATS_FRAME_OK_HI 0x0143\n+#define IPN3KE_10G_RX_STATS_FRAME_OK_LO 0x01C2\n+#define IPN3KE_10G_RX_STATS_FRAME_OK_HI 0x01C3\n+#define IPN3KE_10G_TX_STATS_FRAME_ERR_LO 0x0144\n+#define IPN3KE_10G_TX_STATS_FRAME_ERR_HI 0x0145\n+#define IPN3KE_10G_RX_STATS_FRAME_ERR_LO 0x01C4\n+#define IPN3KE_10G_RX_STATS_FRAME_ERR_HI 0x01C5\n+#define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_LO 0x01C6\n+#define IPN3KE_10G_RX_STATS_FRAME_CRC_ERR_HI 0x01C7\n+#define IPN3KE_10G_TX_STATS_OCTETS_OK_LO 0x0148\n+#define IPN3KE_10G_TX_STATS_OCTETS_OK_HI 0x0149\n+#define IPN3KE_10G_RX_STATS_OCTETS_OK_LO 0x01C8\n+#define IPN3KE_10G_RX_STATS_OCTETS_OK_HI 0x01C9\n+#define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_LO 0x014A\n+#define IPN3KE_10G_TX_STATS_PAUSE_MAC_CTRL_FRAMES_HI 0x014B\n+#define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_LO 0x01CA\n+#define IPN3KE_10G_RX_STATS_PAUSE_MAC_CTRL_FRAMES_HI 0x01CB\n+#define IPN3KE_10G_TX_STATS_IF_ERRORS_LO 0x014C\n+#define IPN3KE_10G_TX_STATS_IF_ERRORS_HI 0x014D\n+#define IPN3KE_10G_RX_STATS_IF_ERRORS_LO 0x01CC\n+#define IPN3KE_10G_RX_STATS_IF_ERRORS_HI 0x01CD\n+#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_LO 0x014E\n+#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_OK_HI 0x014F\n+#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_LO 0x01CE\n+#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_OK_HI 0x01CF\n+#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_LO 0x0150\n+#define IPN3KE_10G_TX_STATS_UNICAST_FRAME_ERR_HI 0x0151\n+#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_LO 0x01D0\n+#define IPN3KE_10G_RX_STATS_UNICAST_FRAME_ERR_HI 0x01D1\n+#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_LO 0x0152\n+#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_OK_HI 0x0153\n+#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_LO 0x01D2\n+#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_OK_HI 0x01D3\n+#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_LO 0x0154\n+#define IPN3KE_10G_TX_STATS_MULTICAST_FRAME_ERR_HI 0x0155\n+#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_LO 0x01D4\n+#define IPN3KE_10G_RX_STATS_MULTICAST_FRAME_ERR_HI 0x01D5\n+#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_LO 0x0156\n+#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_OK_HI 0x0157\n+#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_LO 0x01D6\n+#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_OK_HI 0x01D7\n+#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_LO 0x0158\n+#define IPN3KE_10G_TX_STATS_BROADCAST_FRAME_ERR_HI 0x0159\n+#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_LO 0x01D8\n+#define IPN3KE_10G_RX_STATS_BROADCAST_FRAME_ERR_HI 0x01D9\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_LO 0x015A\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_OCTETS_HI 0x015B\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_LO 0x01DA\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_OCTETS_HI 0x01DB\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_LO 0x015C\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_HI 0x015D\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_LO 0x01DC\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_HI 0x01DD\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO 0x015E\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI 0x015F\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_LO 0x01DE\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_UNDER_SIZE_PKTS_HI 0x01DF\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO 0x0160\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI 0x0161\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_LO 0x01E0\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_OVER_SIZE_PKTS_HI 0x01E1\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO 0x0162\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI 0x0163\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_LO 0x01E2\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_64_OCTETS_HI 0x01E3\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO 0x0164\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI 0x0165\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_LO 0x01E4\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_65_127_OCTETS_HI 0x01E5\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO 0x0166\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI 0x0167\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_LO 0x01E6\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_128_255_OCTETS_HI 0x01E7\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO 0x0168\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI 0x0169\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_LO 0x01E8\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_256_511_OCTETS_HI 0x01E9\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO 0x016A\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI 0x016B\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_LO 0x01EA\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_512_1023_OCTETS_HI 0x01EB\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO 0x016C\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI 0x016D\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_LO 0x01EC\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1024_1518_OCTETS_HI 0x01ED\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO 0x016E\n+#define IPN3KE_10G_TX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI 0x016F\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_LO 0x01EE\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_PKTS_1519_X_OCTETS_HI 0x01EF\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_LO 0x01E0\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_FRAGMENTS_HI 0x01F1\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_LO 0x01E2\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_JABBERS_HI 0x01F3\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_LO 0x01E4\n+#define IPN3KE_10G_RX_STATS_ETHER_STATS_CRC_ERR_HI 0x01F5\n+#define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_LO 0x0176\n+#define IPN3KE_10G_TX_STATS_UNICAST_MAC_CTRL_FRAMES_HI 0x0177\n+#define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_LO 0x01F6\n+#define IPN3KE_10G_RX_STATS_UNICAST_MAC_CTRL_FRAMES_HI 0x01F7\n+#define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO 0x0178\n+#define IPN3KE_10G_TX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI 0x0179\n+#define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_LO 0x01F8\n+#define IPN3KE_10G_RX_STATS_MULTICAST_MAC_CTRL_FRAMES_HI 0x01F9\n+#define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO 0x017A\n+#define IPN3KE_10G_TX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI 0x017B\n+#define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_LO 0x01FA\n+#define IPN3KE_10G_RX_STATS_BROADCAST_MAC_CTRL_FRAMES_HI 0x01FB\n+#define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_LO 0x017C\n+#define IPN3KE_10G_TX_STATS_PFC_MAC_CTRL_FRAMES_HI 0x017D\n+#define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_LO 0x01FC\n+#define IPN3KE_10G_RX_STATS_PFC_MAC_CTRL_FRAMES_HI 0x01FD\n \n static inline void ipn3ke_xmac_tx_enable(struct ipn3ke_hw *hw,\n \t\tuint32_t mac_num, uint32_t eth_group_sel)\n@@ -945,31 +1004,72 @@ static inline void ipn3ke_xmac_smac_ovd_dis(struct ipn3ke_hw *hw,\n \t\t\t\t\teth_group_sel);\n }\n \n-static inline void ipn3ke_xmac_tx_clr_stcs(struct ipn3ke_hw *hw,\n-\tuint32_t mac_num, uint32_t eth_group_sel)\n+static inline void ipn3ke_xmac_tx_clr_10G_stcs\n+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)\n {\n-#define IPN3KE_XMAC_TX_CLR_STCS (1 & \\\n-\t(IPN3KE_MAC_TX_STATS_CLR_CLEAR_MASK))\n+\tuint32_t tmp;\n+\ttmp = 0x00000000;\n+\t(*hw->f_mac_read)(hw,\n+\t\t\t\t\t&tmp,\n+\t\t\t\t\tIPN3KE_10G_TX_STATS_CLR,\n+\t\t\t\t\tmac_num,\n+\t\t\t\t\teth_group_sel);\n+\ttmp |= 0x00000001;\n+\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\ttmp,\n+\t\t\t\t\tIPN3KE_10G_TX_STATS_CLR,\n+\t\t\t\t\tmac_num,\n+\t\t\t\t\teth_group_sel);\n+}\n \n+static inline void ipn3ke_xmac_rx_clr_10G_stcs\n+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)\n+{\n+\tuint32_t tmp;\n+\ttmp = 0x00000000;\n+\t(*hw->f_mac_read)(hw,\n+\t\t\t\t\t&tmp,\n+\t\t\t\t\tIPN3KE_10G_RX_STATS_CLR,\n+\t\t\t\t\tmac_num,\n+\t\t\t\t\teth_group_sel);\n+\ttmp |= 0x00000001;\n \t(*hw->f_mac_write)(hw,\n-\t\t\t\t\tIPN3KE_XMAC_TX_CLR_STCS,\n-\t\t\t\t\tIPN3KE_MAC_TX_STATS_CLR,\n+\t\t\t\t\ttmp,\n+\t\t\t\t\tIPN3KE_10G_RX_STATS_CLR,\n \t\t\t\t\tmac_num,\n \t\t\t\t\teth_group_sel);\n }\n \n-static inline void ipn3ke_xmac_rx_clr_stcs(struct ipn3ke_hw *hw,\n-\tuint32_t mac_num, uint32_t eth_group_sel)\n+static inline void ipn3ke_xmac_tx_clr_25G_stcs\n+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)\n {\n-#define IPN3KE_XMAC_RX_CLR_STCS (1 & \\\n-\t(IPN3KE_MAC_RX_STATS_CLR_CLEAR_MASK))\n+\tuint32_t tmp = 0x00000001;\n \n+\t/* Bit[0]: Software can set this bit to the value of 1\n+\t * to reset all of the TX statistics registers at the same time.\n+\t * This bit is selfclearing.\n+\t */\n \t(*hw->f_mac_write)(hw,\n-\t\t\t\t\tIPN3KE_XMAC_RX_CLR_STCS,\n-\t\t\t\t\tIPN3KE_MAC_RX_STATS_CLR,\n+\t\t\t\t\ttmp,\n+\t\t\t\t\tIPN3KE_25G_TX_STATISTICS_CONFIG,\n \t\t\t\t\tmac_num,\n \t\t\t\t\teth_group_sel);\n }\n \n+static inline void ipn3ke_xmac_rx_clr_25G_stcs\n+(struct ipn3ke_hw *hw, uint32_t mac_num, uint32_t eth_group_sel)\n+{\n+\tuint32_t tmp = 0x00000001;\n+\n+\t/* Bit[0]: Software can set this bit to the value of 1\n+\t * to reset all of the RX statistics registers at the same time.\n+\t * This bit is selfclearing.\n+\t */\n+\t(*hw->f_mac_write)(hw,\n+\t\t\t\t\ttmp,\n+\t\t\t\t\tIPN3KE_25G_RX_STATISTICS_CONFIG,\n+\t\t\t\t\tmac_num,\n+\t\t\t\t\teth_group_sel);\n+}\n \n #endif /* _IPN3KE_ETHDEV_H_ */\n", "prefixes": [ "v4", "1/4" ] }