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GET /api/patches/55215/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 55215,
    "url": "https://patches.dpdk.org/api/patches/55215/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-27-jerinj@marvell.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190622132417.32694-27-jerinj@marvell.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190622132417.32694-27-jerinj@marvell.com",
    "date": "2019-06-22T13:24:16",
    "name": "[v4,26/27] mempool/octeontx2: add devargs for max pool selection",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "75f92469dd3d4b55887df5ac4c8ab24998e6d1f5",
    "submitter": {
        "id": 1188,
        "url": "https://patches.dpdk.org/api/people/1188/?format=api",
        "name": "Jerin Jacob Kollanukkaran",
        "email": "jerinj@marvell.com"
    },
    "delegate": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/users/1/?format=api",
        "username": "tmonjalo",
        "first_name": "Thomas",
        "last_name": "Monjalon",
        "email": "thomas@monjalon.net"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190622132417.32694-27-jerinj@marvell.com/mbox/",
    "series": [
        {
            "id": 5124,
            "url": "https://patches.dpdk.org/api/series/5124/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=5124",
            "date": "2019-06-22T13:23:50",
            "name": "OCTEON TX2 common and mempool driver",
            "version": 4,
            "mbox": "https://patches.dpdk.org/series/5124/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/55215/comments/",
    "check": "fail",
    "checks": "https://patches.dpdk.org/api/patches/55215/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C227E1D010;\n\tSat, 22 Jun 2019 15:26:51 +0200 (CEST)",
            "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n\t[67.231.148.174]) by dpdk.org (Postfix) with ESMTP id ADECB1CDF7\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 15:25:48 +0200 (CEST)",
            "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n\tby mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id\n\tx5MDOd2m028283 for <dev@dpdk.org>; Sat, 22 Jun 2019 06:25:48 -0700",
            "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0a-0016f401.pphosted.com with ESMTP id 2t9hpnrghg-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n\tfor <dev@dpdk.org>; Sat, 22 Jun 2019 06:25:47 -0700",
            "from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tSat, 22 Jun 2019 06:25:46 -0700",
            "from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Sat, 22 Jun 2019 06:25:46 -0700",
            "from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14])\n\tby maili.marvell.com (Postfix) with ESMTP id E39C93F703F;\n\tSat, 22 Jun 2019 06:25:44 -0700 (PDT)"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=gzs4puvF1mB6n+riegbq62g6dxMGU95hgvNcoxG0XQg=;\n\tb=cs4yAMJn9W79Xkqvq8CEu+KQXKMkp3tT/xb4lDJw/ieeRyWN3hVb/vvgiCYiMWF12S9Q\n\tghy2jK3RpMYj3KilTaXRfpfs5yKWYHvSIgA7wUmGv8lSO7KxauDjX8n8zCKJoAi/7dWB\n\tWriDpGOg+XEIDS1/Yg1ihplPSuGHl2Waxyzmin76Ny4gVelQjGAOWwIzkcOSvr6eLXnC\n\tw26tGnHCnh2U4mx+eBJEyZeOy18Z//MmBMN5apnxHx2o9iOVT8+brQ/6rvNhpFmY2PI+\n\tv5d/NJ0wPrLJqdnC3xH3+oHf51eT9USJCHP8vnayv40O+tplhFcJl7i8d/YP1IKrH6PN\n\tgg== ",
        "From": "<jerinj@marvell.com>",
        "To": "Jerin Jacob <jerinj@marvell.com>, Nithin Dabilpuram\n\t<ndabilpuram@marvell.com>, Vamsi Attunuru <vattunuru@marvell.com>",
        "CC": "<dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>",
        "Date": "Sat, 22 Jun 2019 18:54:16 +0530",
        "Message-ID": "<20190622132417.32694-27-jerinj@marvell.com>",
        "X-Mailer": "git-send-email 2.21.0",
        "In-Reply-To": "<20190622132417.32694-1-jerinj@marvell.com>",
        "References": "<20190617155537.36144-1-jerinj@marvell.com>\n\t<20190622132417.32694-1-jerinj@marvell.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:, ,\n\tdefinitions=2019-06-22_09:, , signatures=0",
        "Subject": "[dpdk-dev] [PATCH v4 26/27] mempool/octeontx2: add devargs for max\n\tpool selection",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Jerin Jacob <jerinj@marvell.com>\n\nThe maximum number of mempools per application needs to be configured\non HW during mempool driver initialization. HW can support up to 1M\nmempools, Since each mempool costs set of HW resources, the max_pools\ndevargs parameter is being introduced to configure the number of\nmempools required for the application.\nFor example:\n\n-w 0002:02:00.0,max_pools=512\n\nWith the above configuration, the driver will set up only 512 mempools\nfor the given application to save HW resources.\n\nSigned-off-by: Jerin Jacob <jerinj@marvell.com>\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/mempool/octeontx2/otx2_mempool.c | 41 +++++++++++++++++++++++-\n 1 file changed, 40 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c\nindex c47f95fb0..9a5f11cf4 100644\n--- a/drivers/mempool/octeontx2/otx2_mempool.c\n+++ b/drivers/mempool/octeontx2/otx2_mempool.c\n@@ -7,6 +7,7 @@\n #include <rte_common.h>\n #include <rte_eal.h>\n #include <rte_io.h>\n+#include <rte_kvargs.h>\n #include <rte_malloc.h>\n #include <rte_mbuf_pool_ops.h>\n #include <rte_pci.h>\n@@ -159,6 +160,42 @@ otx2_aura_size_to_u32(uint8_t val)\n \treturn 1 << (val + 6);\n }\n \n+static int\n+parse_max_pools(const char *key, const char *value, void *extra_args)\n+{\n+\tRTE_SET_USED(key);\n+\tuint32_t val;\n+\n+\tval = atoi(value);\n+\tif (val < otx2_aura_size_to_u32(NPA_AURA_SZ_128))\n+\t\tval = 128;\n+\tif (val > otx2_aura_size_to_u32(NPA_AURA_SZ_1M))\n+\t\tval = BIT_ULL(20);\n+\n+\t*(uint8_t *)extra_args = rte_log2_u32(val) - 6;\n+\treturn 0;\n+}\n+\n+#define OTX2_MAX_POOLS \"max_pools\"\n+\n+static uint8_t\n+otx2_parse_aura_size(struct rte_devargs *devargs)\n+{\n+\tuint8_t aura_sz = NPA_AURA_SZ_128;\n+\tstruct rte_kvargs *kvlist;\n+\n+\tif (devargs == NULL)\n+\t\tgoto exit;\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (kvlist == NULL)\n+\t\tgoto exit;\n+\n+\trte_kvargs_process(kvlist, OTX2_MAX_POOLS, &parse_max_pools, &aura_sz);\n+\trte_kvargs_free(kvlist);\n+exit:\n+\treturn aura_sz;\n+}\n+\n static inline int\n npa_lf_attach(struct otx2_mbox *mbox)\n {\n@@ -251,7 +288,7 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)\n \t\tif (rc)\n \t\t\tgoto npa_detach;\n \n-\t\taura_sz = NPA_AURA_SZ_128;\n+\t\taura_sz = otx2_parse_aura_size(pci_dev->device.devargs);\n \t\tnr_pools = otx2_aura_size_to_u32(aura_sz);\n \n \t\tlf = &dev->npalf;\n@@ -414,3 +451,5 @@ static struct rte_pci_driver pci_npa = {\n RTE_PMD_REGISTER_PCI(mempool_octeontx2, pci_npa);\n RTE_PMD_REGISTER_PCI_TABLE(mempool_octeontx2, pci_npa_map);\n RTE_PMD_REGISTER_KMOD_DEP(mempool_octeontx2, \"vfio-pci\");\n+RTE_PMD_REGISTER_PARAM_STRING(mempool_octeontx2,\n+\t\t\t      OTX2_MAX_POOLS \"=<128-1048576>\");\n",
    "prefixes": [
        "v4",
        "26/27"
    ]
}