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{
    "id": 542,
    "url": "https://patches.dpdk.org/api/patches/542/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411711418-12881-4-git-send-email-jingjing.wu@intel.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1411711418-12881-4-git-send-email-jingjing.wu@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1411711418-12881-4-git-send-email-jingjing.wu@intel.com",
    "date": "2014-09-26T06:03:21",
    "name": "[dpdk-dev,v3,03/20] i40e: initialize flexible payload setting",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8dba97d43665a8927dc215b88ee20f0f419441f9",
    "submitter": {
        "id": 47,
        "url": "https://patches.dpdk.org/api/people/47/?format=api",
        "name": "Jingjing Wu",
        "email": "jingjing.wu@intel.com"
    },
    "delegate": null,
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411711418-12881-4-git-send-email-jingjing.wu@intel.com/mbox/",
    "series": [],
    "comments": "https://patches.dpdk.org/api/patches/542/comments/",
    "check": "pending",
    "checks": "https://patches.dpdk.org/api/patches/542/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 2BC5A7DF7;\n\tFri, 26 Sep 2014 07:57:36 +0200 (CEST)",
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            "(from wujingji@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8Q63kPx012933; \n\tFri, 26 Sep 2014 14:03:46 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.04,603,1406617200\"; d=\"scan'208\";a=\"597109889\"",
        "From": "Jingjing Wu <jingjing.wu@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Fri, 26 Sep 2014 14:03:21 +0800",
        "Message-Id": "<1411711418-12881-4-git-send-email-jingjing.wu@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1411711418-12881-1-git-send-email-jingjing.wu@intel.com>",
        "References": "<1411711418-12881-1-git-send-email-jingjing.wu@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v3 03/20] i40e: initialize flexible payload\n\tsetting",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "set flexible payload related registers to default value at initialization time.\n\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\nAcked-by: Chen Jing D(Mark) <jing.d.chen@intel.com>\nAcked-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 33 ++++++++++++++++++++++++++\n lib/librte_pmd_i40e/i40e_fdir.c   | 49 +++++++++++++++++++++++++++++++++++++++\n 2 files changed, 82 insertions(+)",
    "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex da131a8..a3f25e6 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -336,6 +336,32 @@ static struct rte_driver rte_i40e_driver = {\n \n PMD_REGISTER_DRIVER(rte_i40e_driver);\n \n+/*\n+ * Initialize registers for flexible payload, which should be set by NVM.\n+ * This should be removed from code once is fixed in NVM.\n+ */\n+static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)\n+{\n+\t/* GLQF_ORT Registers */\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);\n+\n+\t/* GLQF_PIT Registers */\n+\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);\n+\tI40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);\n+\n+\t/* GL_PRS_FVBM Registers */\n+\tI40E_WRITE_REG(hw, I40E_GL_PRS_FVBM(1), 0x8000035B);\n+}\n+\n static int\n eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,\n                   struct rte_eth_dev *dev)\n@@ -399,6 +425,13 @@ eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,\n \t\treturn ret;\n \t}\n \n+\t/*\n+\t * To work around the NVM issue,initialize registers\n+\t * for flexible payload by software.\n+\t * It should be removed once issues are fixed in NVM.\n+\t */\n+\ti40e_flex_payload_reg_init(hw);\n+\n \t/* Initialize the parameters for adminq */\n \ti40e_init_adminq_parameter(hw);\n \tret = i40e_init_adminq(hw);\ndiff --git a/lib/librte_pmd_i40e/i40e_fdir.c b/lib/librte_pmd_i40e/i40e_fdir.c\nindex 3d8faa0..a3e6bd7 100644\n--- a/lib/librte_pmd_i40e/i40e_fdir.c\n+++ b/lib/librte_pmd_i40e/i40e_fdir.c\n@@ -109,6 +109,53 @@ i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)\n }\n \n /*\n+ * Initialize the configuration about bytes stream extracted as flexible payload\n+ * and mask setting\n+ */\n+static inline void\n+i40e_init_flx_pld(struct i40e_pf *pf)\n+{\n+\tuint8_t pctype;;\n+\tstruct i40e_hw *hw = I40E_PF_TO_HW(pf);\n+\n+\t/*\n+\t * Define the bytes stream extracted as flexible payload in\n+\t * field vector. By default, select 8 words from the beginning\n+\t * of payload as flexible payload.\n+\t */\n+\tmemset(pf->fdir.flex_set, 0, sizeof(pf->fdir.flex_set));\n+\n+\t/* initialize the flexible payload for L2 payload*/\n+\tpf->fdir.flex_set[0][0].offset = 0;\n+\tpf->fdir.flex_set[0][0].size = 8;\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(0), 0x0000C900);\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(1), 0x0000FC29);/*non-used*/\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(2), 0x0000FC2A);/*non-used*/\n+\n+\t/* initialize the flexible payload for L3 payload*/\n+\tpf->fdir.flex_set[1][0].offset = 0;\n+\tpf->fdir.flex_set[1][0].size = 8;\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(3), 0x0000C900);\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(4), 0x0000FC29);/*non-used*/\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(5), 0x0000FC2A);/*non-used*/\n+\n+\t/* initialize the flexible payload for L4 payload*/\n+\tpf->fdir.flex_set[2][0].offset = 0;\n+\tpf->fdir.flex_set[2][0].size = 8;\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(6), 0x0000C900);\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(7), 0x0000FC29);/*non-used*/\n+\tI40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(8), 0x0000FC2A);/*non-used*/\n+\n+\t/* initialize the masks */\n+\tfor (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;\n+\t     pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, 0), 0);\n+\t\tI40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, 1), 0);\n+\t}\n+}\n+\n+/*\n  * i40e_fdir_setup - reserve and initialize the Flow Director resources\n  * @pf: board private structure\n  */\n@@ -182,6 +229,8 @@ i40e_fdir_setup(struct i40e_pf *pf)\n \t\tgoto fail_mem;\n \t}\n \n+\ti40e_init_flx_pld(pf);\n+\n \t/* reserve memory for the fdir programming packet */\n \tsnprintf(z_name, sizeof(z_name), \"%s_%s_%d\",\n \t\t\teth_dev->driver->pci_drv.name,\n",
    "prefixes": [
        "dpdk-dev",
        "v3",
        "03/20"
    ]
}