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GET /api/patches/53930/?format=api
https://patches.dpdk.org/api/patches/53930/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190530212525.40370-4-bruce.richardson@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190530212525.40370-4-bruce.richardson@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190530212525.40370-4-bruce.richardson@intel.com", "date": "2019-05-30T21:25:20", "name": "[3/8] raw/ioat: add register definition file", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "86b37c2232c03d0457c9a2b82cc6be00e46d1b1e", "submitter": { "id": 20, "url": "https://patches.dpdk.org/api/people/20/?format=api", "name": "Bruce Richardson", "email": "bruce.richardson@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190530212525.40370-4-bruce.richardson@intel.com/mbox/", "series": [ { "id": 4831, "url": "https://patches.dpdk.org/api/series/4831/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=4831", "date": "2019-05-30T21:25:17", "name": "raw/ioat: driver for Intel QuickData Technology", "version": 1, "mbox": "https://patches.dpdk.org/series/4831/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/53930/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/53930/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A08651B94D;\n\tThu, 30 May 2019 23:25:53 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id C70614CA6\n\tfor <dev@dpdk.org>; Thu, 30 May 2019 23:25:45 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t30 May 2019 14:25:44 -0700", "from silpixa00399126.ir.intel.com (HELO\n\tsilpixa00399126.ger.corp.intel.com) ([10.237.223.2])\n\tby orsmga001.jf.intel.com with ESMTP; 30 May 2019 14:25:44 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Bruce Richardson <bruce.richardson@intel.com>", "To": "dev@dpdk.org", "Cc": "Bruce Richardson <bruce.richardson@intel.com>", "Date": "Thu, 30 May 2019 22:25:20 +0100", "Message-Id": "<20190530212525.40370-4-bruce.richardson@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190530212525.40370-1-bruce.richardson@intel.com>", "References": "<20190530212525.40370-1-bruce.richardson@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 3/8] raw/ioat: add register definition file", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add in the list of registers for the device. File is taken from the SPDK\nproject:\n\n https://github.com/spdk/spdk/blob/master/include/spdk/ioat_spec.h\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n drivers/raw/ioat/Makefile | 1 +\n drivers/raw/ioat/meson.build | 3 +-\n drivers/raw/ioat/rte_ioat_spec.h | 301 +++++++++++++++++++++++++++++++\n 3 files changed, 304 insertions(+), 1 deletion(-)\n create mode 100644 drivers/raw/ioat/rte_ioat_spec.h", "diff": "diff --git a/drivers/raw/ioat/Makefile b/drivers/raw/ioat/Makefile\nindex 7726e310a..1e10938f3 100644\n--- a/drivers/raw/ioat/Makefile\n+++ b/drivers/raw/ioat/Makefile\n@@ -24,5 +24,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV) += ioat_rawdev.c\n \n # export include files\n SYMLINK-y-include += rte_ioat_rawdev.h\n+SYMLINK-y-include += rte_ioat_spec.h\n \n include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/raw/ioat/meson.build b/drivers/raw/ioat/meson.build\nindex ba7620a68..ca23e23fc 100644\n--- a/drivers/raw/ioat/meson.build\n+++ b/drivers/raw/ioat/meson.build\n@@ -5,4 +5,5 @@ build = dpdk_conf.has('RTE_ARCH_X86')\n sources = files('ioat_rawdev.c')\n deps += ['rawdev', 'bus_pci']\n \n-install_headers('rte_ioat_rawdev.h')\n+install_headers('rte_ioat_rawdev.h',\n+\t\t'rte_ioat_spec.h')\ndiff --git a/drivers/raw/ioat/rte_ioat_spec.h b/drivers/raw/ioat/rte_ioat_spec.h\nnew file mode 100644\nindex 000000000..305e36ded\n--- /dev/null\n+++ b/drivers/raw/ioat/rte_ioat_spec.h\n@@ -0,0 +1,301 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) Intel Corporation\n+ */\n+\n+/**\n+ * \\file\n+ * I/OAT specification definitions\n+ *\n+ * Taken from ioat_spec.h from SPDK project, with prefix renames and\n+ * other minor changes.\n+ */\n+\n+#ifndef RTE_IOAT_SPEC_H\n+#define RTE_IOAT_SPEC_H\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include <stdint.h>\n+\n+#define RTE_IOAT_PCI_CHANERR_INT_OFFSET\t0x180\n+\n+#define RTE_IOAT_INTRCTRL_MASTER_INT_EN\t0x01\n+\n+#define RTE_IOAT_VER_3_0 0x30\n+#define RTE_IOAT_VER_3_3 0x33\n+\n+/* DMA Channel Registers */\n+#define RTE_IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK\t0xF000\n+#define RTE_IOAT_CHANCTRL_COMPL_DCA_EN\t\t0x0200\n+#define RTE_IOAT_CHANCTRL_CHANNEL_IN_USE\t\t0x0100\n+#define RTE_IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL\t0x0020\n+#define RTE_IOAT_CHANCTRL_ERR_INT_EN\t\t0x0010\n+#define RTE_IOAT_CHANCTRL_ANY_ERR_ABORT_EN\t\t0x0008\n+#define RTE_IOAT_CHANCTRL_ERR_COMPLETION_EN\t\t0x0004\n+#define RTE_IOAT_CHANCTRL_INT_REARM\t\t\t0x0001\n+\n+/* DMA Channel Capabilities */\n+#define\tRTE_IOAT_DMACAP_PB\t\t(1 << 0)\n+#define\tRTE_IOAT_DMACAP_DCA\t\t(1 << 4)\n+#define\tRTE_IOAT_DMACAP_BFILL\t\t(1 << 6)\n+#define\tRTE_IOAT_DMACAP_XOR\t\t(1 << 8)\n+#define\tRTE_IOAT_DMACAP_PQ\t\t(1 << 9)\n+#define\tRTE_IOAT_DMACAP_DMA_DIF\t(1 << 10)\n+\n+struct rte_ioat_registers {\n+\tuint8_t\t\tchancnt;\n+\tuint8_t\t\txfercap;\n+\tuint8_t\t\tgenctrl;\n+\tuint8_t\t\tintrctrl;\n+\tuint32_t\tattnstatus;\n+\tuint8_t\t\tcbver;\t\t/* 0x08 */\n+\tuint8_t\t\treserved4[0x3]; /* 0x09 */\n+\tuint16_t\tintrdelay;\t/* 0x0C */\n+\tuint16_t\tcs_status;\t/* 0x0E */\n+\tuint32_t\tdmacapability;\t/* 0x10 */\n+\tuint8_t\t\treserved5[0x6C]; /* 0x14 */\n+\tuint16_t\tchanctrl;\t/* 0x80 */\n+\tuint8_t\t\treserved6[0x2];\t/* 0x82 */\n+\tuint8_t\t\tchancmd;\t/* 0x84 */\n+\tuint8_t\t\treserved3[1];\t/* 0x85 */\n+\tuint16_t\tdmacount;\t/* 0x86 */\n+\tuint64_t\tchansts;\t/* 0x88 */\n+\tuint64_t\tchainaddr;\t/* 0x90 */\n+\tuint64_t\tchancmp;\t/* 0x98 */\n+\tuint8_t\t\treserved2[0x8];\t/* 0xA0 */\n+\tuint32_t\tchanerr;\t/* 0xA8 */\n+\tuint32_t\tchanerrmask;\t/* 0xAC */\n+} __attribute__((packed));\n+\n+#define RTE_IOAT_CHANCMD_RESET\t\t\t0x20\n+#define RTE_IOAT_CHANCMD_SUSPEND\t\t0x04\n+\n+#define RTE_IOAT_CHANSTS_STATUS\t\t0x7ULL\n+#define RTE_IOAT_CHANSTS_ACTIVE\t\t0x0\n+#define RTE_IOAT_CHANSTS_IDLE\t\t\t0x1\n+#define RTE_IOAT_CHANSTS_SUSPENDED\t\t0x2\n+#define RTE_IOAT_CHANSTS_HALTED\t\t0x3\n+#define RTE_IOAT_CHANSTS_ARMED\t\t\t0x4\n+\n+#define RTE_IOAT_CHANSTS_UNAFFILIATED_ERROR\t0x8ULL\n+#define RTE_IOAT_CHANSTS_SOFT_ERROR\t\t0x10ULL\n+\n+#define RTE_IOAT_CHANSTS_COMPLETED_DESCRIPTOR_MASK\t(~0x3FULL)\n+\n+#define RTE_IOAT_CHANCMP_ALIGN\t\t\t8\t/* CHANCMP address must be 64-bit aligned */\n+\n+struct rte_ioat_generic_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t reserved2: 1;\n+\t\t\tuint32_t src_page_break: 1;\n+\t\t\tuint32_t dest_page_break: 1;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t reserved: 13;\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t op_specific[4];\n+};\n+\n+struct rte_ioat_dma_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t null: 1;\n+\t\t\tuint32_t src_page_break: 1;\n+\t\t\tuint32_t dest_page_break: 1;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t reserved: 13;\n+#define RTE_IOAT_OP_COPY 0x00\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t reserved;\n+\tuint64_t reserved2;\n+\tuint64_t user1;\n+\tuint64_t user2;\n+};\n+\n+struct rte_ioat_fill_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t reserved: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t reserved2: 2;\n+\t\t\tuint32_t dest_page_break: 1;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t reserved3: 15;\n+#define RTE_IOAT_OP_FILL 0x01\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_data;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t reserved;\n+\tuint64_t next_dest_addr;\n+\tuint64_t user1;\n+\tuint64_t user2;\n+};\n+\n+struct rte_ioat_xor_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t src_count: 3;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t reserved: 13;\n+#define RTE_IOAT_OP_XOR 0x87\n+#define RTE_IOAT_OP_XOR_VAL 0x88\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t dest_addr;\n+\tuint64_t next;\n+\tuint64_t src_addr2;\n+\tuint64_t src_addr3;\n+\tuint64_t src_addr4;\n+\tuint64_t src_addr5;\n+};\n+\n+struct rte_ioat_xor_ext_hw_desc {\n+\tuint64_t src_addr6;\n+\tuint64_t src_addr7;\n+\tuint64_t src_addr8;\n+\tuint64_t next;\n+\tuint64_t reserved[4];\n+};\n+\n+struct rte_ioat_pq_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t src_count: 3;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t p_disable: 1;\n+\t\t\tuint32_t q_disable: 1;\n+\t\t\tuint32_t reserved: 11;\n+#define RTE_IOAT_OP_PQ 0x89\n+#define RTE_IOAT_OP_PQ_VAL 0x8a\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t p_addr;\n+\tuint64_t next;\n+\tuint64_t src_addr2;\n+\tuint64_t src_addr3;\n+\tuint8_t coef[8];\n+\tuint64_t q_addr;\n+};\n+\n+struct rte_ioat_pq_ext_hw_desc {\n+\tuint64_t src_addr4;\n+\tuint64_t src_addr5;\n+\tuint64_t src_addr6;\n+\tuint64_t next;\n+\tuint64_t src_addr7;\n+\tuint64_t src_addr8;\n+\tuint64_t reserved[2];\n+};\n+\n+struct rte_ioat_pq_update_hw_desc {\n+\tuint32_t size;\n+\tunion {\n+\t\tuint32_t control_raw;\n+\t\tstruct {\n+\t\t\tuint32_t int_enable: 1;\n+\t\t\tuint32_t src_snoop_disable: 1;\n+\t\t\tuint32_t dest_snoop_disable: 1;\n+\t\t\tuint32_t completion_update: 1;\n+\t\t\tuint32_t fence: 1;\n+\t\t\tuint32_t src_cnt: 3;\n+\t\t\tuint32_t bundle: 1;\n+\t\t\tuint32_t dest_dca: 1;\n+\t\t\tuint32_t hint: 1;\n+\t\t\tuint32_t p_disable: 1;\n+\t\t\tuint32_t q_disable: 1;\n+\t\t\tuint32_t reserved: 3;\n+\t\t\tuint32_t coef: 8;\n+#define RTE_IOAT_OP_PQ_UP 0x8b\n+\t\t\tuint32_t op: 8;\n+\t\t} control;\n+\t} u;\n+\tuint64_t src_addr;\n+\tuint64_t p_addr;\n+\tuint64_t next;\n+\tuint64_t src_addr2;\n+\tuint64_t p_src;\n+\tuint64_t q_src;\n+\tuint64_t q_addr;\n+};\n+\n+struct rte_ioat_raw_hw_desc {\n+\tuint64_t field[8];\n+};\n+\n+union rte_ioat_hw_desc {\n+\tstruct rte_ioat_raw_hw_desc raw;\n+\tstruct rte_ioat_generic_hw_desc generic;\n+\tstruct rte_ioat_dma_hw_desc dma;\n+\tstruct rte_ioat_fill_hw_desc fill;\n+\tstruct rte_ioat_xor_hw_desc xor_desc;\n+\tstruct rte_ioat_xor_ext_hw_desc xor_ext;\n+\tstruct rte_ioat_pq_hw_desc pq;\n+\tstruct rte_ioat_pq_ext_hw_desc pq_ext;\n+\tstruct rte_ioat_pq_update_hw_desc pq_update;\n+};\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* RTE_IOAT_SPEC_H */\n", "prefixes": [ "3/8" ] }{ "id": 53930, "url": "