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GET /api/patches/53763/?format=api
{ "id": 53763, "url": "https://patches.dpdk.org/api/patches/53763/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190528120553.2992-28-lukaszx.krakowiak@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190528120553.2992-28-lukaszx.krakowiak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190528120553.2992-28-lukaszx.krakowiak@intel.com", "date": "2019-05-28T12:05:53", "name": "[27/27] sched: code cleanup", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0cda5faf187bffbbbb472affb857cfddfe2487a6", "submitter": { "id": 1221, "url": "https://patches.dpdk.org/api/people/1221/?format=api", "name": "Lukasz Krakowiak", "email": "lukaszx.krakowiak@intel.com" }, "delegate": { "id": 10018, "url": "https://patches.dpdk.org/api/users/10018/?format=api", "username": "cristian_dumitrescu", "first_name": "Cristian", "last_name": "Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190528120553.2992-28-lukaszx.krakowiak@intel.com/mbox/", "series": [ { "id": 4794, "url": "https://patches.dpdk.org/api/series/4794/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=4794", "date": "2019-05-28T12:05:26", "name": "sched: feature enhancements", "version": 1, "mbox": "https://patches.dpdk.org/series/4794/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/53763/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/53763/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id D57051BAB6;\n\tTue, 28 May 2019 14:09:02 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 320071B9C4\n\tfor <dev@dpdk.org>; Tue, 28 May 2019 14:08:55 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 May 2019 05:08:54 -0700", "from lkrakowx-mobl.ger.corp.intel.com ([10.103.104.99])\n\tby fmsmga001.fm.intel.com with ESMTP; 28 May 2019 05:08:53 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Lukasz Krakowiak <lukaszx.krakowiak@intel.com>", "To": "cristian.dumitrescu@intel.com", "Cc": "dev@dpdk.org, Jasvinder Singh <jasvinder.singh@intel.com>,\n\tAbraham Tovar <abrahamx.tovar@intel.com>,\n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Tue, 28 May 2019 14:05:53 +0200", "Message-Id": "<20190528120553.2992-28-lukaszx.krakowiak@intel.com>", "X-Mailer": "git-send-email 2.19.2.windows.1", "In-Reply-To": "<20190528120553.2992-1-lukaszx.krakowiak@intel.com>", "References": "<20190528120553.2992-1-lukaszx.krakowiak@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 27/27] sched: code cleanup", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jasvinder Singh <jasvinder.singh@intel.com>\n\nRemove redundant macros and fields from the data structures.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 53 ------------------------------------\n lib/librte_sched/rte_sched.h | 18 ------------\n 2 files changed, 71 deletions(-)", "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex 563161713..79731af8e 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -100,18 +100,7 @@ struct rte_sched_grinder {\n \tuint32_t tc_index;\n \tstruct rte_sched_strict_priority_class sp;\n \tstruct rte_sched_best_effort_class be;\n-\tstruct rte_sched_queue *queue[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tstruct rte_mbuf **qbase[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint32_t qindex[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint16_t qsize;\n-\tuint32_t qmask;\n-\tuint32_t qpos;\n \tstruct rte_mbuf *pkt;\n-\n-\t/* WRR */\n-\tuint16_t wrr_tokens[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\tuint16_t wrr_mask[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\tuint8_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n };\n \n struct rte_sched_subport {\n@@ -215,7 +204,6 @@ struct rte_sched_pipe {\n \t/* TC oversubscription */\n \tuint32_t tc_ov_credits;\n \tuint8_t tc_ov_period_id;\n-\tuint8_t reserved[3];\n } __rte_cache_aligned;\n \n struct rte_sched_queue {\n@@ -233,18 +221,10 @@ struct rte_sched_queue_extra {\n struct rte_sched_port {\n \t/* User parameters */\n \tuint32_t n_subports_per_port;\n-\tuint32_t n_pipes_per_subport;\n-\tuint32_t n_pipes_per_subport_log2;\n \tint socket;\n \tuint32_t rate;\n \tuint32_t mtu;\n \tuint32_t frame_overhead;\n-\tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\tuint32_t n_pipe_profiles;\n-\tuint32_t pipe_tc3_rate_max;\n-#ifdef RTE_SCHED_RED\n-\tstruct rte_red_config red_config[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS];\n-#endif\n \n \t/* Timing */\n \tuint64_t time_cpu_cycles; /* Current CPU time measured in CPU cyles */\n@@ -252,50 +232,17 @@ struct rte_sched_port {\n \tuint64_t time; /* Current NIC TX time measured in bytes */\n \tstruct rte_reciprocal inv_cycles_per_byte; /* CPU cycles per byte */\n \n-\t/* Scheduling loop detection */\n-\tuint32_t pipe_loop;\n-\tuint32_t pipe_exhaustion;\n-\n-\t/* Bitmap */\n-\tstruct rte_bitmap *bmp;\n-\tuint32_t grinder_base_bmp_pos[RTE_SCHED_PORT_N_GRINDERS] __rte_aligned_16;\n-\n \t/* Grinders */\n-\tstruct rte_sched_grinder grinder[RTE_SCHED_PORT_N_GRINDERS];\n-\tuint32_t busy_grinders;\n \tstruct rte_mbuf **pkts_out;\n \tuint32_t n_pkts_out;\n \tuint32_t subport_id;\n \n \tuint32_t n_max_subport_pipes_log2; /* Max number of subport pipes */\n \n-\t/* Queue base calculation */\n-\tuint32_t qsize_add[RTE_SCHED_QUEUES_PER_PIPE];\n-\tuint32_t qsize_sum;\n-\n \t/* Large data structures */\n-\tstruct rte_sched_subport *subport;\n-\tstruct rte_sched_pipe *pipe;\n-\tstruct rte_sched_queue *queue;\n-\tstruct rte_sched_queue_extra *queue_extra;\n-\tstruct rte_sched_pipe_profile *pipe_profiles;\n-\tuint8_t *bmp_array;\n-\tstruct rte_mbuf **queue_array;\n \tstruct rte_sched_subport *subports[RTE_SCHED_SUBPORTS_PER_PORT];\n-\tuint8_t memory[0] __rte_cache_aligned;\n } __rte_cache_aligned;\n \n-enum rte_sched_port_array {\n-\te_RTE_SCHED_PORT_ARRAY_SUBPORT = 0,\n-\te_RTE_SCHED_PORT_ARRAY_PIPE,\n-\te_RTE_SCHED_PORT_ARRAY_QUEUE,\n-\te_RTE_SCHED_PORT_ARRAY_QUEUE_EXTRA,\n-\te_RTE_SCHED_PORT_ARRAY_PIPE_PROFILES,\n-\te_RTE_SCHED_PORT_ARRAY_BMP_ARRAY,\n-\te_RTE_SCHED_PORT_ARRAY_QUEUE_ARRAY,\n-\te_RTE_SCHED_PORT_ARRAY_TOTAL,\n-};\n-\n enum rte_sched_subport_array {\n \te_RTE_SCHED_SUBPORT_ARRAY_PIPE = 0,\n \te_RTE_SCHED_SUBPORT_ARRAY_QUEUE,\ndiff --git a/lib/librte_sched/rte_sched.h b/lib/librte_sched/rte_sched.h\nindex 28b589309..5d6828e2e 100644\n--- a/lib/librte_sched/rte_sched.h\n+++ b/lib/librte_sched/rte_sched.h\n@@ -81,7 +81,6 @@ extern \"C\" {\n #define RTE_SCHED_WRR_QUEUES_PER_PIPE 8\n \n /** Number of traffic classes per pipe (as well as subport). */\n-#define RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS 4\n #define RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE \\\n (RTE_SCHED_QUEUES_PER_PIPE - RTE_SCHED_WRR_QUEUES_PER_PIPE + 1)\n \n@@ -95,10 +94,6 @@ extern \"C\" {\n /** Maximum number of pipe profiles that can be defined per subport.\n * Compile-time configurable.\n */\n-#ifndef RTE_SCHED_PIPE_PROFILES_PER_PORT\n-#define RTE_SCHED_PIPE_PROFILES_PER_PORT 256\n-#endif\n-\n #ifndef RTE_SCHED_PIPE_PROFILES_PER_SUBPORT\n #define RTE_SCHED_PIPE_PROFILES_PER_SUBPORT 256\n #endif\n@@ -229,19 +224,6 @@ struct rte_sched_port_params {\n \tuint32_t frame_overhead; /**< Framing overhead per packet\n \t\t\t\t\t * (measured in bytes) */\n \tuint32_t n_subports_per_port; /**< Number of subports */\n-\tuint32_t n_pipes_per_subport; /**< Number of pipes per subport */\n-\tuint16_t qsize[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE];\n-\t/**< Packet queue size for each traffic class.\n-\t * All queues within the same pipe traffic class have the same\n-\t * size. Queues from different pipes serving the same traffic\n-\t * class have the same size. */\n-\tstruct rte_sched_pipe_params *pipe_profiles;\n-\t/**< Pipe profile table.\n-\t * Every pipe is configured using one of the profiles from this table. */\n-\tuint32_t n_pipe_profiles; /**< Profiles in the pipe profile table */\n-#ifdef RTE_SCHED_RED\n-\tstruct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; /**< RED parameters */\n-#endif\n };\n \n /*\n", "prefixes": [ "27/27" ] }