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GET /api/patches/53741/?format=api
{ "id": 53741, "url": "https://patches.dpdk.org/api/patches/53741/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190528120553.2992-8-lukaszx.krakowiak@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190528120553.2992-8-lukaszx.krakowiak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190528120553.2992-8-lukaszx.krakowiak@intel.com", "date": "2019-05-28T12:05:33", "name": "[07/27] sched: update pipe profile add api", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "866ede1a2647d245258b506f7706135556dc57c3", "submitter": { "id": 1221, "url": "https://patches.dpdk.org/api/people/1221/?format=api", "name": "Lukasz Krakowiak", "email": "lukaszx.krakowiak@intel.com" }, "delegate": { "id": 10018, "url": "https://patches.dpdk.org/api/users/10018/?format=api", "username": "cristian_dumitrescu", "first_name": "Cristian", "last_name": "Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190528120553.2992-8-lukaszx.krakowiak@intel.com/mbox/", "series": [ { "id": 4794, "url": "https://patches.dpdk.org/api/series/4794/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=4794", "date": "2019-05-28T12:05:26", "name": "sched: feature enhancements", "version": 1, "mbox": "https://patches.dpdk.org/series/4794/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/53741/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/53741/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E72311B9A4;\n\tTue, 28 May 2019 14:08:27 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 342F51B956\n\tfor <dev@dpdk.org>; Tue, 28 May 2019 14:08:18 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 May 2019 05:08:17 -0700", "from lkrakowx-mobl.ger.corp.intel.com ([10.103.104.99])\n\tby fmsmga001.fm.intel.com with ESMTP; 28 May 2019 05:08:16 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Lukasz Krakowiak <lukaszx.krakowiak@intel.com>", "To": "cristian.dumitrescu@intel.com", "Cc": "dev@dpdk.org, Jasvinder Singh <jasvinder.singh@intel.com>,\n\tAbraham Tovar <abrahamx.tovar@intel.com>,\n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Tue, 28 May 2019 14:05:33 +0200", "Message-Id": "<20190528120553.2992-8-lukaszx.krakowiak@intel.com>", "X-Mailer": "git-send-email 2.19.2.windows.1", "In-Reply-To": "<20190528120553.2992-1-lukaszx.krakowiak@intel.com>", "References": "<20190528120553.2992-1-lukaszx.krakowiak@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 07/27] sched: update pipe profile add api", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jasvinder Singh <jasvinder.singh@intel.com>\n\nUpdate the pipe profile add api implementation of the scheduler to allow\nconfiguration flexiblity for pipe traffic classes and queues, and subport\nlevel configuration of the pipe parameters.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 257 +++++++++++++++++++++++++++--------\n lib/librte_sched/rte_sched.h | 3 +\n 2 files changed, 205 insertions(+), 55 deletions(-)", "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex 020c028fd..c1079cdaa 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -365,44 +365,49 @@ rte_sched_port_qsize(struct rte_sched_port *port, uint32_t qindex)\n \n static int\n pipe_profile_check(struct rte_sched_pipe_params *params,\n-\tuint32_t rate)\n+\tuint32_t rate, uint16_t *qsize)\n {\n \tuint32_t i;\n \n \t/* Pipe parameters */\n \tif (params == NULL)\n-\t\treturn -10;\n+\t\treturn -11;\n \n \t/* TB rate: non-zero, not greater than port rate */\n \tif (params->tb_rate == 0 ||\n \t\tparams->tb_rate > rate)\n-\t\treturn -11;\n+\t\treturn -12;\n \n \t/* TB size: non-zero */\n \tif (params->tb_size == 0)\n-\t\treturn -12;\n+\t\treturn -13;\n \n \t/* TC rate: non-zero, less than pipe rate */\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tif (params->tc_rate[i] == 0 ||\n-\t\t\tparams->tc_rate[i] > params->tb_rate)\n-\t\t\treturn -13;\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASS_BE; i++) {\n+\t\tif ((qsize[i] == 0 && params->tc_rate[i] != 0) ||\n+\t\t\t(qsize[i] != 0 && (params->tc_rate[i] == 0 ||\n+\t\t\tparams->tc_rate[i] > params->tb_rate)))\n+\t\t\treturn -14;\n \t}\n+\tif (params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] == 0)\n+\t\treturn -15;\n \n \t/* TC period: non-zero */\n \tif (params->tc_period == 0)\n-\t\treturn -14;\n+\t\treturn -16;\n \n #ifdef RTE_SCHED_SUBPORT_TC_OV\n \t/* TC3 oversubscription weight: non-zero */\n \tif (params->tc_ov_weight == 0)\n-\t\treturn -15;\n+\t\treturn -17;\n #endif\n \n \t/* Queue WRR weights: non-zero */\n-\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++) {\n-\t\tif (params->wrr_weights[i] == 0)\n-\t\t\treturn -16;\n+\tfor (i = 0; i < RTE_SCHED_WRR_QUEUES_PER_PIPE; i++) {\n+\t\tuint32_t qindex = RTE_SCHED_TRAFFIC_CLASS_BE + i;\n+\t\tif ((qsize[qindex] != 0 && params->wrr_weights[i] == 0) ||\n+\t\t\t(qsize[qindex] == 0 && params->wrr_weights[i] != 0))\n+\t\t\treturn -18;\n \t}\n \n \treturn 0;\n@@ -549,6 +554,120 @@ rte_sched_subport_get_array_base(struct rte_sched_subport_params *params,\n \treturn base;\n }\n \n+static void\n+rte_sched_pipe_queues_config(struct rte_sched_subport *subport,\n+\tstruct rte_sched_pipe_profile *dst)\n+{\n+\tuint32_t i;\n+\n+\t/* Queues: strict priority */\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASS_BE; i++)\n+\t\tif (subport->qsize[i])\n+\t\t\tdst->n_sp_queues++;\n+\n+\t/* Queues: best effort */\n+\tfor (i = 0; i < RTE_SCHED_WRR_QUEUES_PER_PIPE; i++)\n+\t\tif (subport->qsize[RTE_SCHED_TRAFFIC_CLASS_BE + i])\n+\t\t\tdst->n_be_queues++;\n+}\n+\n+static void\n+rte_sched_pipe_wrr_queues_config(struct rte_sched_pipe_params *src,\n+\tstruct rte_sched_pipe_profile *dst)\n+{\n+\tuint32_t wrr_cost[RTE_SCHED_WRR_QUEUES_PER_PIPE];\n+\n+\tif (dst->n_be_queues == 1) {\n+\t\tdst->wrr_cost[0] = (uint8_t) src->wrr_weights[0];\n+\n+\t\treturn;\n+\t}\n+\n+\tif (dst->n_be_queues == 2) {\n+\t\tuint32_t lcd;\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\n+\t\tlcd = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n+\n+\t\twrr_cost[0] = lcd / wrr_cost[0];\n+\t\twrr_cost[1] = lcd / wrr_cost[1];\n+\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\n+\t\treturn;\n+\t}\n+\n+\tif (dst->n_be_queues == 4) {\n+\t\tuint32_t lcd, lcd1, lcd2;\n+\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\t\twrr_cost[2] = src->wrr_weights[2];\n+\t\twrr_cost[3] = src->wrr_weights[3];\n+\n+\t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n+\t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n+\t\tlcd = rte_get_lcd(lcd1, lcd2);\n+\n+\t\twrr_cost[0] = lcd / wrr_cost[0];\n+\t\twrr_cost[1] = lcd / wrr_cost[1];\n+\t\twrr_cost[2] = lcd / wrr_cost[2];\n+\t\twrr_cost[3] = lcd / wrr_cost[3];\n+\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\t\tdst->wrr_cost[2] = (uint8_t) wrr_cost[2];\n+\t\tdst->wrr_cost[3] = (uint8_t) wrr_cost[3];\n+\n+\t\treturn;\n+\t}\n+\n+\tif (dst->n_be_queues == 8) {\n+\t\tuint32_t lcd1, lcd2, lcd3, lcd4, lcd5, lcd6, lcd7;\n+\n+\t\twrr_cost[0] = src->wrr_weights[0];\n+\t\twrr_cost[1] = src->wrr_weights[1];\n+\t\twrr_cost[2] = src->wrr_weights[2];\n+\t\twrr_cost[3] = src->wrr_weights[3];\n+\t\twrr_cost[4] = src->wrr_weights[4];\n+\t\twrr_cost[5] = src->wrr_weights[5];\n+\t\twrr_cost[6] = src->wrr_weights[6];\n+\t\twrr_cost[7] = src->wrr_weights[7];\n+\n+\t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n+\t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n+\t\tlcd3 = rte_get_lcd(wrr_cost[4], wrr_cost[5]);\n+\t\tlcd4 = rte_get_lcd(wrr_cost[6], wrr_cost[7]);\n+\n+\t\tlcd5 = rte_get_lcd(lcd1, lcd2);\n+\t\tlcd6 = rte_get_lcd(lcd3, lcd4);\n+\n+\t\tlcd7 = rte_get_lcd(lcd5, lcd6);\n+\n+\t\twrr_cost[0] = lcd7 / wrr_cost[0];\n+\t\twrr_cost[1] = lcd7 / wrr_cost[1];\n+\t\twrr_cost[2] = lcd7 / wrr_cost[2];\n+\t\twrr_cost[3] = lcd7 / wrr_cost[3];\n+\t\twrr_cost[4] = lcd7 / wrr_cost[4];\n+\t\twrr_cost[5] = lcd7 / wrr_cost[5];\n+\t\twrr_cost[6] = lcd7 / wrr_cost[6];\n+\t\twrr_cost[7] = lcd7 / wrr_cost[7];\n+\n+\t\tdst->wrr_cost[0] = (uint8_t) wrr_cost[0];\n+\t\tdst->wrr_cost[1] = (uint8_t) wrr_cost[1];\n+\t\tdst->wrr_cost[2] = (uint8_t) wrr_cost[2];\n+\t\tdst->wrr_cost[3] = (uint8_t) wrr_cost[3];\n+\t\tdst->wrr_cost[4] = (uint8_t) wrr_cost[4];\n+\t\tdst->wrr_cost[5] = (uint8_t) wrr_cost[5];\n+\t\tdst->wrr_cost[6] = (uint8_t) wrr_cost[6];\n+\t\tdst->wrr_cost[7] = (uint8_t) wrr_cost[7];\n+\n+\t\treturn;\n+\t}\n+}\n+\n static void\n rte_sched_subport_config_qsize(struct rte_sched_subport *subport)\n {\n@@ -564,15 +683,15 @@ rte_sched_subport_config_qsize(struct rte_sched_subport *subport)\n }\n \n static void\n-rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n+rte_sched_port_log_pipe_profile(struct rte_sched_subport *subport, uint32_t i)\n {\n-\tstruct rte_sched_pipe_profile *p = port->pipe_profiles + i;\n+\tstruct rte_sched_pipe_profile *p = subport->pipe_profiles + i;\n \n \tRTE_LOG(DEBUG, SCHED, \"Low level config for pipe profile %u:\\n\"\n \t\t\" Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n-\t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n-\t\t\" Traffic class 3 oversubscription: weight = %hhu\\n\"\n-\t\t\" WRR cost: [%hhu, %hhu, %hhu, %hhu], [%hhu, %hhu, %hhu, %hhu],\\n\",\n+\t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u, %u, %u, %u, %u, %u]\\n\"\n+\t\t\" Traffic class BE oversubscription: weight = %hhu\\n\"\n+\t\t\" WRR cost: [%hhu, %hhu, %hhu, %hhu, %hhu, %hhu, %hhu, %hhu]\\n\",\n \t\ti,\n \n \t\t/* Token bucket */\n@@ -586,6 +705,11 @@ rte_sched_port_log_pipe_profile(struct rte_sched_port *port, uint32_t i)\n \t\tp->tc_credits_per_period[1],\n \t\tp->tc_credits_per_period[2],\n \t\tp->tc_credits_per_period[3],\n+\t\tp->tc_credits_per_period[4],\n+\t\tp->tc_credits_per_period[5],\n+\t\tp->tc_credits_per_period[6],\n+\t\tp->tc_credits_per_period[7],\n+\t\tp->tc_credits_per_period[8],\n \n \t\t/* Traffic class 3 oversubscription */\n \t\tp->tc_ov_weight,\n@@ -606,7 +730,8 @@ rte_sched_time_ms_to_bytes(uint32_t time_ms, uint32_t rate)\n }\n \n static void\n-rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n+rte_sched_pipe_profile_convert(struct rte_sched_subport *subport,\n+\tstruct rte_sched_pipe_params *src,\n \tstruct rte_sched_pipe_profile *dst,\n \tuint32_t rate)\n {\n@@ -632,40 +757,42 @@ rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n \t\t\t\t\t\trate);\n \n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\tdst->tc_credits_per_period[i]\n-\t\t\t= rte_sched_time_ms_to_bytes(src->tc_period,\n-\t\t\t\tsrc->tc_rate[i]);\n+\t\tif (subport->qsize[i])\n+\t\t\tdst->tc_credits_per_period[i]\n+\t\t\t\t= rte_sched_time_ms_to_bytes(src->tc_period,\n+\t\t\t\t\tsrc->tc_rate[i]);\n \n #ifdef RTE_SCHED_SUBPORT_TC_OV\n \tdst->tc_ov_weight = src->tc_ov_weight;\n #endif\n \n+\trte_sched_pipe_queues_config(subport, dst);\n+\n \t/* WRR */\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tuint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS];\n-\t\tuint32_t lcd, lcd1, lcd2;\n-\t\tuint32_t qindex;\n+\trte_sched_pipe_wrr_queues_config(src, dst);\n+}\n \n-\t\tqindex = i * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS;\n+static void\n+rte_sched_subport_config_pipe_profile_table(struct rte_sched_subport *subport,\n+\tstruct rte_sched_subport_params *params, uint32_t rate)\n+{\n+\tuint32_t i;\n \n-\t\twrr_cost[0] = src->wrr_weights[qindex];\n-\t\twrr_cost[1] = src->wrr_weights[qindex + 1];\n-\t\twrr_cost[2] = src->wrr_weights[qindex + 2];\n-\t\twrr_cost[3] = src->wrr_weights[qindex + 3];\n+\tfor (i = 0; i < subport->n_pipe_profiles; i++) {\n+\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n+\t\tstruct rte_sched_pipe_profile *dst = subport->pipe_profiles + i;\n \n-\t\tlcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]);\n-\t\tlcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]);\n-\t\tlcd = rte_get_lcd(lcd1, lcd2);\n+\t\trte_sched_pipe_profile_convert(subport, src, dst, rate);\n+\t\trte_sched_port_log_pipe_profile(subport, i);\n+\t}\n \n-\t\twrr_cost[0] = lcd / wrr_cost[0];\n-\t\twrr_cost[1] = lcd / wrr_cost[1];\n-\t\twrr_cost[2] = lcd / wrr_cost[2];\n-\t\twrr_cost[3] = lcd / wrr_cost[3];\n+\tsubport->pipe_tc_be_rate_max = 0;\n+\tfor (i = 0; i < subport->n_pipe_profiles; i++) {\n+\t\tstruct rte_sched_pipe_params *src = params->pipe_profiles + i;\n+\t\tuint32_t pipe_tc_be_rate = src->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE];\n \n-\t\tdst->wrr_cost[qindex] = (uint8_t) wrr_cost[0];\n-\t\tdst->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1];\n-\t\tdst->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2];\n-\t\tdst->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3];\n+\t\tif (subport->pipe_tc_be_rate_max < pipe_tc_be_rate)\n+\t\t\tsubport->pipe_tc_be_rate_max = pipe_tc_be_rate;\n \t}\n }\n \n@@ -733,6 +860,15 @@ rte_sched_subport_check_params(struct rte_sched_subport_params *params,\n \t params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_SUBPORT)\n \t\treturn -10;\n \n+\tfor (i = 0; i < params->n_pipe_profiles; i++) {\n+\t\tstruct rte_sched_pipe_params *p = params->pipe_profiles + i;\n+\t\tint status;\n+\n+\t\tstatus = pipe_profile_check(p, rate, ¶ms->qsize[0]);\n+\t\tif (status != 0)\n+\t\t\treturn status;\n+\t}\n+\n \treturn 0;\n }\n \n@@ -1013,6 +1149,9 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t\t(s->memory + rte_sched_subport_get_array_base(params,\n \t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY));\n \n+\t/* Pipe profile table */\n+\trte_sched_subport_config_pipe_profile_table(s, params, port->rate);\n+\n \t/* Bitmap */\n \tn_subport_queues = rte_sched_subport_queues(s);\n \tbmp_mem_size = rte_bitmap_get_memory_footprint(n_subport_queues);\n@@ -1150,10 +1289,12 @@ rte_sched_pipe_config(struct rte_sched_port *port,\n \n int __rte_experimental\n rte_sched_port_pipe_profile_add(struct rte_sched_port *port,\n+\tuint32_t subport_id,\n \tstruct rte_sched_pipe_params *params,\n \tuint32_t *pipe_profile_id)\n {\n \tstruct rte_sched_pipe_profile *pp;\n+\tstruct rte_sched_subport *s;\n \tuint32_t i;\n \tint status;\n \n@@ -1161,31 +1302,37 @@ rte_sched_port_pipe_profile_add(struct rte_sched_port *port,\n \tif (port == NULL)\n \t\treturn -1;\n \n-\t/* Pipe profiles not exceeds the max limit */\n-\tif (port->n_pipe_profiles >= RTE_SCHED_PIPE_PROFILES_PER_PORT)\n+\t/* Subport id not exceeds the max limit */\n+\tif (subport_id > port->n_subports_per_port)\n \t\treturn -2;\n \n+\ts = port->subports[subport_id];\n+\n+\t/* Pipe profiles not exceeds the max limit */\n+\tif (s->n_pipe_profiles >= RTE_SCHED_PIPE_PROFILES_PER_SUBPORT)\n+\t\treturn -3;\n+\n \t/* Pipe params */\n-\tstatus = pipe_profile_check(params, port->rate);\n+\tstatus = pipe_profile_check(params, port->rate, &s->qsize[0]);\n \tif (status != 0)\n \t\treturn status;\n \n-\tpp = &port->pipe_profiles[port->n_pipe_profiles];\n-\trte_sched_pipe_profile_convert(params, pp, port->rate);\n+\tpp = &s->pipe_profiles[s->n_pipe_profiles];\n+\trte_sched_pipe_profile_convert(s, params, pp, port->rate);\n \n \t/* Pipe profile not exists */\n-\tfor (i = 0; i < port->n_pipe_profiles; i++)\n-\t\tif (memcmp(port->pipe_profiles + i, pp, sizeof(*pp)) == 0)\n-\t\t\treturn -3;\n+\tfor (i = 0; i < s->n_pipe_profiles; i++)\n+\t\tif (memcmp(s->pipe_profiles + i, pp, sizeof(*pp)) == 0)\n+\t\t\treturn -4;\n \n \t/* Pipe profile commit */\n-\t*pipe_profile_id = port->n_pipe_profiles;\n-\tport->n_pipe_profiles++;\n+\t*pipe_profile_id = s->n_pipe_profiles;\n+\ts->n_pipe_profiles++;\n \n-\tif (port->pipe_tc3_rate_max < params->tc_rate[3])\n-\t\tport->pipe_tc3_rate_max = params->tc_rate[3];\n+\tif (s->pipe_tc_be_rate_max < params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE])\n+\t\ts->pipe_tc_be_rate_max = params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE];\n \n-\trte_sched_port_log_pipe_profile(port, *pipe_profile_id);\n+\trte_sched_port_log_pipe_profile(s, *pipe_profile_id);\n \n \treturn 0;\n }\ndiff --git a/lib/librte_sched/rte_sched.h b/lib/librte_sched/rte_sched.h\nindex 71728f725..51f801098 100644\n--- a/lib/librte_sched/rte_sched.h\n+++ b/lib/librte_sched/rte_sched.h\n@@ -277,6 +277,8 @@ rte_sched_port_free(struct rte_sched_port *port);\n *\n * @param port\n * Handle to port scheduler instance\n+ * @param subport_id\n+ * Subport ID\n * @param params\n * Pipe profile parameters\n * @param pipe_profile_id\n@@ -286,6 +288,7 @@ rte_sched_port_free(struct rte_sched_port *port);\n */\n int __rte_experimental\n rte_sched_port_pipe_profile_add(struct rte_sched_port *port,\n+\tuint32_t subport_id,\n \tstruct rte_sched_pipe_params *params,\n \tuint32_t *pipe_profile_id);\n \n", "prefixes": [ "07/27" ] }