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GET /api/patches/53740/?format=api
{ "id": 53740, "url": "https://patches.dpdk.org/api/patches/53740/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190528120553.2992-7-lukaszx.krakowiak@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190528120553.2992-7-lukaszx.krakowiak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190528120553.2992-7-lukaszx.krakowiak@intel.com", "date": "2019-05-28T12:05:32", "name": "[06/27] sched: update subport config api", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "efd747011eb8ddbceb0c9b16cf62c48321b19e01", "submitter": { "id": 1221, "url": "https://patches.dpdk.org/api/people/1221/?format=api", "name": "Lukasz Krakowiak", "email": "lukaszx.krakowiak@intel.com" }, "delegate": { "id": 10018, "url": "https://patches.dpdk.org/api/users/10018/?format=api", "username": "cristian_dumitrescu", "first_name": "Cristian", "last_name": "Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190528120553.2992-7-lukaszx.krakowiak@intel.com/mbox/", "series": [ { "id": 4794, "url": "https://patches.dpdk.org/api/series/4794/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=4794", "date": "2019-05-28T12:05:26", "name": "sched: feature enhancements", "version": 1, "mbox": "https://patches.dpdk.org/series/4794/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/53740/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/53740/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E623B1B99C;\n\tTue, 28 May 2019 14:08:24 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id 4337B1B950\n\tfor <dev@dpdk.org>; Tue, 28 May 2019 14:08:16 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 May 2019 05:08:15 -0700", "from lkrakowx-mobl.ger.corp.intel.com ([10.103.104.99])\n\tby fmsmga001.fm.intel.com with ESMTP; 28 May 2019 05:08:14 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Lukasz Krakowiak <lukaszx.krakowiak@intel.com>", "To": "cristian.dumitrescu@intel.com", "Cc": "dev@dpdk.org, Jasvinder Singh <jasvinder.singh@intel.com>,\n\tAbraham Tovar <abrahamx.tovar@intel.com>,\n\tLukasz Krakowiak <lukaszx.krakowiak@intel.com>", "Date": "Tue, 28 May 2019 14:05:32 +0200", "Message-Id": "<20190528120553.2992-7-lukaszx.krakowiak@intel.com>", "X-Mailer": "git-send-email 2.19.2.windows.1", "In-Reply-To": "<20190528120553.2992-1-lukaszx.krakowiak@intel.com>", "References": "<20190528120553.2992-1-lukaszx.krakowiak@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 06/27] sched: update subport config api", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Jasvinder Singh <jasvinder.singh@intel.com>\n\nUpdate suport configuration api implementation of the scheduler to allow\nconfiguration flexiblity for pipe traffic classes and queues, and subport\nlevel configuration of the pipe parameters.\n\nSigned-off-by: Jasvinder Singh <jasvinder.singh@intel.com>\nSigned-off-by: Abraham Tovar <abrahamx.tovar@intel.com>\nSigned-off-by: Lukasz Krakowiak <lukaszx.krakowiak@intel.com>\n---\n lib/librte_sched/rte_sched.c | 325 ++++++++++++++++++++++++++++++-----\n 1 file changed, 283 insertions(+), 42 deletions(-)", "diff": "diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c\nindex 39a6165e3..020c028fd 100644\n--- a/lib/librte_sched/rte_sched.c\n+++ b/lib/librte_sched/rte_sched.c\n@@ -495,24 +495,72 @@ rte_sched_port_get_array_base(struct rte_sched_port_params *params, enum rte_sch\n \treturn base;\n }\n \n-uint32_t\n-rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n+static uint32_t\n+rte_sched_subport_get_array_base(struct rte_sched_subport_params *params,\n+\tenum rte_sched_subport_array array)\n {\n-\tuint32_t size0, size1;\n-\tint status;\n+\tuint32_t n_subport_pipes = params->n_subport_pipes;\n+\tuint32_t n_subport_queues = RTE_SCHED_QUEUES_PER_PIPE * n_subport_pipes;\n \n-\tstatus = rte_sched_port_check_params(params);\n-\tif (status != 0) {\n-\t\tRTE_LOG(NOTICE, SCHED,\n-\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\tuint32_t size_pipe = n_subport_pipes * sizeof(struct rte_sched_pipe);\n+\tuint32_t size_queue = n_subport_queues * sizeof(struct rte_sched_queue);\n+\tuint32_t size_queue_extra\n+\t\t= n_subport_queues * sizeof(struct rte_sched_queue_extra);\n+\tuint32_t size_pipe_profiles = RTE_SCHED_PIPE_PROFILES_PER_SUBPORT *\n+\t\tsizeof(struct rte_sched_pipe_profile);\n+\tuint32_t size_bmp_array =\n+\t\trte_bitmap_get_memory_footprint(n_subport_queues);\n+\tuint32_t size_per_pipe_queue_array, size_queue_array;\n \n-\t\treturn 0;\n+\tuint32_t base, i;\n+\n+\tsize_per_pipe_queue_array = 0;\n+\tfor (i = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++) {\n+\t\tsize_per_pipe_queue_array += params->qsize[i] * sizeof(struct rte_mbuf *);\n \t}\n+\tsize_queue_array = n_subport_pipes * size_per_pipe_queue_array;\n \n-\tsize0 = sizeof(struct rte_sched_port);\n-\tsize1 = rte_sched_port_get_array_base(params, e_RTE_SCHED_PORT_ARRAY_TOTAL);\n+\tbase = 0;\n \n-\treturn size0 + size1;\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_PIPE)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_extra);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_pipe_profiles);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_bmp_array);\n+\n+\tif (array == e_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY)\n+\t\treturn base;\n+\tbase += RTE_CACHE_LINE_ROUNDUP(size_queue_array);\n+\n+\treturn base;\n+}\n+\n+static void\n+rte_sched_subport_config_qsize(struct rte_sched_subport *subport)\n+{\n+\tuint32_t i;\n+\n+\tsubport->qsize_add[0] = 0;\n+\n+\tfor (i = 1; i < RTE_SCHED_QUEUES_PER_PIPE; i++)\n+\t\tsubport->qsize_add[i] =\n+\t\t\tsubport->qsize_add[i-1] + subport->qsize[i-1];\n+\n+\tsubport->qsize_sum = subport->qsize_add[15] + subport->qsize[15];\n }\n \n static void\n@@ -621,6 +669,120 @@ rte_sched_pipe_profile_convert(struct rte_sched_pipe_params *src,\n \t}\n }\n \n+static int\n+rte_sched_subport_check_params(struct rte_sched_subport_params *params,\n+\tuint32_t rate)\n+{\n+\tuint32_t i, j;\n+\n+\t/* Check user parameters */\n+\tif (params == NULL)\n+\t\treturn -1;\n+\n+\tif (params->tb_rate == 0 || params->tb_rate > rate)\n+\t\treturn -2;\n+\n+\tif (params->tb_size == 0)\n+\t\treturn -3;\n+\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n+\t\tif (params->tc_rate[i] > params->tb_rate) {\n+\t\t\tprintf(\"traffic class %u, tc_rate %u, tb_rate %u\\n\", i,\n+\t\t\t\tparams->tc_rate[i], params->tb_rate);\n+\t\t\treturn -4;\n+\t\t}\n+\tif (params->tc_period == 0)\n+\t\treturn -6;\n+\n+\t/* n_subport_pipes: non-zero, power of 2 */\n+\tif (params->n_subport_pipes == 0 ||\n+\t !rte_is_power_of_2(params->n_subport_pipes))\n+\t\treturn -7;\n+\n+\t/* qsize: power of 2, if non-zero\n+\t * no bigger than 32K (due to 16-bit read/write pointers)\n+\t */\n+\tfor (i = 0, j = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++) {\n+\t\tuint32_t tc_rate = params->tc_rate[j];\n+\t\tuint16_t qsize = params->qsize[i];\n+\n+\t\tif (((qsize == 0) &&\n+\t\t\t((tc_rate != 0) &&\n+\t\t\t(j != RTE_SCHED_TRAFFIC_CLASS_BE))) ||\n+\t\t\t((qsize != 0) && !rte_is_power_of_2(qsize)))\n+\t\t\treturn -8;\n+\n+\t\tif (j < RTE_SCHED_TRAFFIC_CLASS_BE)\n+\t\t\tj++;\n+\t}\n+\n+\t/* WRR queues : 1, 4, 8 */\n+\tuint32_t wrr_queues = 0;\n+\tfor (i = 0; i < RTE_SCHED_WRR_QUEUES_PER_PIPE; i++) {\n+\t\tif (params->qsize[RTE_SCHED_TRAFFIC_CLASS_BE + i])\n+\t\t\twrr_queues++;\n+\t}\n+\tif (params->tc_rate[RTE_SCHED_TRAFFIC_CLASS_BE] &&\n+\t\t(wrr_queues != 1 && wrr_queues != 2 &&\n+\t\twrr_queues != 4 && wrr_queues != 8))\n+\t\treturn -9;\n+\n+\t/* pipe_profiles and n_pipe_profiles */\n+\tif (params->pipe_profiles == NULL ||\n+\t params->n_pipe_profiles == 0 ||\n+\t params->n_pipe_profiles > RTE_SCHED_PIPE_PROFILES_PER_SUBPORT)\n+\t\treturn -10;\n+\n+\treturn 0;\n+}\n+\n+static uint32_t\n+rte_sched_subport_get_memory_footprint(struct rte_sched_port *port,\n+\tuint32_t subport_id, struct rte_sched_subport_params *params)\n+{\n+\tuint32_t size0, size1;\n+\tint status;\n+\n+\tif (port == NULL ||\n+\t subport_id >= port->n_subports_per_port)\n+\t\treturn 0;\n+\n+\tstatus = rte_sched_subport_check_params(params, port->rate);\n+\tif (status != 0) {\n+\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tsize0 = sizeof(struct rte_sched_subport);\n+\tsize1 = rte_sched_subport_get_array_base(params,\n+\t\t\te_RTE_SCHED_SUBPORT_ARRAY_TOTAL);\n+\n+\treturn size0 + size1;\n+}\n+\n+uint32_t\n+rte_sched_port_get_memory_footprint(struct rte_sched_port_params *params)\n+{\n+\tuint32_t size0, size1;\n+\tint status;\n+\n+\tstatus = rte_sched_port_check_params(params);\n+\tif (status != 0) {\n+\t\tRTE_LOG(NOTICE, SCHED,\n+\t\t\t\"Port scheduler params check failed (%d)\\n\", status);\n+\n+\t\treturn 0;\n+\t}\n+\n+\tsize0 = sizeof(struct rte_sched_port);\n+\tsize1 = rte_sched_port_get_array_base(params,\n+\t\t\te_RTE_SCHED_PORT_ARRAY_TOTAL);\n+\n+\treturn size0 + size1;\n+}\n+\n struct rte_sched_port *\n rte_sched_port_config(struct rte_sched_port_params *params)\n {\n@@ -710,12 +872,12 @@ rte_sched_port_free(struct rte_sched_port *port)\n static void\n rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)\n {\n-\tstruct rte_sched_subport *s = port->subport + i;\n+\tstruct rte_sched_subport *s = port->subports[i];\n \n \tRTE_LOG(DEBUG, SCHED, \"Low level config for subport %u:\\n\"\n \t\t\" Token bucket: period = %u, credits per period = %u, size = %u\\n\"\n-\t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u]\\n\"\n-\t\t\" Traffic class 3 oversubscription: wm min = %u, wm max = %u\\n\",\n+\t\t\" Traffic classes: period = %u, credits per period = [%u, %u, %u, %u, %u, %u, %u, %u, %u]\\n\"\n+\t\t\" Traffic class BE oversubscription: wm min = %u, wm max = %u\\n\",\n \t\ti,\n \n \t\t/* Token bucket */\n@@ -729,8 +891,13 @@ rte_sched_port_log_subport_config(struct rte_sched_port *port, uint32_t i)\n \t\ts->tc_credits_per_period[1],\n \t\ts->tc_credits_per_period[2],\n \t\ts->tc_credits_per_period[3],\n+\t\ts->tc_credits_per_period[4],\n+\t\ts->tc_credits_per_period[5],\n+\t\ts->tc_credits_per_period[6],\n+\t\ts->tc_credits_per_period[7],\n+\t\ts->tc_credits_per_period[8],\n \n-\t\t/* Traffic class 3 oversubscription */\n+\t\t/* Traffic class BE oversubscription */\n \t\ts->tc_ov_wm_min,\n \t\ts->tc_ov_wm_max);\n }\n@@ -740,32 +907,21 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \tuint32_t subport_id,\n \tstruct rte_sched_subport_params *params)\n {\n-\tstruct rte_sched_subport *s;\n-\tuint32_t i;\n+\tstruct rte_sched_subport *s = NULL;\n+\tuint32_t mem_size, bmp_mem_size, n_subport_queues, n_subport_pipes_log2, i;\n \n-\t/* Check user parameters */\n-\tif (port == NULL ||\n-\t subport_id >= port->n_subports_per_port ||\n-\t params == NULL)\n+\t/* Check user parameters. Determine the amount of memory to allocate */\n+\tmem_size = rte_sched_subport_get_memory_footprint(port,\n+\t\tsubport_id, params);\n+\tif (mem_size == 0)\n \t\treturn -1;\n \n-\tif (params->tb_rate == 0 || params->tb_rate > port->rate)\n+\t/* Allocate memory to store the data structures */\n+\ts = rte_zmalloc_socket(\"subport_params\", mem_size, RTE_CACHE_LINE_SIZE,\n+\t\tport->socket);\n+\tif (s == NULL)\n \t\treturn -2;\n \n-\tif (params->tb_size == 0)\n-\t\treturn -3;\n-\n-\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\tif (params->tc_rate[i] == 0 ||\n-\t\t params->tc_rate[i] > params->tb_rate)\n-\t\t\treturn -4;\n-\t}\n-\n-\tif (params->tc_period == 0)\n-\t\treturn -5;\n-\n-\ts = port->subport + subport_id;\n-\n \t/* Token Bucket (TB) */\n \tif (params->tb_rate == port->rate) {\n \t\ts->tb_credits_per_period = 1;\n@@ -784,19 +940,104 @@ rte_sched_subport_config(struct rte_sched_port *port,\n \t/* Traffic Classes (TCs) */\n \ts->tc_period = rte_sched_time_ms_to_bytes(params->tc_period, port->rate);\n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n-\t\ts->tc_credits_per_period[i]\n-\t\t\t= rte_sched_time_ms_to_bytes(params->tc_period,\n-\t\t\t\t\t\t params->tc_rate[i]);\n+\t\tif (params->qsize[i])\n+\t\t\ts->tc_credits_per_period[i]\n+\t\t\t\t= rte_sched_time_ms_to_bytes(params->tc_period,\n+\t\t\t\t\tparams->tc_rate[i]);\n \t}\n \ts->tc_time = port->time + s->tc_period;\n \tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++)\n-\t\ts->tc_credits[i] = s->tc_credits_per_period[i];\n+\t\tif (params->qsize[i])\n+\t\t\ts->tc_credits[i] = s->tc_credits_per_period[i];\n+\n+\t/* compile time checks */\n+\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS == 0);\n+\tRTE_BUILD_BUG_ON(RTE_SCHED_PORT_N_GRINDERS &\n+\t\t(RTE_SCHED_PORT_N_GRINDERS - 1));\n+\n+\t/* User parameters */\n+\ts->n_subport_pipes = params->n_subport_pipes;\n+\tn_subport_pipes_log2 = __builtin_ctz(params->n_subport_pipes);\n+\tmemcpy(s->qsize, params->qsize, sizeof(params->qsize));\n+\ts->n_pipe_profiles = params->n_pipe_profiles;\n+\n+#ifdef RTE_SCHED_RED\n+\tfor (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) {\n+\t\tuint32_t j;\n+\n+\t\tfor (j = 0; j < RTE_COLORS; j++) {\n+\t\t\t/* if min/max are both zero, then RED is disabled */\n+\t\t\tif ((params->red_params[i][j].min_th |\n+\t\t\t params->red_params[i][j].max_th) == 0) {\n+\t\t\t\tcontinue;\n+\t\t\t}\n+\n+\t\t\tif (rte_red_config_init(&s->red_config[i][j],\n+\t\t\t\tparams->red_params[i][j].wq_log2,\n+\t\t\t\tparams->red_params[i][j].min_th,\n+\t\t\t\tparams->red_params[i][j].max_th,\n+\t\t\t\tparams->red_params[i][j].maxp_inv) != 0) {\n+\t\t\t\trte_free(s);\n+\t\t\t\treturn -3;\n+\t\t\t}\n+\t\t}\n+\t}\n+#endif\n+\n+\t/* Scheduling loop detection */\n+\ts->pipe_loop = RTE_SCHED_PIPE_INVALID;\n+\ts->pipe_exhaustion = 0;\n+\n+\t/* Grinders */\n+\ts->busy_grinders = 0;\n+\n+\t/* Queue base calculation */\n+\trte_sched_subport_config_qsize(s);\n+\n+\t/* Large data structures */\n+\ts->pipe = (struct rte_sched_pipe *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_PIPE));\n+\ts->queue = (struct rte_sched_queue *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE));\n+\ts->queue_extra = (struct rte_sched_queue_extra *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_EXTRA));\n+\ts->pipe_profiles = (struct rte_sched_pipe_profile *)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_PIPE_PROFILES));\n+\ts->bmp_array = s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_BMP_ARRAY);\n+\ts->queue_array = (struct rte_mbuf **)\n+\t\t(s->memory + rte_sched_subport_get_array_base(params,\n+\t\t\t\t\t\te_RTE_SCHED_SUBPORT_ARRAY_QUEUE_ARRAY));\n+\n+\t/* Bitmap */\n+\tn_subport_queues = rte_sched_subport_queues(s);\n+\tbmp_mem_size = rte_bitmap_get_memory_footprint(n_subport_queues);\n+\ts->bmp = rte_bitmap_init(n_subport_queues, s->bmp_array,\n+\t\t\t\tbmp_mem_size);\n+\tif (s->bmp == NULL) {\n+\t\tRTE_LOG(ERR, SCHED, \"Subport bitmap init error\\n\");\n+\t\trte_free(port);\n+\t\treturn -4;\n+\t}\n+\n+\tfor (i = 0; i < RTE_SCHED_PORT_N_GRINDERS; i++)\n+\t\ts->grinder_base_bmp_pos[i] = RTE_SCHED_PIPE_INVALID;\n+\n+\t/* Port */\n+\tport->subports[subport_id] = s;\n+\n+\tif (n_subport_pipes_log2 > port->n_max_subport_pipes_log2)\n+\t\tport->n_max_subport_pipes_log2 = n_subport_pipes_log2;\n \n #ifdef RTE_SCHED_SUBPORT_TC_OV\n \t/* TC oversubscription */\n \ts->tc_ov_wm_min = port->mtu;\n \ts->tc_ov_wm_max = rte_sched_time_ms_to_bytes(params->tc_period,\n-\t\t\t\t\t\t port->pipe_tc3_rate_max);\n+\t\t\t\t\t\t s->pipe_tc_be_rate_max);\n \ts->tc_ov_wm = s->tc_ov_wm_max;\n \ts->tc_ov_period_id = 0;\n \ts->tc_ov = 0;\n", "prefixes": [ "06/27" ] }