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GET /api/patches/521/?format=api
{ "id": 521, "url": "https://patches.dpdk.org/api/patches/521/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411654744-9460-13-git-send-email-changchun.ouyang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411654744-9460-13-git-send-email-changchun.ouyang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411654744-9460-13-git-send-email-changchun.ouyang@intel.com", "date": "2014-09-25T14:18:58", "name": "[dpdk-dev,12/18] ixgbe: Use hardware MAC type for I2C control", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "fea780b0edaf2350feccabff59a0d29a0bd6d19a", "submitter": { "id": 31, "url": "https://patches.dpdk.org/api/people/31/?format=api", "name": "Ouyang Changchun", "email": "changchun.ouyang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411654744-9460-13-git-send-email-changchun.ouyang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/521/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/521/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 74EBAB421;\n\tThu, 25 Sep 2014 16:13:34 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id CEE81B436\n\tfor <dev@dpdk.org>; Thu, 25 Sep 2014 16:13:32 +0200 (CEST)", "from azsmga001.ch.intel.com ([10.2.17.19])\n\tby fmsmga102.fm.intel.com with ESMTP; 25 Sep 2014 07:19:49 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby azsmga001.ch.intel.com with ESMTP; 25 Sep 2014 07:19:38 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8PEJa73027934;\n\tThu, 25 Sep 2014 22:19:36 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8PEJYwv009577; Thu, 25 Sep 2014 22:19:36 +0800", "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8PEJY3o009573; \n\tThu, 25 Sep 2014 22:19:34 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,597,1406617200\"; d=\"scan'208\";a=\"479955705\"", "From": "Ouyang Changchun <changchun.ouyang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 25 Sep 2014 22:18:58 +0800", "Message-Id": "<1411654744-9460-13-git-send-email-changchun.ouyang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411654744-9460-1-git-send-email-changchun.ouyang@intel.com>", "References": "<1411654744-9460-1-git-send-email-changchun.ouyang@intel.com>", "Subject": "[dpdk-dev] [PATCH 12/18] ixgbe: Use hardware MAC type for I2C\n\tcontrol", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch uses hardware MAC type to determine I2C control, clock \nin/out, and data in/out in IXGBE base code.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c | 58 ++++++++++++++++-----------------\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 12 ++++---\n 2 files changed, 37 insertions(+), 33 deletions(-)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\nindex 462e884..2e8fe93 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n@@ -2075,7 +2075,7 @@ write_byte_out:\n **/\n STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)\n {\n-\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n+\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n \n \tDEBUGFUNC(\"ixgbe_i2c_start\");\n \n@@ -2106,7 +2106,7 @@ STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)\n **/\n STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)\n {\n-\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n+\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n \n \tDEBUGFUNC(\"ixgbe_i2c_stop\");\n \n@@ -2170,9 +2170,9 @@ STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)\n \t}\n \n \t/* Release SDA line (set high) */\n-\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n-\ti2cctl |= IXGBE_I2C_DATA_OUT;\n-\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);\n+\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n+\ti2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);\n+\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);\n \tIXGBE_WRITE_FLUSH(hw);\n \n \treturn status;\n@@ -2188,7 +2188,7 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)\n {\n \ts32 status = IXGBE_SUCCESS;\n \tu32 i = 0;\n-\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n+\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n \tu32 timeout = 10;\n \tbool ack = 1;\n \n@@ -2203,17 +2203,16 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)\n \t/* Poll for ACK. Note that ACK in I2C spec is\n \t * transition from 1 to 0 */\n \tfor (i = 0; i < timeout; i++) {\n-\t\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n-\t\tack = ixgbe_get_i2c_data(&i2cctl);\n+\t\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n+\t\tack = ixgbe_get_i2c_data(hw, &i2cctl);\n \n \t\tusec_delay(1);\n \t\tif (!ack)\n \t\t\tbreak;\n \t}\n \n-\tif (ack == 1) {\n-\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n-\t\t\t \"I2C ack was not received.\\n\");\n+\tif (ack) {\n+\t\tDEBUGOUT(\"I2C ack was not received.\\n\");\n \t\tstatus = IXGBE_ERR_I2C;\n \t}\n \n@@ -2234,7 +2233,7 @@ STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)\n **/\n STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)\n {\n-\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n+\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n \n \tDEBUGFUNC(\"ixgbe_clock_in_i2c_bit\");\n \n@@ -2243,8 +2242,8 @@ STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)\n \t/* Minimum high period of clock is 4us */\n \tusec_delay(IXGBE_I2C_T_HIGH);\n \n-\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n-\t*data = ixgbe_get_i2c_data(&i2cctl);\n+\ti2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n+\t*data = ixgbe_get_i2c_data(hw, &i2cctl);\n \n \tixgbe_lower_i2c_clk(hw, &i2cctl);\n \n@@ -2264,7 +2263,7 @@ STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)\n STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)\n {\n \ts32 status;\n-\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n+\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n \n \tDEBUGFUNC(\"ixgbe_clock_out_i2c_bit\");\n \n@@ -2306,15 +2305,15 @@ STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n \tDEBUGFUNC(\"ixgbe_raise_i2c_clk\");\n \n \tfor (i = 0; i < timeout; i++) {\n-\t\t*i2cctl |= IXGBE_I2C_CLK_OUT;\n+\t\t*i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);\n \n-\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n \t\tIXGBE_WRITE_FLUSH(hw);\n \t\t/* SCL rise time (1000ns) */\n \t\tusec_delay(IXGBE_I2C_T_RISE);\n \n-\t\ti2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n-\t\tif (i2cctl_r & IXGBE_I2C_CLK_IN)\n+\t\ti2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n+\t\tif (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))\n \t\t\tbreak;\n \t}\n }\n@@ -2331,9 +2330,9 @@ STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)\n \n \tDEBUGFUNC(\"ixgbe_lower_i2c_clk\");\n \n-\t*i2cctl &= ~IXGBE_I2C_CLK_OUT;\n+\t*i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));\n \n-\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);\n+\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n \tIXGBE_WRITE_FLUSH(hw);\n \n \t/* SCL fall time (300ns) */\n@@ -2355,19 +2354,19 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)\n \tDEBUGFUNC(\"ixgbe_set_i2c_data\");\n \n \tif (data)\n-\t\t*i2cctl |= IXGBE_I2C_DATA_OUT;\n+\t\t*i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);\n \telse\n-\t\t*i2cctl &= ~IXGBE_I2C_DATA_OUT;\n+\t\t*i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));\n \n-\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);\n+\tIXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);\n \tIXGBE_WRITE_FLUSH(hw);\n \n \t/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */\n \tusec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);\n \n \t/* Verify data was set correctly */\n-\t*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n-\tif (data != ixgbe_get_i2c_data(i2cctl)) {\n+\t*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n+\tif (data != ixgbe_get_i2c_data(hw, i2cctl)) {\n \t\tstatus = IXGBE_ERR_I2C;\n \t\tERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,\n \t\t\t \"Error - I2C data was not set to %X.\\n\",\n@@ -2384,13 +2383,14 @@ STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)\n *\n * Returns the I2C data bit value\n **/\n-STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)\n+STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)\n {\n \tbool data;\n+\tUNREFERENCED_1PARAMETER(hw);\n \n \tDEBUGFUNC(\"ixgbe_get_i2c_data\");\n \n-\tif (*i2cctl & IXGBE_I2C_DATA_IN)\n+\tif (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))\n \t\tdata = 1;\n \telse\n \t\tdata = 0;\n@@ -2407,7 +2407,7 @@ STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)\n **/\n void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)\n {\n-\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);\n+\tu32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));\n \tu32 i;\n \n \tDEBUGFUNC(\"ixgbe_i2c_bus_clear\");\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\nindex bfe1235..48f25d1 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n@@ -171,10 +171,14 @@ POSSIBILITY OF SUCH DAMAGE.\n #define IXGBE_VPDDIAG1\t0x10208\n \n /* I2CCTL Bit Masks */\n-#define IXGBE_I2C_CLK_IN\t0x00000001\n-#define IXGBE_I2C_CLK_OUT\t0x00000002\n-#define IXGBE_I2C_DATA_IN\t0x00000004\n-#define IXGBE_I2C_DATA_OUT\t0x00000008\n+#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \\\n+\t\t\t\t\t0x00004000 : 0x00000001)\n+#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \\\n+\t\t\t\t\t0x00000200 : 0x00000002)\n+#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \\\n+\t\t\t\t\t0x00001000 : 0x00000004)\n+#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \\\n+\t\t\t\t\t0x00000400 : 0x00000008)\n #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT\t500\n \n \n", "prefixes": [ "dpdk-dev", "12/18" ] }