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GET /api/patches/51599/?format=api
{ "id": 51599, "url": "https://patches.dpdk.org/api/patches/51599/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1553493995-29803-6-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1553493995-29803-6-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1553493995-29803-6-git-send-email-wenzhuo.lu@intel.com", "date": "2019-03-25T06:06:32", "name": "[v6,5/8] net/ice: support Tx SSE vector", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "accefc2988e8cf326a4909f5254799b89e45818b", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1553493995-29803-6-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 3887, "url": "https://patches.dpdk.org/api/series/3887/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=3887", "date": "2019-03-25T06:06:28", "name": "Support vector instructions on ICE", "version": 6, "mbox": "https://patches.dpdk.org/series/3887/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/51599/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/51599/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C128D4F91;\n\tMon, 25 Mar 2019 07:01:26 +0100 (CET)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id A68D644C3\n\tfor <dev@dpdk.org>; Mon, 25 Mar 2019 07:01:10 +0100 (CET)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t24 Mar 2019 23:01:09 -0700", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby fmsmga002.fm.intel.com with ESMTP; 24 Mar 2019 23:01:09 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.60,256,1549958400\"; d=\"scan'208\";a=\"154850732\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "Date": "Mon, 25 Mar 2019 14:06:32 +0800", "Message-Id": "<1553493995-29803-6-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1553493995-29803-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1551340136-83843-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1553493995-29803-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v6 5/8] net/ice: support Tx SSE vector", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\n---\n doc/guides/nics/features/ice_vec.ini | 2 +\n drivers/net/ice/ice_rxtx.c | 17 +++++\n drivers/net/ice/ice_rxtx.h | 4 +\n drivers/net/ice/ice_rxtx_vec_common.h | 133 +++++++++++++++++++++++++++++++++\n drivers/net/ice/ice_rxtx_vec_sse.c | 135 ++++++++++++++++++++++++++++++++++\n 5 files changed, 291 insertions(+)", "diff": "diff --git a/doc/guides/nics/features/ice_vec.ini b/doc/guides/nics/features/ice_vec.ini\nindex 1a19788..173c8f2 100644\n--- a/doc/guides/nics/features/ice_vec.ini\n+++ b/doc/guides/nics/features/ice_vec.ini\n@@ -12,6 +12,7 @@ Queue start/stop = Y\n MTU update = Y\n Jumbo frame = Y\n Scattered Rx = Y\n+TSO = Y\n Promiscuous mode = Y\n Allmulticast mode = Y\n Unicast MAC filter = Y\n@@ -22,6 +23,7 @@ RSS reta update = Y\n VLAN filter = Y\n Packet type parsing = Y\n Rx descriptor status = Y\n+Tx descriptor status = Y\n Basic stats = Y\n Extended stats = Y\n FW version = Y\ndiff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c\nindex 5409dd0..f9ecffa 100644\n--- a/drivers/net/ice/ice_rxtx.c\n+++ b/drivers/net/ice/ice_rxtx.c\n@@ -2332,6 +2332,23 @@ void __attribute__((cold))\n {\n \tstruct ice_adapter *ad =\n \t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+#ifdef RTE_ARCH_X86\n+\tstruct ice_tx_queue *txq;\n+\tint i;\n+\n+\tif (!ice_tx_vec_dev_check(dev)) {\n+\t\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\t\ttxq = dev->data->tx_queues[i];\n+\t\t\t(void)ice_txq_vec_setup(txq);\n+\t\t}\n+\t\tPMD_DRV_LOG(DEBUG, \"Using Vector Tx (port %d).\",\n+\t\t\t dev->data->port_id);\n+\t\tdev->tx_pkt_burst = ice_xmit_pkts_vec;\n+\t\tdev->tx_pkt_prepare = NULL;\n+\n+\t\treturn;\n+\t}\n+#endif\n \n \tif (ad->tx_simple_allowed) {\n \t\tPMD_INIT_LOG(DEBUG, \"Simple tx finally be used.\");\ndiff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h\nindex 6ef0a84..1dde4e7 100644\n--- a/drivers/net/ice/ice_rxtx.h\n+++ b/drivers/net/ice/ice_rxtx.h\n@@ -170,9 +170,13 @@ void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);\n \n int ice_rx_vec_dev_check(struct rte_eth_dev *dev);\n+int ice_tx_vec_dev_check(struct rte_eth_dev *dev);\n int ice_rxq_vec_setup(struct ice_rx_queue *rxq);\n+int ice_txq_vec_setup(struct ice_tx_queue *txq);\n uint16_t ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t uint16_t nb_pkts);\n uint16_t ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,\n \t\t\t\t uint16_t nb_pkts);\n+uint16_t ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts);\n #endif /* _ICE_RXTX_H_ */\ndiff --git a/drivers/net/ice/ice_rxtx_vec_common.h b/drivers/net/ice/ice_rxtx_vec_common.h\nindex d41232d..c5f0d56 100644\n--- a/drivers/net/ice/ice_rxtx_vec_common.h\n+++ b/drivers/net/ice/ice_rxtx_vec_common.h\n@@ -71,6 +71,73 @@\n \treturn pkt_idx;\n }\n \n+static __rte_always_inline int\n+ice_tx_free_bufs(struct ice_tx_queue *txq)\n+{\n+\tstruct ice_tx_entry *txep;\n+\tuint32_t n;\n+\tuint32_t i;\n+\tint nb_free = 0;\n+\tstruct rte_mbuf *m, *free[ICE_TX_MAX_FREE_BUF_SZ];\n+\n+\t/* check DD bits on threshold descriptor */\n+\tif ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &\n+\t\t\trte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=\n+\t\t\trte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))\n+\t\treturn 0;\n+\n+\tn = txq->tx_rs_thresh;\n+\n+\t /* first buffer to free from S/W ring is at index\n+\t * tx_next_dd - (tx_rs_thresh-1)\n+\t */\n+\ttxep = &txq->sw_ring[txq->tx_next_dd - (n - 1)];\n+\tm = rte_pktmbuf_prefree_seg(txep[0].mbuf);\n+\tif (likely(m)) {\n+\t\tfree[0] = m;\n+\t\tnb_free = 1;\n+\t\tfor (i = 1; i < n; i++) {\n+\t\t\tm = rte_pktmbuf_prefree_seg(txep[i].mbuf);\n+\t\t\tif (likely(m)) {\n+\t\t\t\tif (likely(m->pool == free[0]->pool)) {\n+\t\t\t\t\tfree[nb_free++] = m;\n+\t\t\t\t} else {\n+\t\t\t\t\trte_mempool_put_bulk(free[0]->pool,\n+\t\t\t\t\t\t\t (void *)free,\n+\t\t\t\t\t\t\t nb_free);\n+\t\t\t\t\tfree[0] = m;\n+\t\t\t\t\tnb_free = 1;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\trte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);\n+\t} else {\n+\t\tfor (i = 1; i < n; i++) {\n+\t\t\tm = rte_pktmbuf_prefree_seg(txep[i].mbuf);\n+\t\t\tif (m)\n+\t\t\t\trte_mempool_put(m->pool, m);\n+\t\t}\n+\t}\n+\n+\t/* buffers were freed, update counters */\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);\n+\ttxq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);\n+\tif (txq->tx_next_dd >= txq->nb_tx_desc)\n+\t\ttxq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);\n+\n+\treturn txq->tx_rs_thresh;\n+}\n+\n+static __rte_always_inline void\n+ice_tx_backlog_entry(struct ice_tx_entry *txep,\n+\t\t struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < (int)nb_pkts; ++i)\n+\t\ttxep[i].mbuf = tx_pkts[i];\n+}\n+\n static inline void\n _ice_rx_queue_release_mbufs_vec(struct ice_rx_queue *rxq)\n {\n@@ -106,6 +173,34 @@\n \tmemset(rxq->sw_ring, 0, sizeof(rxq->sw_ring[0]) * rxq->nb_rx_desc);\n }\n \n+static inline void\n+_ice_tx_queue_release_mbufs_vec(struct ice_tx_queue *txq)\n+{\n+\tuint16_t i;\n+\n+\tif (unlikely(!txq || !txq->sw_ring)) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Pointer to rxq or sw_ring is NULL\");\n+\t\treturn;\n+\t}\n+\n+\t/**\n+\t * vPMD tx will not set sw_ring's mbuf to NULL after free,\n+\t * so need to free remains more carefully.\n+\t */\n+\ti = txq->tx_next_dd - txq->tx_rs_thresh + 1;\n+\tif (txq->tx_tail < i) {\n+\t\tfor (; i < txq->nb_tx_desc; i++) {\n+\t\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n+\t\t\ttxq->sw_ring[i].mbuf = NULL;\n+\t\t}\n+\t\ti = 0;\n+\t}\n+\tfor (; i < txq->tx_tail; i++) {\n+\t\trte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);\n+\t\ttxq->sw_ring[i].mbuf = NULL;\n+\t}\n+}\n+\n static inline int\n ice_rxq_vec_setup_default(struct ice_rx_queue *rxq)\n {\n@@ -142,6 +237,29 @@\n \treturn 0;\n }\n \n+#define ICE_NO_VECTOR_FLAGS (\t\t\t\t \\\n+\t\tDEV_TX_OFFLOAD_MULTI_SEGS |\t\t \\\n+\t\tDEV_TX_OFFLOAD_VLAN_INSERT |\t\t \\\n+\t\tDEV_TX_OFFLOAD_SCTP_CKSUM |\t\t \\\n+\t\tDEV_TX_OFFLOAD_UDP_CKSUM |\t\t \\\n+\t\tDEV_TX_OFFLOAD_TCP_CKSUM)\n+\n+static inline int\n+ice_tx_vec_queue_default(struct ice_tx_queue *txq)\n+{\n+\tif (!txq)\n+\t\treturn -1;\n+\n+\tif (txq->offloads & ICE_NO_VECTOR_FLAGS)\n+\t\treturn -1;\n+\n+\tif (txq->tx_rs_thresh < ICE_VPMD_TX_BURST ||\n+\t txq->tx_rs_thresh > ICE_TX_MAX_FREE_BUF_SZ)\n+\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n static inline int\n ice_rx_vec_dev_check_default(struct rte_eth_dev *dev)\n {\n@@ -157,4 +275,19 @@\n \treturn 0;\n }\n \n+static inline int\n+ice_tx_vec_dev_check_default(struct rte_eth_dev *dev)\n+{\n+\tint i;\n+\tstruct ice_tx_queue *txq;\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\tif (ice_tx_vec_queue_default(txq))\n+\t\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n #endif\ndiff --git a/drivers/net/ice/ice_rxtx_vec_sse.c b/drivers/net/ice/ice_rxtx_vec_sse.c\nindex 639dc86..3acfaaf 100644\n--- a/drivers/net/ice/ice_rxtx_vec_sse.c\n+++ b/drivers/net/ice/ice_rxtx_vec_sse.c\n@@ -514,12 +514,131 @@\n \t\t\t\t\t &split_flags[i]);\n }\n \n+static inline void\n+ice_vtx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf *pkt,\n+\t uint64_t flags)\n+{\n+\tuint64_t high_qw =\n+\t\t(ICE_TX_DESC_DTYPE_DATA |\n+\t\t ((uint64_t)flags << ICE_TXD_QW1_CMD_S) |\n+\t\t ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));\n+\n+\t__m128i descriptor = _mm_set_epi64x(high_qw,\n+\t\t\t\t\t pkt->buf_iova + pkt->data_off);\n+\t_mm_store_si128((__m128i *)txdp, descriptor);\n+}\n+\n+static inline void\n+ice_vtx(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkt,\n+\tuint16_t nb_pkts, uint64_t flags)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)\n+\t\tice_vtx1(txdp, *pkt, flags);\n+}\n+\n+static uint16_t\n+ice_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t\t uint16_t nb_pkts)\n+{\n+\tstruct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;\n+\tvolatile struct ice_tx_desc *txdp;\n+\tstruct ice_tx_entry *txep;\n+\tuint16_t n, nb_commit, tx_id;\n+\tuint64_t flags = ICE_TD_CMD;\n+\tuint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;\n+\tint i;\n+\n+\t/* cross rx_thresh boundary is not allowed */\n+\tnb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\n+\tif (txq->nb_tx_free < txq->tx_free_thresh)\n+\t\tice_tx_free_bufs(txq);\n+\n+\tnb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);\n+\tnb_commit = nb_pkts;\n+\tif (unlikely(nb_pkts == 0))\n+\t\treturn 0;\n+\n+\ttx_id = txq->tx_tail;\n+\ttxdp = &txq->tx_ring[tx_id];\n+\ttxep = &txq->sw_ring[tx_id];\n+\n+\ttxq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);\n+\n+\tn = (uint16_t)(txq->nb_tx_desc - tx_id);\n+\tif (nb_commit >= n) {\n+\t\tice_tx_backlog_entry(txep, tx_pkts, n);\n+\n+\t\tfor (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)\n+\t\t\tice_vtx1(txdp, *tx_pkts, flags);\n+\n+\t\tice_vtx1(txdp, *tx_pkts++, rs);\n+\n+\t\tnb_commit = (uint16_t)(nb_commit - n);\n+\n+\t\ttx_id = 0;\n+\t\ttxq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);\n+\n+\t\t/* avoid reach the end of ring */\n+\t\ttxdp = &txq->tx_ring[tx_id];\n+\t\ttxep = &txq->sw_ring[tx_id];\n+\t}\n+\n+\tice_tx_backlog_entry(txep, tx_pkts, nb_commit);\n+\n+\tice_vtx(txdp, tx_pkts, nb_commit, flags);\n+\n+\ttx_id = (uint16_t)(tx_id + nb_commit);\n+\tif (tx_id > txq->tx_next_rs) {\n+\t\ttxq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=\n+\t\t\trte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<\n+\t\t\t\t\t ICE_TXD_QW1_CMD_S);\n+\t\ttxq->tx_next_rs =\n+\t\t\t(uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);\n+\t}\n+\n+\ttxq->tx_tail = tx_id;\n+\n+\tICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);\n+\n+\treturn nb_pkts;\n+}\n+\n+uint16_t\n+ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\t uint16_t nb_pkts)\n+{\n+\tuint16_t nb_tx = 0;\n+\tstruct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;\n+\n+\twhile (nb_pkts) {\n+\t\tuint16_t ret, num;\n+\n+\t\tnum = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);\n+\t\tret = ice_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);\n+\t\tnb_tx += ret;\n+\t\tnb_pkts -= ret;\n+\t\tif (ret < num)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn nb_tx;\n+}\n+\n static void __attribute__((cold))\n ice_rx_queue_release_mbufs_vec(struct ice_rx_queue *rxq)\n {\n \t_ice_rx_queue_release_mbufs_vec(rxq);\n }\n \n+static void __attribute__((cold))\n+ice_tx_queue_release_mbufs_vec(struct ice_tx_queue *txq)\n+{\n+\t_ice_tx_queue_release_mbufs_vec(txq);\n+}\n+\n int __attribute__((cold))\n ice_rxq_vec_setup(struct ice_rx_queue *rxq)\n {\n@@ -531,7 +650,23 @@ int __attribute__((cold))\n }\n \n int __attribute__((cold))\n+ice_txq_vec_setup(struct ice_tx_queue __rte_unused *txq)\n+{\n+\tif (!txq)\n+\t\treturn -1;\n+\n+\ttxq->tx_rel_mbufs = ice_tx_queue_release_mbufs_vec;\n+\treturn 0;\n+}\n+\n+int __attribute__((cold))\n ice_rx_vec_dev_check(struct rte_eth_dev *dev)\n {\n \treturn ice_rx_vec_dev_check_default(dev);\n }\n+\n+int __attribute__((cold))\n+ice_tx_vec_dev_check(struct rte_eth_dev *dev)\n+{\n+\treturn ice_tx_vec_dev_check_default(dev);\n+}\n", "prefixes": [ "v6", "5/8" ] }