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GET /api/patches/513/?format=api
{ "id": 513, "url": "https://patches.dpdk.org/api/patches/513/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411654744-9460-8-git-send-email-changchun.ouyang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411654744-9460-8-git-send-email-changchun.ouyang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411654744-9460-8-git-send-email-changchun.ouyang@intel.com", "date": "2014-09-25T14:18:53", "name": "[dpdk-dev,07/18] ixgbe: Extend mask for SWFW semaphore", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b64bc8b194481d3790b0acbc28174058e903bdc9", "submitter": { "id": 31, "url": "https://patches.dpdk.org/api/people/31/?format=api", "name": "Ouyang Changchun", "email": "changchun.ouyang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411654744-9460-8-git-send-email-changchun.ouyang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/513/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/513/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 1A875B410;\n\tThu, 25 Sep 2014 16:13:14 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby dpdk.org (Postfix) with ESMTP id 6C028B407\n\tfor <dev@dpdk.org>; Thu, 25 Sep 2014 16:13:11 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga103.jf.intel.com with ESMTP; 25 Sep 2014 07:17:28 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 25 Sep 2014 07:19:27 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8PEJP5r027868;\n\tThu, 25 Sep 2014 22:19:25 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8PEJNFV009542; Thu, 25 Sep 2014 22:19:25 +0800", "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8PEJNJl009538; \n\tThu, 25 Sep 2014 22:19:23 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,597,1406617200\"; d=\"scan'208\";a=\"578890966\"", "From": "Ouyang Changchun <changchun.ouyang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 25 Sep 2014 22:18:53 +0800", "Message-Id": "<1411654744-9460-8-git-send-email-changchun.ouyang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411654744-9460-1-git-send-email-changchun.ouyang@intel.com>", "References": "<1411654744-9460-1-git-send-email-changchun.ouyang@intel.com>", "Subject": "[dpdk-dev] [PATCH 07/18] ixgbe: Extend mask for SWFW semaphore", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch extend mask from 16 bits to 32 bits for releasing or \nacquiring SWFW semaphore in IXGBE base code. It is used in reading and \nwriting I2C byte.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c | 4 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h | 4 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c | 4 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h | 4 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c | 32 +++------\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 4 +-\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c | 108 ++++++++++++++++++------------\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h | 4 +-\n 8 files changed, 88 insertions(+), 76 deletions(-)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\nindex 7e6b092..378304f 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c\n@@ -1178,7 +1178,7 @@ s32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw)\n * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n-s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)\n+s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n {\n \treturn ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync,\n \t\t\t (hw, mask), IXGBE_NOT_IMPLEMENTED);\n@@ -1192,7 +1192,7 @@ s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)\n * Releases the SWFW semaphore through SW_FW_SYNC register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n-void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask)\n+void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask)\n {\n \tif (hw->mac.ops.release_swfw_sync)\n \t\thw->mac.ops.release_swfw_sync(hw, mask);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\nindex da41d95..88a31e8 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.h\n@@ -172,8 +172,8 @@ s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);\n s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);\n s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);\n s32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps);\n-s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);\n-void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u16 mask);\n+s32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);\n+void ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask);\n s32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix,\n \t\t\t u16 *wwpn_prefix);\n s32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\nindex f8f4e7e..749188d 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c\n@@ -3172,7 +3172,7 @@ out:\n * Acquires the SWFW semaphore through the GSSR register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)\n+s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n {\n \tu32 gssr = 0;\n \tu32 swmask = mask;\n@@ -3219,7 +3219,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)\n * Releases the SWFW semaphore through the GSSR register for the specified\n * function (CSR, PHY0, PHY1, EEPROM, Flash)\n **/\n-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)\n+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)\n {\n \tu32 gssr;\n \tu32 swmask = mask;\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h\nindex 8b8bd0b..14f1fec 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h\n@@ -114,8 +114,8 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw);\n void ixgbe_fc_autoneg(struct ixgbe_hw *hw);\n \n s32 ixgbe_validate_mac_addr(u8 *mac_addr);\n-s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask);\n-void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask);\n+s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask);\n+void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask);\n s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);\n \n s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *, u32 *reg_val);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\nindex 4271f70..4351f4f 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c\n@@ -1510,26 +1510,18 @@ s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,\n s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\t\tu8 dev_addr, u8 *data)\n {\n-\ts32 status = IXGBE_SUCCESS;\n+\ts32 status;\n \tu32 max_retry = 10;\n \tu32 retry = 0;\n-\tu16 swfw_mask = 0;\n+\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n \tbool nack = 1;\n \t*data = 0;\n \n \tDEBUGFUNC(\"ixgbe_read_i2c_byte_generic\");\n \n-\tif (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)\n-\t\tswfw_mask = IXGBE_GSSR_PHY1_SM;\n-\telse\n-\t\tswfw_mask = IXGBE_GSSR_PHY0_SM;\n-\n \tdo {\n-\t\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)\n-\t\t != IXGBE_SUCCESS) {\n-\t\t\tstatus = IXGBE_ERR_SWFW_SYNC;\n-\t\t\tgoto read_byte_out;\n-\t\t}\n+\t\tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))\n+\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n \n \t\tixgbe_i2c_start(hw);\n \n@@ -1570,7 +1562,8 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\tgoto fail;\n \n \t\tixgbe_i2c_stop(hw);\n-\t\tbreak;\n+\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\t\treturn IXGBE_SUCCESS;\n \n fail:\n \t\tixgbe_i2c_bus_clear(hw);\n@@ -1584,9 +1577,6 @@ fail:\n \n \t} while (retry < max_retry);\n \n-\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n-\n-read_byte_out:\n \treturn status;\n }\n \n@@ -1605,15 +1595,10 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \ts32 status = IXGBE_SUCCESS;\n \tu32 max_retry = 1;\n \tu32 retry = 0;\n-\tu16 swfw_mask = 0;\n+\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n \n \tDEBUGFUNC(\"ixgbe_write_i2c_byte_generic\");\n \n-\tif (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)\n-\t\tswfw_mask = IXGBE_GSSR_PHY1_SM;\n-\telse\n-\t\tswfw_mask = IXGBE_GSSR_PHY0_SM;\n-\n \tif (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {\n \t\tstatus = IXGBE_ERR_SWFW_SYNC;\n \t\tgoto write_byte_out;\n@@ -1647,7 +1632,8 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,\n \t\t\tgoto fail;\n \n \t\tixgbe_i2c_stop(hw);\n-\t\tbreak;\n+\t\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\t\treturn IXGBE_SUCCESS;\n \n fail:\n \t\tixgbe_i2c_bus_clear(hw);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\nindex b266e94..89543c0 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n@@ -3101,8 +3101,8 @@ struct ixgbe_mac_operations {\n \ts32 (*enable_rx_dma)(struct ixgbe_hw *, u32);\n \ts32 (*disable_sec_rx_path)(struct ixgbe_hw *);\n \ts32 (*enable_sec_rx_path)(struct ixgbe_hw *);\n-\ts32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);\n-\tvoid (*release_swfw_sync)(struct ixgbe_hw *, u16);\n+\ts32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);\n+\tvoid (*release_swfw_sync)(struct ixgbe_hw *, u32);\n \ts32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);\n \ts32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);\n \ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c\nindex 9cecd29..e47fb1d 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c\n@@ -737,6 +737,26 @@ STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)\n }\n \n /**\n+ * ixgbe_set_mux - Set mux for port 1 access with CS4227\n+ * @hw: pointer to hardware structure\n+ * @state: set mux if 1, clear if 0\n+ */\n+STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)\n+{\n+\tu32 esdp;\n+\n+\tif (!hw->phy.lan_id)\n+\t\treturn;\n+\tesdp = IXGBE_READ_REG(hw, IXGBE_ESDP);\n+\tif (state)\n+\t\tesdp |= IXGBE_ESDP_SDP1;\n+\telse\n+\t\tesdp &= ~IXGBE_ESDP_SDP1;\n+\tIXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);\n+\tIXGBE_WRITE_FLUSH(hw);\n+}\n+\n+/**\n * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore\n * @hw: pointer to hardware structure\n * @mask: Mask to specify which semaphore to acquire\n@@ -744,34 +764,33 @@ STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)\n * Acquires the SWFW semaphore thought the SW_FW_SYNC register for\n * the specified function (CSR, PHY0, PHY1, NVM, Flash)\n **/\n-s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)\n+s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n {\n-\tu32 swfw_sync;\n-\tu32 swmask = mask;\n-\tu32 fwmask = mask << 5;\n-\tu32 hwmask = 0;\n+\tu32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;\n+\tu32 fwmask = swmask << 5;\n+\tu32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;\n \tu32 timeout = 200;\n+\tu32 hwmask = 0;\n+\tu32 swfw_sync;\n \tu32 i;\n-\ts32 ret_val = IXGBE_SUCCESS;\n \n \tDEBUGFUNC(\"ixgbe_acquire_swfw_sync_X540\");\n \n-\tif (swmask == IXGBE_GSSR_EEP_SM)\n-\t\thwmask = IXGBE_GSSR_FLASH_SM;\n+\tif (swmask & IXGBE_GSSR_EEP_SM)\n+\t\thwmask |= IXGBE_GSSR_FLASH_SM;\n \n \t/* SW only mask doesn't have FW bit pair */\n-\tif (swmask == IXGBE_GSSR_SW_MNG_SM)\n-\t\tfwmask = 0;\n+\tif (mask & IXGBE_GSSR_SW_MNG_SM)\n+\t\tswmask |= IXGBE_GSSR_SW_MNG_SM;\n \n+\tswmask |= swi2c_mask;\n+\tfwmask |= swi2c_mask << 2;\n \tfor (i = 0; i < timeout; i++) {\n-\t\t/*\n-\t\t * SW NVM semaphore bit is used for access to all\n+\t\t/* SW NVM semaphore bit is used for access to all\n \t\t * SW_FW_SYNC bits (not just NVM)\n \t\t */\n-\t\tif (ixgbe_get_swfw_sync_semaphore(hw)) {\n-\t\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n-\t\t\tgoto out;\n-\t\t}\n+\t\tif (ixgbe_get_swfw_sync_semaphore(hw))\n+\t\t\treturn IXGBE_ERR_SWFW_SYNC;\n \n \t\tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n \t\tif (!(swfw_sync & (fwmask | swmask | hwmask))) {\n@@ -779,24 +798,23 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)\n \t\t\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n \t\t\tixgbe_release_swfw_sync_semaphore(hw);\n \t\t\tmsec_delay(5);\n-\t\t\tgoto out;\n-\t\t} else {\n-\t\t\t/*\n-\t\t\t * Firmware currently using resource (fwmask), hardware\n-\t\t\t * currently using resource (hwmask), or other software\n-\t\t\t * thread currently using resource (swmask)\n-\t\t\t */\n-\t\t\tixgbe_release_swfw_sync_semaphore(hw);\n-\t\t\tmsec_delay(5);\n+\t\t\tif (swi2c_mask)\n+\t\t\t\tixgbe_set_mux(hw, 1);\n+\t\t\treturn IXGBE_SUCCESS;\n \t\t}\n+\t\t/* Firmware currently using resource (fwmask), hardware\n+\t\t * currently using resource (hwmask), or other software\n+\t\t * thread currently using resource (swmask)\n+\t\t */\n+\t\tixgbe_release_swfw_sync_semaphore(hw);\n+\t\tmsec_delay(5);\n \t}\n \n \t/* Failed to get SW only semaphore */\n \tif (swmask == IXGBE_GSSR_SW_MNG_SM) {\n-\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n \t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n \t\t\t \"Failed to get SW only semaphore\");\n-\t\tgoto out;\n+\t\treturn IXGBE_ERR_SWFW_SYNC;\n \t}\n \n \t/* If the resource is not released by the FW/HW the SW can assume that\n@@ -804,32 +822,36 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)\n \t * of the requested resource(s) while ignoring the corresponding FW/HW\n \t * bits in the SW_FW_SYNC register.\n \t */\n+\tif (ixgbe_get_swfw_sync_semaphore(hw))\n+\t\treturn IXGBE_ERR_SWFW_SYNC;\n \tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\n \tif (swfw_sync & (fwmask | hwmask)) {\n-\t\tif (ixgbe_get_swfw_sync_semaphore(hw)) {\n-\t\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n-\t\t\tgoto out;\n-\t\t}\n-\n \t\tswfw_sync |= swmask;\n \t\tIXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);\n \t\tixgbe_release_swfw_sync_semaphore(hw);\n \t\tmsec_delay(5);\n+\t\tif (swi2c_mask)\n+\t\t\tixgbe_set_mux(hw, 1);\n+\t\treturn IXGBE_SUCCESS;\n \t}\n \t/* If the resource is not released by other SW the SW can assume that\n \t * the other SW malfunctions. In that case the SW should clear all SW\n \t * flags that it does not own and then repeat the whole process once\n \t * again.\n \t */\n-\telse if (swfw_sync & swmask) {\n-\t\tixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM |\n-\t\t\tIXGBE_GSSR_PHY0_SM | IXGBE_GSSR_PHY1_SM |\n-\t\t\tIXGBE_GSSR_MAC_CSR_SM);\n-\t\tret_val = IXGBE_ERR_SWFW_SYNC;\n+\tif (swfw_sync & swmask) {\n+\t\tu32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |\n+\t\t\t IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;\n+\n+\t\tif (swi2c_mask)\n+\t\t\trmask |= IXGBE_GSSR_I2C_MASK;\n+\t\tixgbe_release_swfw_sync_X540(hw, rmask);\n+\t\tixgbe_release_swfw_sync_semaphore(hw);\n+\t\treturn IXGBE_ERR_SWFW_SYNC;\n \t}\n+\tixgbe_release_swfw_sync_semaphore(hw);\n \n-out:\n-\treturn ret_val;\n+\treturn IXGBE_ERR_SWFW_SYNC;\n }\n \n /**\n@@ -840,13 +862,17 @@ out:\n * Releases the SWFW semaphore through the SW_FW_SYNC register\n * for the specified function (CSR, PHY0, PHY1, EVM, Flash)\n **/\n-void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)\n+void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)\n {\n+\tu32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);\n \tu32 swfw_sync;\n-\tu32 swmask = mask;\n \n \tDEBUGFUNC(\"ixgbe_release_swfw_sync_X540\");\n \n+\tif (mask & IXGBE_GSSR_I2C_MASK) {\n+\t\tswmask |= mask & IXGBE_GSSR_I2C_MASK;\n+\t\tixgbe_set_mux(hw, 0);\n+\t}\n \tixgbe_get_swfw_sync_semaphore(hw);\n \n \tswfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h\nindex 86158e6..338c0e6 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h\n@@ -58,8 +58,8 @@ s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val);\n s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw);\n s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);\n \n-s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);\n-void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);\n+s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);\n+void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask);\n \n s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);\n s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);\n", "prefixes": [ "dpdk-dev", "07/18" ] }