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GET /api/patches/50932/?format=api
{ "id": 50932, "url": "https://patches.dpdk.org/api/patches/50932/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190307125841.14247-12-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190307125841.14247-12-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190307125841.14247-12-qi.z.zhang@intel.com", "date": "2019-03-07T12:58:15", "name": "[v2,11/37] net/ice/base: add APIs to get allocated resources", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4e3f6379e2bac88f7f6791abb80d3df80b1e072a", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190307125841.14247-12-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 3662, "url": "https://patches.dpdk.org/api/series/3662/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=3662", "date": "2019-03-07T12:58:04", "name": "ice share code update.", "version": 2, "mbox": "https://patches.dpdk.org/series/3662/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/50932/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/50932/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8FA597CCA;\n\tThu, 7 Mar 2019 13:57:14 +0100 (CET)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n\tby dpdk.org (Postfix) with ESMTP id 23DB25F19\n\tfor <dev@dpdk.org>; Thu, 7 Mar 2019 13:57:09 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t07 Mar 2019 04:57:09 -0800", "from dpdk51.sh.intel.com ([10.67.110.160])\n\tby fmsmga001.fm.intel.com with ESMTP; 07 Mar 2019 04:57:08 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.58,451,1544515200\"; d=\"scan'208\";a=\"152884365\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "wenzhuo.lu@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, paul.m.stillwell.jr@intel.com, ferruh.yigit@intel.com,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Thu, 7 Mar 2019 20:58:15 +0800", "Message-Id": "<20190307125841.14247-12-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20190307125841.14247-1-qi.z.zhang@intel.com>", "References": "<20190228055650.25237-1-qi.z.zhang@intel.com>\n\t<20190307125841.14247-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 11/37] net/ice/base: add APIs to get allocated\n\tresources", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "1. ice_aq_get_res_alloc - get allocated resources.\n2. ice_aq_get_res_descs - get allocated resource descriptors.\n\nThese APIs may help to PMD to enable some debug utilities to\ndump the resource allocation status.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 53 +++++++++++++++++++++-\n drivers/net/ice/base/ice_switch.c | 83 +++++++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_switch.h | 12 +++++\n 3 files changed, 147 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 724657af6..ca3d40c8b 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -281,6 +281,34 @@ struct ice_aqc_get_sw_cfg_resp {\n \n #define ICE_AQC_RES_TYPE_FLAG_DEDICATED\t\t\t0x00\n \n+#define ICE_AQC_RES_TYPE_S\t0\n+#define ICE_AQC_RES_TYPE_M\t(0x07F << ICE_AQC_RES_TYPE_S)\n+\n+/* Get Resource Allocation command (indirect 0x0204) */\n+struct ice_aqc_get_res_alloc {\n+\t__le16 resp_elem_num; /* Used in response, reserved in command */\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+/* Get Resource Allocation Response Buffer per response */\n+struct ice_aqc_get_res_resp_elem {\n+\t__le16 res_type; /* Types defined above cmd 0x0204 */\n+\t__le16 total_capacity; /* Resources available to all PF's */\n+\t__le16 total_function; /* Resources allocated for a PF */\n+\t__le16 total_shared; /* Resources allocated as shared */\n+\t__le16 total_free; /* Resources un-allocated/not reserved by any PF */\n+};\n+\n+/* Buffer for Get Resource command */\n+struct ice_aqc_get_res_resp {\n+\t/* Number of resource entries to be calculated using\n+\t * datalen/sizeof(struct ice_aqc_cmd_resp)).\n+\t * Value of 'datalen' gets updated as part of response.\n+\t */\n+\tstruct ice_aqc_get_res_resp_elem elem[1];\n+};\n \n \n /* Allocate Resources command (indirect 0x0208)\n@@ -314,6 +342,28 @@ struct ice_aqc_alloc_free_res_elem {\n };\n \n \n+/* Get Allocated Resource Descriptors Command (indirect 0x020A) */\n+struct ice_aqc_get_allocd_res_desc {\n+\tunion {\n+\t\tstruct {\n+\t\t\t__le16 res; /* Types defined above cmd 0x0204 */\n+\t\t\t__le16 first_desc;\n+\t\t\t__le32 reserved;\n+\t\t} cmd;\n+\t\tstruct {\n+\t\t\t__le16 res;\n+\t\t\t__le16 next_desc;\n+\t\t\t__le16 num_desc;\n+\t\t\t__le16 reserved;\n+\t\t} resp;\n+\t} ops;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+struct ice_aqc_get_allocd_res_desc_resp {\n+\tstruct ice_aqc_res_elem elem[1];\n+};\n \n \n /* Add VSI (indirect 0x0210)\n@@ -1912,7 +1962,6 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_query_node_to_root query_node_to_root;\n \t\tstruct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;\n \t\tstruct ice_aqc_rl_profile rl_profile;\n-\n \t\tstruct ice_aqc_nvm nvm;\n \t\tstruct ice_aqc_nvm_cfg nvm_cfg;\n \t\tstruct ice_aqc_nvm_checksum nvm_checksum;\n@@ -1930,6 +1979,8 @@ struct ice_aq_desc {\n \t\tstruct ice_aqc_get_clear_fw_log get_clear_fw_log;\n \t\tstruct ice_aqc_set_mac_lb set_mac_lb;\n \t\tstruct ice_aqc_alloc_free_res_cmd sw_res_ctrl;\n+\t\tstruct ice_aqc_get_res_alloc get_res;\n+\t\tstruct ice_aqc_get_allocd_res_desc get_res_desc;\n \t\tstruct ice_aqc_set_mac_cfg set_mac_cfg;\n \t\tstruct ice_aqc_set_event_mask set_event_mask;\n \t\tstruct ice_aqc_get_link_status get_link_status;\ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex 4af6a323c..c985c1e31 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -2042,6 +2042,89 @@ ice_remove_rule_internal(struct ice_hw *hw, u8 recp_id,\n \treturn status;\n }\n \n+/**\n+ * ice_aq_get_res_alloc - get allocated resources\n+ * @hw: pointer to the HW struct\n+ * @num_entries: pointer to u16 to store the number of resource entries returned\n+ * @buf: pointer to user-supplied buffer\n+ * @buf_size: size of buff\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * The user-supplied buffer must be large enough to store the resource\n+ * information for all resource types. Each resource type is an\n+ * ice_aqc_get_res_resp_data_elem structure.\n+ */\n+enum ice_status\n+ice_aq_get_res_alloc(struct ice_hw *hw, u16 *num_entries, void *buf,\n+\t\t u16 buf_size, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_res_alloc *resp;\n+\tenum ice_status status;\n+\tstruct ice_aq_desc desc;\n+\n+\tif (!buf)\n+\t\treturn ICE_ERR_BAD_PTR;\n+\n+\tif (buf_size < ICE_AQ_GET_RES_ALLOC_BUF_LEN)\n+\t\treturn ICE_ERR_INVAL_SIZE;\n+\n+\tresp = &desc.params.get_res;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_res_alloc);\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\n+\tif (!status && num_entries)\n+\t\t*num_entries = LE16_TO_CPU(resp->resp_elem_num);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_aq_get_res_descs - get allocated resource descriptors\n+ * @hw: pointer to the hardware structure\n+ * @num_entries: number of resource entries in buffer\n+ * @buf: Indirect buffer to hold data parameters and response\n+ * @buf_size: size of buffer for indirect commands\n+ * @res_type: resource type\n+ * @res_shared: is resource shared\n+ * @desc_id: input - first desc ID to start; output - next desc ID\n+ * @cd: pointer to command details structure or NULL\n+ */\n+enum ice_status\n+ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,\n+\t\t struct ice_aqc_get_allocd_res_desc_resp *buf,\n+\t\t u16 buf_size, u16 res_type, bool res_shared, u16 *desc_id,\n+\t\t struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aqc_get_allocd_res_desc *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_get_res_descs\");\n+\n+\tcmd = &desc.params.get_res_desc;\n+\n+\tif (!buf)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tif (buf_size != (num_entries * sizeof(*buf)))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_allocd_res_desc);\n+\n+\tcmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &\n+\t\t\t\t\t ICE_AQC_RES_TYPE_M) | (res_shared ?\n+\t\t\t\t\tICE_AQC_RES_TYPE_FLAG_SHARED : 0));\n+\tcmd->ops.cmd.first_desc = CPU_TO_LE16(*desc_id);\n+\n+\tdesc.flags |= CPU_TO_LE16(ICE_AQ_FLAG_RD);\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);\n+\tif (!status)\n+\t\t*desc_id = LE16_TO_CPU(cmd->ops.resp.next_desc);\n+\n+\treturn status;\n+}\n \n /**\n * ice_add_mac - Add a MAC address based filter rule\ndiff --git a/drivers/net/ice/base/ice_switch.h b/drivers/net/ice/base/ice_switch.h\nindex f331621e1..4b77d920f 100644\n--- a/drivers/net/ice/base/ice_switch.h\n+++ b/drivers/net/ice/base/ice_switch.h\n@@ -13,6 +13,10 @@\n #define ICE_DFLT_VSI_INVAL 0xff\n \n \n+/* Worst case buffer length for ice_aqc_opc_get_res_alloc */\n+#define ICE_MAX_RES_TYPES 0x80\n+#define ICE_AQ_GET_RES_ALLOC_BUF_LEN \\\n+\t(ICE_MAX_RES_TYPES * sizeof(struct ice_aqc_get_res_resp_elem))\n \n #define ICE_VSI_INVAL_ID 0xFFFF\n #define ICE_INVAL_Q_HANDLE 0xFFFF\n@@ -343,6 +347,14 @@ ice_alloc_sw(struct ice_hw *hw, bool ena_stats, bool shared_res, u16 *sw_id,\n enum ice_status\n ice_free_sw(struct ice_hw *hw, u16 sw_id, u16 counter_id);\n enum ice_status\n+ice_aq_get_res_alloc(struct ice_hw *hw, u16 *num_entries, void *buf,\n+\t\t u16 buf_size, struct ice_sq_cd *cd);\n+enum ice_status\n+ice_aq_get_res_descs(struct ice_hw *hw, u16 num_entries,\n+\t\t struct ice_aqc_get_allocd_res_desc_resp *buf,\n+\t\t u16 buf_size, u16 res_type, bool res_shared, u16 *desc_id,\n+\t\t struct ice_sq_cd *cd);\n+enum ice_status\n ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list);\n enum ice_status ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst);\n enum ice_status ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst);\n", "prefixes": [ "v2", "11/37" ] }