Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/505/?format=api
{ "id": 505, "url": "https://patches.dpdk.org/api/patches/505/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1411634427-746-12-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411634427-746-12-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411634427-746-12-git-send-email-helin.zhang@intel.com", "date": "2014-09-25T08:40:25", "name": "[dpdk-dev,v2,11/13] i40e: rework of updating/querying reta", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "8e44301aaf8787b15263449e1dcce8254fe53317", "submitter": { "id": 14, "url": "https://patches.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1411634427-746-12-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "https://patches.dpdk.org/api/patches/505/comments/", "check": "pending", "checks": "https://patches.dpdk.org/api/patches/505/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 8A9C6B3D3;\n\tThu, 25 Sep 2014 10:35:13 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id C80FEB3D1\n\tfor <dev@dpdk.org>; Thu, 25 Sep 2014 10:35:11 +0200 (CEST)", "from orsmga001.jf.intel.com ([10.7.209.18])\n\tby orsmga102.jf.intel.com with ESMTP; 25 Sep 2014 01:35:12 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby orsmga001.jf.intel.com with ESMTP; 25 Sep 2014 01:40:57 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8P8eu4V002330;\n\tThu, 25 Sep 2014 16:40:56 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8P8erDB000859; Thu, 25 Sep 2014 16:40:55 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8P8erKe000855; \n\tThu, 25 Sep 2014 16:40:53 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,595,1406617200\"; d=\"scan'208\";a=\"578729312\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 25 Sep 2014 16:40:25 +0800", "Message-Id": "<1411634427-746-12-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411634427-746-1-git-send-email-helin.zhang@intel.com>", "References": "<1411634427-746-1-git-send-email-helin.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 11/13] i40e: rework of updating/querying reta", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "As ethdev has been changed to support multiple sizes of reta,\nupdating/querying reta should be reworked to support that change.\n\nv2 changes:\n* Put rework of updating/querying i40e reta to a single patch.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nReviewed-by: Jijiang Liu <jijiang.liu@intel.com>\nReviewed-by: Cunming Liang <cunming.liang@intel.com>\nReviewed-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n lib/librte_pmd_i40e/i40e_ethdev.c | 93 ++++++++++++++++++++++-----------------\n lib/librte_pmd_i40e/i40e_ethdev.h | 12 +++++\n 2 files changed, 65 insertions(+), 40 deletions(-)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c\nindex 9fe3f7a..6338e1b 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.c\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.c\n@@ -72,14 +72,6 @@\n /* Maximun number of VSI */\n #define I40E_MAX_NUM_VSIS (384UL)\n \n-/* Bit shift and mask */\n-#define I40E_16_BIT_SHIFT 16\n-#define I40E_16_BIT_MASK 0xFFFF\n-#define I40E_32_BIT_SHIFT 32\n-#define I40E_32_BIT_MASK 0xFFFFFFFF\n-#define I40E_48_BIT_SHIFT 48\n-#define I40E_48_BIT_MASK 0xFFFFFFFFFFFFULL\n-\n /* Default queue interrupt throttling time in microseconds*/\n #define I40E_ITR_INDEX_DEFAULT 0\n #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */\n@@ -160,9 +152,11 @@ static void i40e_macaddr_add(struct rte_eth_dev *dev,\n \t\t\t uint32_t pool);\n static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);\n static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_rss_reta *reta_conf);\n+\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t\t uint16_t reta_size);\n static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\t\t\t struct rte_eth_rss_reta *reta_conf);\n+\t\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t\t uint16_t reta_size);\n \n static int i40e_get_cap(struct i40e_hw *hw);\n static int i40e_pf_parameter_init(struct rte_eth_dev *dev);\n@@ -1590,32 +1584,41 @@ i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)\n \n static int\n i40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n-\t\t\t struct rte_eth_rss_reta *reta_conf)\n+\t\t\t struct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\t uint16_t reta_size)\n {\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint32_t lut, l;\n-\tuint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;\n-\n-\tfor (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < max)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n-\t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t\t\t(i - max)) & 0xF);\n+\tuint16_t i, j, lut_size = pf->hash_lut_size;\n+\tuint16_t idx, shift;\n+\tuint8_t mask;\n+\n+\tif (reta_size != lut_size ||\n+\t\treta_size > ETH_RSS_RETA_SIZE_512) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\t\t\"(%d)\\n\", reta_size, lut_size);\n+\t\treturn -EINVAL;\n+\t}\n \n+\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\t\t\tI40E_4_BIT_MASK);\n \t\tif (!mask)\n \t\t\tcontinue;\n-\n-\t\tif (mask == 0xF)\n+\t\tif (mask == I40E_4_BIT_MASK)\n \t\t\tl = 0;\n \t\telse\n \t\t\tl = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));\n-\n-\t\tfor (j = 0, lut = 0; j < 4; j++) {\n+\t\tfor (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {\n \t\t\tif (mask & (0x1 << j))\n-\t\t\t\tlut |= reta_conf->reta[i + j] << (8 * j);\n+\t\t\t\tlut |= reta_conf[idx].reta[shift + j] <<\n+\t\t\t\t\t\t\t(CHAR_BIT * j);\n \t\t\telse\n-\t\t\t\tlut |= l & (0xFF << (8 * j));\n+\t\t\t\tlut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));\n \t\t}\n \t\tI40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);\n \t}\n@@ -1625,27 +1628,37 @@ i40e_dev_rss_reta_update(struct rte_eth_dev *dev,\n \n static int\n i40e_dev_rss_reta_query(struct rte_eth_dev *dev,\n-\t\t\tstruct rte_eth_rss_reta *reta_conf)\n+\t\t\tstruct rte_eth_rss_reta_entry64 *reta_conf,\n+\t\t\tuint16_t reta_size)\n {\n+\tstruct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n \tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \tuint32_t lut;\n-\tuint8_t i, j, mask, max = ETH_RSS_RETA_NUM_ENTRIES / 2;\n-\n-\tfor (i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {\n-\t\tif (i < max)\n-\t\t\tmask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);\n-\t\telse\n-\t\t\tmask = (uint8_t)((reta_conf->mask_hi >>\n-\t\t\t\t\t\t(i - max)) & 0xF);\n+\tuint16_t i, j, lut_size = pf->hash_lut_size;\n+\tuint16_t idx, shift;\n+\tuint8_t mask;\n+\n+\tif (reta_size != lut_size ||\n+\t\treta_size > ETH_RSS_RETA_SIZE_512) {\n+\t\tPMD_DRV_LOG(ERR, \"The size of hash lookup table configured \"\n+\t\t\t\"(%d) doesn't match the number hardware can supported \"\n+\t\t\t\t\t\"(%d)\\n\", reta_size, lut_size);\n+\t\treturn -EINVAL;\n+\t}\n \n+\tfor (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {\n+\t\tidx = i / RTE_BIT_WIDTH_64;\n+\t\tshift = i % RTE_BIT_WIDTH_64;\n+\t\tmask = (uint8_t)((reta_conf[idx].mask >> shift) &\n+\t\t\t\t\t\tI40E_4_BIT_MASK);\n \t\tif (!mask)\n \t\t\tcontinue;\n \n \t\tlut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));\n-\t\tfor (j = 0; j < 4; j++) {\n+\t\tfor (j = 0; j < I40E_4_BIT_WIDTH; j++) {\n \t\t\tif (mask & (0x1 << j))\n-\t\t\t\treta_conf->reta[i + j] =\n-\t\t\t\t\t(uint8_t)((lut >> (8 * j)) & 0xFF);\n+\t\t\t\treta_conf[idx].reta[shift] = ((lut >>\n+\t\t\t\t\t(CHAR_BIT * j)) & I40E_8_BIT_MASK);\n \t\t}\n \t}\n \n@@ -3225,7 +3238,7 @@ i40e_stat_update_32(struct i40e_hw *hw,\n \t\t*stat = (uint64_t)(new_data - *offset);\n \telse\n \t\t*stat = (uint64_t)((new_data +\n-\t\t\t((uint64_t)1 << I40E_32_BIT_SHIFT)) - *offset);\n+\t\t\t((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);\n }\n \n static void\n@@ -3240,7 +3253,7 @@ i40e_stat_update_48(struct i40e_hw *hw,\n \n \tnew_data = (uint64_t)I40E_READ_REG(hw, loreg);\n \tnew_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &\n-\t\t\tI40E_16_BIT_MASK)) << I40E_32_BIT_SHIFT;\n+\t\t\tI40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;\n \n \tif (!offset_loaded)\n \t\t*offset = new_data;\n@@ -3249,7 +3262,7 @@ i40e_stat_update_48(struct i40e_hw *hw,\n \t\t*stat = new_data - *offset;\n \telse\n \t\t*stat = (uint64_t)((new_data +\n-\t\t\t((uint64_t)1 << I40E_48_BIT_SHIFT)) - *offset);\n+\t\t\t((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);\n \n \t*stat &= I40E_48_BIT_MASK;\n }\ndiff --git a/lib/librte_pmd_i40e/i40e_ethdev.h b/lib/librte_pmd_i40e/i40e_ethdev.h\nindex a1a2e75..336e936 100644\n--- a/lib/librte_pmd_i40e/i40e_ethdev.h\n+++ b/lib/librte_pmd_i40e/i40e_ethdev.h\n@@ -52,6 +52,18 @@\n /* Default TC traffic in case DCB is not enabled */\n #define I40E_DEFAULT_TCMAP 0x1\n \n+/* Bit shift and mask */\n+#define I40E_4_BIT_WIDTH (CHAR_BIT / 2)\n+#define I40E_4_BIT_MASK ((1 << I40E_4_BIT_WIDTH) - 1)\n+#define I40E_8_BIT_WIDTH CHAR_BIT\n+#define I40E_8_BIT_MASK ((1 << I40E_8_BIT_WIDTH) - 1)\n+#define I40E_16_BIT_WIDTH (CHAR_BIT * 2)\n+#define I40E_16_BIT_MASK ((1 << I40E_16_BIT_WIDTH) - 1)\n+#define I40E_32_BIT_WIDTH (CHAR_BIT * 4)\n+#define I40E_32_BIT_MASK ((1 << I40E_32_BIT_WIDTH) - 1)\n+#define I40E_48_BIT_WIDTH (CHAR_BIT * 6)\n+#define I40E_48_BIT_MASK ((1ULL << I40E_48_BIT_WIDTH) - 1)\n+\n /* i40e flags */\n #define I40E_FLAG_RSS (1ULL << 0)\n #define I40E_FLAG_DCB (1ULL << 1)\n", "prefixes": [ "dpdk-dev", "v2", "11/13" ] }