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GET /api/patches/50219/?format=api
{ "id": 50219, "url": "https://patches.dpdk.org/api/patches/50219/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1549556983-10896-19-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1549556983-10896-19-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1549556983-10896-19-git-send-email-arybchenko@solarflare.com", "date": "2019-02-07T16:29:23", "name": "[18/38] net/sfc/base: support different Tx descriptor sizes", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "882d18614ae3509ad6e092a0a96f97b322b3ceb6", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1549556983-10896-19-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 3411, "url": "https://patches.dpdk.org/api/series/3411/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=3411", "date": "2019-02-07T16:29:05", "name": "net/sfc: update base driver", "version": 1, "mbox": "https://patches.dpdk.org/series/3411/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/50219/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/50219/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 841151B60C;\n\tThu, 7 Feb 2019 17:31:04 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id B2B011B57F\n\tfor <dev@dpdk.org>; Thu, 7 Feb 2019 17:30:37 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id 6C8A4B80097; Thu, 7 Feb 2019 16:30:36 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:31 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:31 -0800", "from ukv-loginhost.uk.solarflarecom.com\n\t(ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tx17GUU0I015319; Thu, 7 Feb 2019 16:30:30 GMT", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n\tby ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id\n\tF3CF01613E4; Thu, 7 Feb 2019 16:30:29 +0000 (GMT)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Igor Romanov <igor.romanov@oktetlabs.ru>", "Date": "Thu, 7 Feb 2019 16:29:23 +0000", "Message-ID": "<1549556983-10896-19-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "References": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-TM-AS-Result": "No-3.226600-4.000000-10", "X-TMASE-MatchedRID": "Av/pE9tNfKGbGHSBj+j5WW4gfPq9dKeJ7qPKKDEKjrIs/uUAk6xP7Gb6\n\tPphVtfZgjcuGinzvclViZXavL3o+QLf0EuHoGRzuyDp+jSvEtWuENvZav9mwIVSOymiJfTYXFER\n\tdnCEO4XGERJHCmsiOOJIKYwRfNxg8t/K29VNwEQWNzYJBKgDdESseSAhqf1rRMBVcbaPpizAsDq\n\tJYnYVD8eLzNWBegCW2wgn7iDBesS1YF3qW3Je6+2Y7NY2xbBtzWnyneff42cquXKBrUu7cA74zQ\n\tkI6W2QY1oY+s8iXCWgdRxJkXsyDZmgBX0AWRD1haSFMZKuVVmLEMjJbUM6/OL1NuKS30BZnQIFI\n\tZLtsgG0DUH+nVLNyiCsqIP9TxvtJo1s8kG68tot+3BndfXUhXQ==", "X-TM-AS-User-Approved-Sender": "No", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10-3.226600-4.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-MDID": "1549557037-zsHq1ynzCGjB", "Subject": "[dpdk-dev] [PATCH 18/38] net/sfc/base: support different Tx\n\tdescriptor sizes", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Igor Romanov <igor.romanov@oktetlabs.ru>\n\nSize of Tx descriptor is different on Riverhead. So, the size\nshould be a part of NIC config, not a macro that is common for\nall NIC families.\n\nSigned-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_impl.h | 2 ++\n drivers/net/sfc/base/ef10_tx.c | 7 ++++---\n drivers/net/sfc/base/efx.h | 21 +++++++++++++++++++++\n drivers/net/sfc/base/efx_tx.c | 18 ++++++++++++++++++\n drivers/net/sfc/base/hunt_nic.c | 2 ++\n drivers/net/sfc/base/medford2_nic.c | 2 ++\n drivers/net/sfc/base/medford_nic.c | 2 ++\n drivers/net/sfc/base/siena_impl.h | 2 ++\n drivers/net/sfc/base/siena_nic.c | 2 ++\n 9 files changed, 55 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h\nindex 12747f43c..0116bc91c 100644\n--- a/drivers/net/sfc/base/ef10_impl.h\n+++ b/drivers/net/sfc/base/ef10_impl.h\n@@ -19,6 +19,8 @@ extern \"C\" {\n \n #define\tEF10_TXQ_MINNDESCS\t512\n \n+#define\tEF10_TXQ_DESC_SIZE\t(sizeof (efx_qword_t))\n+\n /* Maximum independent of EFX_BUG35388_WORKAROUND. */\n #define\tEF10_TXQ_MAXNBUFS\t8\n \ndiff --git a/drivers/net/sfc/base/ef10_tx.c b/drivers/net/sfc/base/ef10_tx.c\nindex aacf4310a..82be77f13 100644\n--- a/drivers/net/sfc/base/ef10_tx.c\n+++ b/drivers/net/sfc/base/ef10_tx.c\n@@ -41,14 +41,15 @@ efx_mcdi_init_txq(\n \tefx_rc_t rc;\n \n \tEFSYS_ASSERT(EF10_TXQ_MAXNBUFS >=\n-\t EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));\n+\t efx_txq_nbufs(enp, enp->en_nic_cfg.enc_txq_max_ndescs));\n \n-\tif ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_TXQ_SIZE(ndescs))) {\n+\tif ((esmp == NULL) ||\n+\t (EFSYS_MEM_SIZE(esmp) < efx_txq_size(enp, ndescs))) {\n \t\trc = EINVAL;\n \t\tgoto fail1;\n \t}\n \n-\tnpages = EFX_TXQ_NBUFS(ndescs);\n+\tnpages = efx_txq_nbufs(enp, ndescs);\n \tif (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {\n \t\trc = EINVAL;\n \t\tgoto fail2;\ndiff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex 8aa03b538..506bdb5e1 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -1284,6 +1284,7 @@ typedef struct efx_nic_cfg_s {\n \tuint32_t\t\tenc_evq_timer_quantum_ns;\n \tuint32_t\t\tenc_evq_timer_max_us;\n \tuint32_t\t\tenc_clk_mult;\n+\tuint32_t\t\tenc_tx_desc_size;\n \tuint32_t\t\tenc_rx_prefix_size;\n \tuint32_t\t\tenc_rx_buf_align_start;\n \tuint32_t\t\tenc_rx_buf_align_end;\n@@ -2645,8 +2646,28 @@ efx_tx_fini(\n */\n #define\tEFX_TXQ_MINNDESCS\t\t512\n \n+/*\n+ * This macro is deprecated and will be removed.\n+ * Use the function efx_txq_size() instead.\n+ */\n #define\tEFX_TXQ_SIZE(_ndescs)\t\t((_ndescs) * sizeof (efx_qword_t))\n+\n+/*\n+ * This macro is deprecated and will be removed.\n+ * Use the function efx_txq_nbufs() instead.\n+ */\n #define\tEFX_TXQ_NBUFS(_ndescs)\t\t(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)\n+\n+extern\t__checkReturn\tsize_t\n+efx_txq_size(\n+\t__in\tconst efx_nic_t *enp,\n+\t__in\tunsigned int ndescs);\n+\n+extern\t__checkReturn\tunsigned int\n+efx_txq_nbufs(\n+\t__in\tconst efx_nic_t *enp,\n+\t__in\tunsigned int ndescs);\n+\n #define\tEFX_TXQ_LIMIT(_ndescs)\t\t((_ndescs) - 16)\n \n #define\tEFX_TXQ_CKSUM_IPV4\t\t0x0001\ndiff --git a/drivers/net/sfc/base/efx_tx.c b/drivers/net/sfc/base/efx_tx.c\nindex b777a85c5..bbe2bd1b7 100644\n--- a/drivers/net/sfc/base/efx_tx.c\n+++ b/drivers/net/sfc/base/efx_tx.c\n@@ -297,6 +297,24 @@ efx_tx_fini(\n \tenp->en_mod_flags &= ~EFX_MOD_TX;\n }\n \n+\t__checkReturn\tsize_t\n+efx_txq_size(\n+\t__in\tconst efx_nic_t *enp,\n+\t__in\tunsigned int ndescs)\n+{\n+\tconst efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);\n+\n+\treturn (ndescs * encp->enc_tx_desc_size);\n+}\n+\n+\t__checkReturn\tunsigned int\n+efx_txq_nbufs(\n+\t__in\tconst efx_nic_t *enp,\n+\t__in\tunsigned int ndescs)\n+{\n+\treturn (efx_txq_size(enp, ndescs) / EFX_BUF_SIZE);\n+}\n+\n \t__checkReturn\tefx_rc_t\n efx_tx_qcreate(\n \t__in\t\tefx_nic_t *enp,\ndiff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c\nindex 755a377f0..b4fc3cc9e 100644\n--- a/drivers/net/sfc/base/hunt_nic.c\n+++ b/drivers/net/sfc/base/hunt_nic.c\n@@ -186,6 +186,8 @@ hunt_board_cfg(\n \t/* Checksums for TSO sends can be incorrect on Huntington. */\n \tencp->enc_bug61297_workaround = B_TRUE;\n \n+\tencp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;\n+\n \t/* Alignment for receive packet DMA buffers */\n \tencp->enc_rx_buf_align_start = 1;\n \tencp->enc_rx_buf_align_end = 64; /* RX DMA end padding */\ndiff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c\nindex 3274744d9..9cfc5077c 100644\n--- a/drivers/net/sfc/base/medford2_nic.c\n+++ b/drivers/net/sfc/base/medford2_nic.c\n@@ -101,6 +101,8 @@ medford2_board_cfg(\n \tencp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<\n \t\t FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;\n \n+\tencp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;\n+\n \t/* Alignment for receive packet DMA buffers */\n \tencp->enc_rx_buf_align_start = 1;\n \ndiff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c\nindex cb107fe75..3f2c5b877 100644\n--- a/drivers/net/sfc/base/medford_nic.c\n+++ b/drivers/net/sfc/base/medford_nic.c\n@@ -99,6 +99,8 @@ medford_board_cfg(\n \tencp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<\n \t\t FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;\n \n+\tencp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;\n+\n \t/* Alignment for receive packet DMA buffers */\n \tencp->enc_rx_buf_align_start = 1;\n \ndiff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h\nindex caab29af0..6f07b1ec7 100644\n--- a/drivers/net/sfc/base/siena_impl.h\n+++ b/drivers/net/sfc/base/siena_impl.h\n@@ -34,6 +34,8 @@ extern \"C\" {\n #define\tSIENA_RXQ_MAXNDESCS\t4096\n #define\tSIENA_RXQ_MINNDESCS\t512\n \n+#define\tSIENA_TXQ_DESC_SIZE\t(sizeof (efx_qword_t))\n+\n #define\tSIENA_NVRAM_CHUNK 0x80\n \n \ndiff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c\nindex 4962a65c5..987a32d2f 100644\n--- a/drivers/net/sfc/base/siena_nic.c\n+++ b/drivers/net/sfc/base/siena_nic.c\n@@ -104,6 +104,8 @@ siena_board_cfg(\n \tencp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<\n \t\tFRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;\n \n+\tencp->enc_tx_desc_size = SIENA_TXQ_DESC_SIZE;\n+\n \t/* When hash header insertion is enabled, Siena inserts 16 bytes */\n \tencp->enc_rx_prefix_size = 16;\n \n", "prefixes": [ "18/38" ] }