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GET /api/patches/50217/?format=api
{ "id": 50217, "url": "https://patches.dpdk.org/api/patches/50217/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1549556983-10896-29-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1549556983-10896-29-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1549556983-10896-29-git-send-email-arybchenko@solarflare.com", "date": "2019-02-07T16:29:33", "name": "[28/38] net/sfc/base: add support for the Rx event mode w/o continue", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f42b41dada7df2dc42a9c16b1e1070032b73efe8", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1549556983-10896-29-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 3411, "url": "https://patches.dpdk.org/api/series/3411/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=3411", "date": "2019-02-07T16:29:05", "name": "net/sfc: update base driver", "version": 1, "mbox": "https://patches.dpdk.org/series/3411/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/50217/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/50217/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id ED72E1B6F1;\n\tThu, 7 Feb 2019 17:31:11 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 5CA951B586\n\tfor <dev@dpdk.org>; Thu, 7 Feb 2019 17:30:38 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id\n\t1FDB2B80083 for <dev@dpdk.org>; Thu, 7 Feb 2019 16:30:37 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:32 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:31 -0800", "from ukv-loginhost.uk.solarflarecom.com\n\t(ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tx17GUUN3015364; Thu, 7 Feb 2019 16:30:30 GMT", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n\tby ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id\n\t7A9DD1613E4; Thu, 7 Feb 2019 16:30:30 +0000 (GMT)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Mark Spender <mspender@solarflare.com>", "Date": "Thu, 7 Feb 2019 16:29:33 +0000", "Message-ID": "<1549556983-10896-29-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "References": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-TM-AS-Result": "No-10.194600-4.000000-10", "X-TMASE-MatchedRID": "WjngBjSap6+qO+wHLkIcOxMxKDqgAFSzKx5ICGp/WtHUkmGK2R+K3Ea6\n\tQkPhaz6Ts5PSbmZsjxrJKx74LP4l24dM1kFwmWfIyDp+jSvEtWteu73mFK6GNDWtSJsoHmgLCKh\n\tuU3rY4TAf3xAoOEZdyXKe5+5QHgy+t/QS4egZHO4flhDI6DvVlkyQ5fRSh265PDYCh3hVzeEWQo\n\tlg+d2D28ZF20JOjXR3DfRK7KHA7EC5fzRNL0I/VtOcmYs9btukoJif9euUGyvhV9mrCoq9XDA+a\n\tK41wNmIZ/K473afdmQrgaInFEE2wbZYfOyEKIls2ITTDZb/tDeCxYB2hPS4vcJ3vzMzuod4JWTQ\n\tsTqHabwpg9Tj/tAM3VRVzWRwtEoOxlkBw4mGj0Dil2r2x2PwtcSgMQYKGHsJzBk0Re9qFM1ALxM\n\tc0oXKrKHoquK2Le6ShEJetNSRxpSBBu3TM3/C4rccDyHlrQw5O1IfDKON40nI9EDAP/dptryGTr\n\tl5AuvT6juXFyNxoy3JgRAd5IlvjRDmHEk4zuFDHcQQBuf4ZFvXLq4lttlH/779+hjN0V79o8WMk\n\tQWv6iXBcIE78YqRWvcUt5lc1lLgOMB0shqXhHqy3+j5mRAwnruVoIPWTG2Z0AYF622OCMJnvH+H\n\t428T5dT1rysQ1ED/", "X-TM-AS-User-Approved-Sender": "No", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--10.194600-4.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-MDID": "1549557037-hk9lBxTwD0pz", "Subject": "[dpdk-dev] [PATCH 28/38] net/sfc/base: add support for the Rx event\n\tmode w/o continue", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Mark Spender <mspender@solarflare.com>\n\nThe recently added NO_CONT_EV mode is recommended for when looking for\nmaximum throughput on 100G links as it allows the firmware to operate\nmore efficiently. The biggest benefit is when using scatter and jumbo\nframes, but it is also necessary to achieve line rate in other cases.\n\nSupport for NO_CONT_EV when scatter is disabled is simple - the main\ndatapth change is to always read the packet length from the prefix,\nnot the event. This requires storing a flag with the event queue so\nthe event handler knows NO_CONT_EV mode is in use.\n\nSupporting NO_CONT_EV with scatter would require an API change.\n\n(Now the ee_flags field in efx_evq_t is used on the datapath, move it\nnext to other fields which are also read on the datapath to try to avoid\nreading an additional cache line.)\n\nSigned-off-by: Mark Spender <mspender@solarflare.com>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_ev.c | 65 +++++++++++++++++++++++++++------\n drivers/net/sfc/base/ef10_nic.c | 8 ++++\n drivers/net/sfc/base/ef10_rx.c | 23 +++++++++---\n drivers/net/sfc/base/efx.h | 11 ++++++\n drivers/net/sfc/base/efx_impl.h | 3 +-\n 5 files changed, 91 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_ev.c b/drivers/net/sfc/base/ef10_ev.c\nindex b80cb0a35..202930876 100644\n--- a/drivers/net/sfc/base/ef10_ev.c\n+++ b/drivers/net/sfc/base/ef10_ev.c\n@@ -457,6 +457,23 @@ ef10_ev_qcreate(\n \t\tgoto fail2;\n \t}\n \n+\t/*\n+\t * NO_CONT_EV mode is only requested from the firmware when creating\n+\t * receive queues, but here it needs to be specified at event queue\n+\t * creation, as the event handler needs to know which format is in use.\n+\t *\n+\t * If EFX_EVQ_FLAGS_NO_CONT_EV is specified, all receive queues for this\n+\t * event queue will be created in NO_CONT_EV mode.\n+\t *\n+\t * See SF-109306-TC 5.11 \"Events for RXQs in NO_CONT_EV mode\".\n+\t */\n+\tif (flags & EFX_EVQ_FLAGS_NO_CONT_EV) {\n+\t\tif (enp->en_nic_cfg.enc_no_cont_ev_mode_supported == B_FALSE) {\n+\t\t\trc = EINVAL;\n+\t\t\tgoto fail3;\n+\t\t}\n+\t}\n+\n \t/* Set up the handler table */\n \teep->ee_rx\t= ef10_ev_rx;\n \teep->ee_tx\t= ef10_ev_tx;\n@@ -494,7 +511,7 @@ ef10_ev_qcreate(\n \t\trc = efx_mcdi_init_evq_v2(enp, index, esmp, ndescs, irq, us,\n \t\t flags);\n \t\tif (rc != 0)\n-\t\t\tgoto fail3;\n+\t\t\tgoto fail4;\n \t} else {\n \t\t/*\n \t\t * On Huntington we need to specify the settings to use.\n@@ -511,11 +528,13 @@ ef10_ev_qcreate(\n \t\trc = efx_mcdi_init_evq(enp, index, esmp, ndescs, irq, us, flags,\n \t\t low_latency);\n \t\tif (rc != 0)\n-\t\t\tgoto fail4;\n+\t\t\tgoto fail5;\n \t}\n \n \treturn (0);\n \n+fail5:\n+\tEFSYS_PROBE(fail5);\n fail4:\n \tEFSYS_PROBE(fail4);\n fail3:\n@@ -912,23 +931,47 @@ ef10_ev_rx(\n \tif (mac_class == ESE_DZ_MAC_CLASS_UCAST)\n \t\tflags |= EFX_PKT_UNICAST;\n \n-\t/* Increment the count of descriptors read */\n+\t/*\n+\t * Increment the count of descriptors read.\n+\t *\n+\t * In NO_CONT_EV mode, RX_DSC_PTR_LBITS is actually a packet count, but\n+\t * when scatter is disabled, there is only one descriptor per packet and\n+\t * so it can be treated the same.\n+\t *\n+\t * TODO: Support scatter in NO_CONT_EV mode.\n+\t */\n \tdesc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &\n \t EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);\n \teersp->eers_rx_read_ptr += desc_count;\n \n-\t/*\n-\t * FIXME: add error checking to make sure this a batched event.\n-\t * This could also be an aborted scatter, see Bug36629.\n-\t */\n-\tif (desc_count > 1) {\n+\t/* Calculate the index of the last descriptor consumed */\n+\tlast_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;\n+\n+\tif (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV) {\n+\t\tif (desc_count > 1)\n+\t\t\tEFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);\n+\n+\t\t/* Always read the length from the prefix in NO_CONT_EV mode. */\n+\t\tflags |= EFX_PKT_PREFIX_LEN;\n+\n+\t\t/*\n+\t\t * Check for an aborted scatter, signalled by the ABORT bit in\n+\t\t * NO_CONT_EV mode. The ABORT bit was not used before NO_CONT_EV\n+\t\t * mode was added as it was broken in Huntington silicon.\n+\t\t */\n+\t\tif (EFX_QWORD_FIELD(*eqp, ESF_EZ_RX_ABORT) != 0) {\n+\t\t\tflags |= EFX_DISCARD;\n+\t\t\tgoto deliver;\n+\t\t}\n+\t} else if (desc_count > 1) {\n+\t\t/*\n+\t\t * FIXME: add error checking to make sure this a batched event.\n+\t\t * This could also be an aborted scatter, see Bug36629.\n+\t\t */\n \t\tEFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);\n \t\tflags |= EFX_PKT_PREFIX_LEN;\n \t}\n \n-\t/* Calculate the index of the last descriptor consumed */\n-\tlast_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;\n-\n \t/* Check for errors that invalidate checksum and L3/L4 fields */\n \tif (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TRUNC_ERR) != 0) {\n \t\t/* RX frame truncated */\ndiff --git a/drivers/net/sfc/base/ef10_nic.c b/drivers/net/sfc/base/ef10_nic.c\nindex d68920638..39ca53f03 100644\n--- a/drivers/net/sfc/base/ef10_nic.c\n+++ b/drivers/net/sfc/base/ef10_nic.c\n@@ -1197,6 +1197,14 @@ ef10_get_datapath_caps(\n \telse\n \t\tencp->enc_init_evq_v2_supported = B_FALSE;\n \n+\t/*\n+\t * Check if the NO_CONT_EV mode for RX events is supported.\n+\t */\n+\tif (CAP_FLAGS2(req, INIT_RXQ_NO_CONT_EV))\n+\t\tencp->enc_no_cont_ev_mode_supported = B_TRUE;\n+\telse\n+\t\tencp->enc_no_cont_ev_mode_supported = B_FALSE;\n+\n \t/*\n \t * Check if firmware-verified NVRAM updates must be used.\n \t *\ndiff --git a/drivers/net/sfc/base/ef10_rx.c b/drivers/net/sfc/base/ef10_rx.c\nindex 23b80d78f..3b296e488 100644\n--- a/drivers/net/sfc/base/ef10_rx.c\n+++ b/drivers/net/sfc/base/ef10_rx.c\n@@ -15,7 +15,7 @@ static\t__checkReturn\tefx_rc_t\n efx_mcdi_init_rxq(\n \t__in\t\tefx_nic_t *enp,\n \t__in\t\tuint32_t ndescs,\n-\t__in\t\tuint32_t target_evq,\n+\t__in\t\tefx_evq_t *eep,\n \t__in\t\tuint32_t label,\n \t__in\t\tuint32_t instance,\n \t__in\t\tefsys_mem_t *esmp,\n@@ -38,6 +38,7 @@ efx_mcdi_init_rxq(\n \tefx_rc_t rc;\n \tuint32_t dma_mode;\n \tboolean_t want_outer_classes;\n+\tboolean_t no_cont_ev;\n \n \tEFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs);\n \n@@ -47,6 +48,13 @@ efx_mcdi_init_rxq(\n \t\tgoto fail1;\n \t}\n \n+\tno_cont_ev = (eep->ee_flags & EFX_EVQ_FLAGS_NO_CONT_EV);\n+\tif ((no_cont_ev == B_TRUE) && (disable_scatter == B_FALSE)) {\n+\t\t/* TODO: Support scatter in NO_CONT_EV mode */\n+\t\trc = EINVAL;\n+\t\tgoto fail2;\n+\t}\n+\n \tif (ps_bufsize > 0)\n \t\tdma_mode = MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM;\n \telse if (es_bufs_per_desc > 0)\n@@ -81,10 +89,10 @@ efx_mcdi_init_rxq(\n \treq.emr_out_length = MC_CMD_INIT_RXQ_V3_OUT_LEN;\n \n \tMCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_SIZE, ndescs);\n-\tMCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, target_evq);\n+\tMCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_TARGET_EVQ, eep->ee_index);\n \tMCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_LABEL, label);\n \tMCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_INSTANCE, instance);\n-\tMCDI_IN_POPULATE_DWORD_9(req, INIT_RXQ_EXT_IN_FLAGS,\n+\tMCDI_IN_POPULATE_DWORD_10(req, INIT_RXQ_EXT_IN_FLAGS,\n \t INIT_RXQ_EXT_IN_FLAG_BUFF_MODE, 0,\n \t INIT_RXQ_EXT_IN_FLAG_HDR_SPLIT, 0,\n \t INIT_RXQ_EXT_IN_FLAG_TIMESTAMP, 0,\n@@ -94,7 +102,8 @@ efx_mcdi_init_rxq(\n \t INIT_RXQ_EXT_IN_DMA_MODE,\n \t dma_mode,\n \t INIT_RXQ_EXT_IN_PACKED_STREAM_BUFF_SIZE, ps_bufsize,\n-\t INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes);\n+\t INIT_RXQ_EXT_IN_FLAG_WANT_OUTER_CLASSES, want_outer_classes,\n+\t INIT_RXQ_EXT_IN_FLAG_NO_CONT_EV, no_cont_ev);\n \tMCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_OWNER_ID, 0);\n \tMCDI_IN_SET_DWORD(req, INIT_RXQ_EXT_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);\n \n@@ -127,11 +136,13 @@ efx_mcdi_init_rxq(\n \n \tif (req.emr_rc != 0) {\n \t\trc = req.emr_rc;\n-\t\tgoto fail2;\n+\t\tgoto fail3;\n \t}\n \n \treturn (0);\n \n+fail3:\n+\tEFSYS_PROBE(fail3);\n fail2:\n \tEFSYS_PROBE(fail2);\n fail1:\n@@ -1122,7 +1133,7 @@ ef10_rx_qcreate(\n \telse\n \t\twant_inner_classes = B_FALSE;\n \n-\tif ((rc = efx_mcdi_init_rxq(enp, ndescs, eep->ee_index, label, index,\n+\tif ((rc = efx_mcdi_init_rxq(enp, ndescs, eep, label, index,\n \t\t esmp, disable_scatter, want_inner_classes,\n \t\t ps_buf_size, es_bufs_per_desc, es_max_dma_len,\n \t\t es_buf_stride, hol_block_timeout)) != 0)\ndiff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex f7d0a4f67..f5ad095d4 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -1370,6 +1370,7 @@ typedef struct efx_nic_cfg_s {\n \tboolean_t\t\tenc_allow_set_mac_with_installed_filters;\n \tboolean_t\t\tenc_enhanced_set_mac_supported;\n \tboolean_t\t\tenc_init_evq_v2_supported;\n+\tboolean_t\t\tenc_no_cont_ev_mode_supported;\n \tboolean_t\t\tenc_rx_packed_stream_supported;\n \tboolean_t\t\tenc_rx_var_packed_stream_supported;\n \tboolean_t\t\tenc_rx_es_super_buffer_supported;\n@@ -2000,6 +2001,16 @@ efx_evq_nbufs(\n #define\tEFX_EVQ_FLAGS_NOTIFY_INTERRUPT\t(0x0)\t/* Interrupting (default) */\n #define\tEFX_EVQ_FLAGS_NOTIFY_DISABLED\t(0x4)\t/* Non-interrupting */\n \n+/*\n+ * Use the NO_CONT_EV RX event format, which allows the firmware to operate more\n+ * efficiently at high data rates. See SF-109306-TC 5.11 \"Events for RXQs in\n+ * NO_CONT_EV mode\".\n+ *\n+ * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,\n+ * which is the case when an event queue is set to THROUGHPUT mode.\n+ */\n+#define\tEFX_EVQ_FLAGS_NO_CONT_EV\t(0x10)\n+\n extern\t__checkReturn\tefx_rc_t\n efx_ev_qcreate(\n \t__in\t\tefx_nic_t *enp,\ndiff --git a/drivers/net/sfc/base/efx_impl.h b/drivers/net/sfc/base/efx_impl.h\nindex bad23f819..e2cdba692 100644\n--- a/drivers/net/sfc/base/efx_impl.h\n+++ b/drivers/net/sfc/base/efx_impl.h\n@@ -760,6 +760,7 @@ typedef struct efx_evq_rxq_state_s {\n \n struct efx_evq_s {\n \tuint32_t\t\t\tee_magic;\n+\tuint32_t\t\t\tee_flags;\n \tefx_nic_t\t\t\t*ee_enp;\n \tunsigned int\t\t\tee_index;\n \tunsigned int\t\t\tee_mask;\n@@ -778,8 +779,6 @@ struct efx_evq_s {\n #endif\t/* EFSYS_OPT_MCDI */\n \n \tefx_evq_rxq_state_t\t\tee_rxq_state[EFX_EV_RX_NLABELS];\n-\n-\tuint32_t\t\t\tee_flags;\n };\n \n #define\tEFX_EVQ_MAGIC\t0x08081997\n", "prefixes": [ "28/38" ] }