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GET /api/patches/50201/?format=api
{ "id": 50201, "url": "https://patches.dpdk.org/api/patches/50201/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1549556983-10896-8-git-send-email-arybchenko@solarflare.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1549556983-10896-8-git-send-email-arybchenko@solarflare.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1549556983-10896-8-git-send-email-arybchenko@solarflare.com", "date": "2019-02-07T16:29:12", "name": "[07/38] net/sfc/base: remove min/max defines for number of Rx descs", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6827d5495a7a130ba94cd6974bf579a8e064ec1b", "submitter": { "id": 607, "url": "https://patches.dpdk.org/api/people/607/?format=api", "name": "Andrew Rybchenko", "email": "arybchenko@solarflare.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1549556983-10896-8-git-send-email-arybchenko@solarflare.com/mbox/", "series": [ { "id": 3411, "url": "https://patches.dpdk.org/api/series/3411/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=3411", "date": "2019-02-07T16:29:05", "name": "net/sfc: update base driver", "version": 1, "mbox": "https://patches.dpdk.org/series/3411/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/50201/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/50201/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A78CC1B598;\n\tThu, 7 Feb 2019 17:30:43 +0100 (CET)", "from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com\n\t[67.231.154.164]) by dpdk.org (Postfix) with ESMTP id A18B31B580\n\tfor <dev@dpdk.org>; Thu, 7 Feb 2019 17:30:35 +0100 (CET)", "from webmail.solarflare.com (webmail.solarflare.com\n\t[12.187.104.26])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby mx1-us4.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with\n\tESMTPS id 73127B401B4; Thu, 7 Feb 2019 16:30:34 +0000 (UTC)", "from ocex03.SolarFlarecom.com (10.20.40.36) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:30 -0800", "from opal.uk.solarflarecom.com (10.17.10.1) by\n\tocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server\n\t(TLS) id\n\t15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:30 -0800", "from ukv-loginhost.uk.solarflarecom.com\n\t(ukv-loginhost.uk.solarflarecom.com [10.17.10.39])\n\tby opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id\n\tx17GUTjp015276; Thu, 7 Feb 2019 16:30:29 GMT", "from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1])\n\tby ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id\n\t63A861613F0; Thu, 7 Feb 2019 16:30:29 +0000 (GMT)" ], "X-Virus-Scanned": "Proofpoint Essentials engine", "From": "Andrew Rybchenko <arybchenko@solarflare.com>", "To": "<dev@dpdk.org>", "CC": "Igor Romanov <igor.romanov@oktetlabs.ru>", "Date": "Thu, 7 Feb 2019 16:29:12 +0000", "Message-ID": "<1549556983-10896-8-git-send-email-arybchenko@solarflare.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "References": "<1549556983-10896-1-git-send-email-arybchenko@solarflare.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-TM-AS-Product-Ver": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-TM-AS-Result": "No-3.182900-4.000000-10", "X-TMASE-MatchedRID": "t0V6V3Db6XA2jeY+Udg/Im4gfPq9dKeJ7qPKKDEKjrIs/uUAk6xP7ICu\n\tqghmtWfXmyr1EA+2/DDHdRuTe36BzNfV8L2ZOXrNyeVujmXuYYXEoDEGChh7CRS11FlOYRohS0e\n\tiOsrXcTgzkoS7NSD9vWJVHm/j9yxpSgu5Yo8VqDhDmVmiQbM5ql+iEcKpKdpuw01zN1c0miJRUx\n\tWIvi1rmuLzNWBegCW2wgn7iDBesS1YF3qW3Je6+z2akx8hsGa7joGo9Bys9BDNPyw27KIAX55rS\n\toTnjQ35jZnMJwYLFegmsYD3iS8m3qyAkCkhGgUlMwyGG7Ram2nH9bg6UMZEH71NuKS30BZnQIFI\n\tZLtsgG0DUH+nVLNyiCsqIP9TxvtJhyLR7CBmZbR+3BndfXUhXQ==", "X-TM-AS-User-Approved-Sender": "No", "X-TM-AS-User-Blocked-Sender": "No", "X-TMASE-Result": "10--3.182900-4.000000", "X-TMASE-Version": "SMEX-12.5.0.1300-8.5.1010-24412.006", "X-MDID": "1549557035-6QmrfS2q4B2V", "Subject": "[dpdk-dev] [PATCH 07/38] net/sfc/base: remove min/max defines for\n\tnumber of Rx descs", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Igor Romanov <igor.romanov@oktetlabs.ru>\n\nEF100/Riverhead has different min/max limits. So, these limits should\nbe a part of NIC config, not defines common for all NIC families.\n\nSigned-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>\nSigned-off-by: Andrew Rybchenko <arybchenko@solarflare.com>\n---\n drivers/net/sfc/base/ef10_impl.h | 3 +++\n drivers/net/sfc/base/ef10_rx.c | 9 +++++----\n drivers/net/sfc/base/efx.h | 10 ++++++++--\n drivers/net/sfc/base/efx_rx.c | 12 +++++++-----\n drivers/net/sfc/base/hunt_nic.c | 3 +++\n drivers/net/sfc/base/medford2_nic.c | 3 +++\n drivers/net/sfc/base/medford_nic.c | 3 +++\n drivers/net/sfc/base/siena_impl.h | 3 +++\n drivers/net/sfc/base/siena_nic.c | 3 +++\n 9 files changed, 38 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/sfc/base/ef10_impl.h b/drivers/net/sfc/base/ef10_impl.h\nindex 165a4013c..bf71b5a18 100644\n--- a/drivers/net/sfc/base/ef10_impl.h\n+++ b/drivers/net/sfc/base/ef10_impl.h\n@@ -11,6 +11,9 @@\n extern \"C\" {\n #endif\n \n+#define\tEF10_RXQ_MAXNDESCS\t4096\n+#define\tEF10_RXQ_MINNDESCS\t512\n+\n #define\tEF10_TXQ_MINNDESCS\t512\n \n /* Number of hardware PIO buffers (for compile-time resource dimensions) */\ndiff --git a/drivers/net/sfc/base/ef10_rx.c b/drivers/net/sfc/base/ef10_rx.c\nindex d18010d0f..1f2a6e009 100644\n--- a/drivers/net/sfc/base/ef10_rx.c\n+++ b/drivers/net/sfc/base/ef10_rx.c\n@@ -39,7 +39,7 @@ efx_mcdi_init_rxq(\n \tuint32_t dma_mode;\n \tboolean_t want_outer_classes;\n \n-\tEFSYS_ASSERT3U(ndescs, <=, EFX_RXQ_MAXNDESCS);\n+\tEFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs);\n \n \tif ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) {\n \t\trc = EINVAL;\n@@ -1012,11 +1012,12 @@ ef10_rx_qcreate(\n \tEFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);\n \tEFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);\n \n-\tEFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));\n-\tEFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));\n+\tEFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));\n+\tEFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));\n \n \tif (!ISP2(ndescs) ||\n-\t (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {\n+\t (ndescs < encp->enc_rxq_min_ndescs) ||\n+\t (ndescs > encp->enc_rxq_max_ndescs)) {\n \t\trc = EINVAL;\n \t\tgoto fail1;\n \t}\ndiff --git a/drivers/net/sfc/base/efx.h b/drivers/net/sfc/base/efx.h\nindex 5b5d790fc..06ce3d2fc 100644\n--- a/drivers/net/sfc/base/efx.h\n+++ b/drivers/net/sfc/base/efx.h\n@@ -1271,6 +1271,8 @@ typedef struct efx_nic_cfg_s {\n \tuint32_t\t\tenc_evq_limit;\n \tuint32_t\t\tenc_txq_limit;\n \tuint32_t\t\tenc_rxq_limit;\n+\tuint32_t\t\tenc_rxq_max_ndescs;\n+\tuint32_t\t\tenc_rxq_min_ndescs;\n \tuint32_t\t\tenc_txq_max_ndescs;\n \tuint32_t\t\tenc_txq_min_ndescs;\n \tuint32_t\t\tenc_buftbl_limit;\n@@ -2462,8 +2464,12 @@ efx_pseudo_hdr_pkt_length_get(\n \t__in\t\tuint8_t *buffer,\n \t__out\t\tuint16_t *pkt_lengthp);\n \n-#define\tEFX_RXQ_MAXNDESCS\t\t4096\n-#define\tEFX_RXQ_MINNDESCS\t\t512\n+/*\n+ * These symbols are deprecated and will be removed.\n+ * Use the fields from efx_nic_cfg_t instead.\n+ */\n+#define EFX_RXQ_MAXNDESCS 4096\n+#define EFX_RXQ_MINNDESCS 512\n \n #define\tEFX_RXQ_SIZE(_ndescs)\t\t((_ndescs) * sizeof (efx_qword_t))\n #define\tEFX_RXQ_NBUFS(_ndescs)\t\t(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)\ndiff --git a/drivers/net/sfc/base/efx_rx.c b/drivers/net/sfc/base/efx_rx.c\nindex afa3ac588..332f8c800 100644\n--- a/drivers/net/sfc/base/efx_rx.c\n+++ b/drivers/net/sfc/base/efx_rx.c\n@@ -1590,11 +1590,12 @@ siena_rx_qcreate(\n \tEFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);\n \tEFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);\n \n-\tEFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));\n-\tEFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));\n+\tEFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));\n+\tEFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));\n \n \tif (!ISP2(ndescs) ||\n-\t (ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {\n+\t (ndescs < encp->enc_rxq_min_ndescs) ||\n+\t (ndescs > encp->enc_rxq_max_ndescs)) {\n \t\trc = EINVAL;\n \t\tgoto fail1;\n \t}\n@@ -1602,9 +1603,10 @@ siena_rx_qcreate(\n \t\trc = EINVAL;\n \t\tgoto fail2;\n \t}\n-\tfor (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);\n+\tfor (size = 0;\n+\t (1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs;\n \t size++)\n-\t\tif ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))\n+\t\tif ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs)\n \t\t\tbreak;\n \tif (id + (1 << size) >= encp->enc_buftbl_limit) {\n \t\trc = EINVAL;\ndiff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c\nindex 6605cfce4..ae8a0085e 100644\n--- a/drivers/net/sfc/base/hunt_nic.c\n+++ b/drivers/net/sfc/base/hunt_nic.c\n@@ -190,6 +190,9 @@ hunt_board_cfg(\n \tencp->enc_rx_buf_align_start = 1;\n \tencp->enc_rx_buf_align_end = 64; /* RX DMA end padding */\n \n+\tencp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;\n+\tencp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;\n+\n \t/*\n \t * The workaround for bug35388 uses the top bit of transmit queue\n \t * descriptor writes, preventing the use of 4096 descriptor TXQs.\ndiff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c\nindex 020c37fd9..87c97b5db 100644\n--- a/drivers/net/sfc/base/medford2_nic.c\n+++ b/drivers/net/sfc/base/medford2_nic.c\n@@ -114,6 +114,9 @@ medford2_board_cfg(\n \t}\n \tencp->enc_rx_buf_align_end = end_padding;\n \n+\tencp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;\n+\tencp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;\n+\n \t/*\n \t * The maximum supported transmit queue size is 2048. TXQs with 4096\n \t * descriptors are not supported as the top bit is used for vfifo\ndiff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c\nindex 171e39b03..c5d919742 100644\n--- a/drivers/net/sfc/base/medford_nic.c\n+++ b/drivers/net/sfc/base/medford_nic.c\n@@ -112,6 +112,9 @@ medford_board_cfg(\n \t}\n \tencp->enc_rx_buf_align_end = end_padding;\n \n+\tencp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;\n+\tencp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;\n+\n \t/*\n \t * The maximum supported transmit queue size is 2048. TXQs with 4096\n \t * descriptors are not supported as the top bit is used for vfifo\ndiff --git a/drivers/net/sfc/base/siena_impl.h b/drivers/net/sfc/base/siena_impl.h\nindex 549712377..90f71d9c4 100644\n--- a/drivers/net/sfc/base/siena_impl.h\n+++ b/drivers/net/sfc/base/siena_impl.h\n@@ -27,6 +27,9 @@ extern \"C\" {\n #define\tSIENA_TXQ_MAXNDESCS\t4096\n #define\tSIENA_TXQ_MINNDESCS\t512\n \n+#define\tSIENA_RXQ_MAXNDESCS\t4096\n+#define\tSIENA_RXQ_MINNDESCS\t512\n+\n #define\tSIENA_NVRAM_CHUNK 0x80\n \n \ndiff --git a/drivers/net/sfc/base/siena_nic.c b/drivers/net/sfc/base/siena_nic.c\nindex 0f02195c0..341abd8f6 100644\n--- a/drivers/net/sfc/base/siena_nic.c\n+++ b/drivers/net/sfc/base/siena_nic.c\n@@ -149,6 +149,9 @@ siena_board_cfg(\n \tencp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);\n \tencp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);\n \n+\tencp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;\n+\tencp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;\n+\n \tencp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;\n \tencp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;\n \n", "prefixes": [ "07/38" ] }