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GET /api/patches/49944/?format=api
{ "id": 49944, "url": "https://patches.dpdk.org/api/patches/49944/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20190118102930.27487-1-shshaikh@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190118102930.27487-1-shshaikh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190118102930.27487-1-shshaikh@marvell.com", "date": "2019-01-18T10:29:29", "name": "[1/2] net/qede: fix performance bottleneck in Rx path", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "83d5cd7f90d68264be613a6a54526c718e64b171", "submitter": { "id": 1210, "url": "https://patches.dpdk.org/api/people/1210/?format=api", "name": "Shahed Shaikh", "email": "shshaikh@marvell.com" }, "delegate": { "id": 319, "url": "https://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20190118102930.27487-1-shshaikh@marvell.com/mbox/", "series": [ { "id": 3258, "url": "https://patches.dpdk.org/api/series/3258/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=3258", "date": "2019-01-18T10:29:29", "name": "[1/2] net/qede: fix performance bottleneck in Rx path", "version": 1, "mbox": "https://patches.dpdk.org/series/3258/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/49944/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/49944/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E91FC1041;\n\tFri, 18 Jan 2019 11:29:36 +0100 (CET)", "from NAM02-BL2-obe.outbound.protection.outlook.com\n\t(mail-eopbgr750053.outbound.protection.outlook.com [40.107.75.53])\n\tby dpdk.org (Postfix) with ESMTP id D7FFF160;\n\tFri, 18 Jan 2019 11:29:35 +0100 (CET)", "from DM5PR07CA0070.namprd07.prod.outlook.com (2603:10b6:4:ad::35)\n\tby\n\tBYAPR07MB4759.namprd07.prod.outlook.com (2603:10b6:a02:f0::23) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1537.25; Fri, 18 Jan 2019 10:29:34 +0000", "from BY2NAM05FT026.eop-nam05.prod.protection.outlook.com\n\t(2a01:111:f400:7e52::202) by DM5PR07CA0070.outlook.office365.com\n\t(2603:10b6:4:ad::35) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.1537.26 via\n\tFrontend Transport; Fri, 18 Jan 2019 10:29:34 +0000", "from CAEXCH02.caveonetworks.com (199.233.58.38) by\n\tBY2NAM05FT026.mail.protection.outlook.com (10.152.100.163) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA) id\n\t15.20.1558.9 via Frontend Transport; Fri, 18 Jan 2019 10:29:33 +0000", "from dut1171.mv.qlogic.com (10.112.88.18) by\n\tCAEXCH02.caveonetworks.com (10.67.98.110) with Microsoft SMTP Server\n\t(TLS) id 14.2.347.0; Fri, 18 Jan 2019 02:29:33 -0800", "from dut1171.mv.qlogic.com (localhost [127.0.0.1])\tby\n\tdut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id x0IATWgK027524;\n\tFri, 18 Jan 2019 02:29:32 -0800", "(from root@localhost)\tby dut1171.mv.qlogic.com\n\t(8.14.7/8.14.7/Submit) id x0IATWP9027523;\n\tFri, 18 Jan 2019 02:29:32 -0800" ], "Authentication-Results": "spf=fail (sender IP is 199.233.58.38)\n\tsmtp.mailfrom=marvell.com; dpdk.org; dkim=none (message not signed)\n\theader.d=none; dpdk.org;\n\tdmarc=fail action=none header.from=marvell.com; ", "Received-SPF": "Fail (protection.outlook.com: domain of marvell.com does not\n\tdesignate 199.233.58.38 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=199.233.58.38; helo=CAEXCH02.caveonetworks.com;", "From": "Shahed Shaikh <shshaikh@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<ferruh.yigit@intel.com>, <stable@dpdk.org>", "Date": "Fri, 18 Jan 2019 02:29:29 -0800", "Message-ID": "<20190118102930.27487-1-shshaikh@marvell.com>", "X-Mailer": "git-send-email 2.12.0", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131922809741216247;\n\t(abac79dc-c90b-41ba-8033-08d666125e47);\n\t(abac79dc-c90b-41ba-8033-08d666125e47)", "X-Forefront-Antispam-Report": "CIP:199.233.58.38; IPV:CAL; CTRY:US; EFV:NLI;\n\tSFV:NSPM;\n\tSFS:(10009020)(396003)(136003)(376002)(346002)(39860400002)(2980300002)(1110001)(1109001)(339900001)(199004)(189003)(8936002)(47776003)(50466002)(5660300001)(8676002)(305945005)(14444005)(51416003)(2906002)(498600001)(26826003)(87636003)(81166006)(6916009)(336012)(48376002)(126002)(476003)(50226002)(42186006)(68736007)(486006)(316002)(26005)(81156014)(16586007)(54906003)(2616005)(1076003)(105606002)(36906005)(106466001)(85426001)(2351001)(36756003)(80596001)(97736004)(69596002)(6666004)(356004)(53936002)(450100002)(86362001)(4326008);\n\tDIR:OUT; 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PCL:0;\n\tRULEID:(2390118)(7020095)(5600109)(711020)(2017052603328);\n\tSRVR:BYAPR07MB4759; ", "X-MS-TrafficTypeDiagnostic": "BYAPR07MB4759:", "X-Microsoft-Antispam-PRVS": "<BYAPR07MB47592B106BC0694E90C4A156D39C0@BYAPR07MB4759.namprd07.prod.outlook.com>", "X-Forefront-PRVS": "0921D55E4F", "X-Microsoft-Antispam-Message-Info": "GWyHq9uxtdWeEu9bQ5u599cLTz7p4nq4l74wiOHEnnUZa+3ilxNEAnPCHLjGgsnVWPGkOAZd7RYp9/XvaBa9O4O8ynwANsCpWuoRiRijF87B7YBg9qixz3o6g7WJUoGKRB+oXfThIuc5whLhH12QhLHlAgNbSaPbdu7tgHJH22oknZmGpminvWuzg8R9DdQsFmDynTuSN/i7BWG3UO+wemK+6MzeyYPjzCKZlNRumeO3WBxm77YfhCObZtOG2G4r0HpBjyH6aix0POR5BBgHxkieoKyWIELGbcqXukDwMLJmFfz8IcJuiRMIpujCVI6f9JmTjta5T9Nuz7Fd2vjCo8JuW/1lShKXXtfu7WSl/FYPI5bmql7+ZCtmjnPOdphXJj0annDUZ7cmVKMVzMilPHglsqdJqNE51uSXQ/SsuV8=", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Jan 2019 10:29:33.7622\n\t(UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "dd2cbb83-7f03-41c6-9e42-08d67d2fd6d0", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[199.233.58.38]; \n\tHelo=[CAEXCH02.caveonetworks.com]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR07MB4759", "Subject": "[dpdk-dev] [PATCH 1/2] net/qede: fix performance bottleneck in Rx\n\tpath", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Allocating replacement buffer per received packet is expensive.\nInstead, process received packets first and allocate\nreplacement buffers in bulk later.\n\nThis improves performance by ~25% in terms of PPS on AMD\nplatforms.\n\nFixes: 2ea6f76aff40 (\"qede: add core driver\")\nCc: stable@dpdk.org\n\nSigned-off-by: Shahed Shaikh <shshaikh@marvell.com>\n---\n drivers/net/qede/qede_rxtx.c | 97 +++++++++++++++++++++++++++++++++-----------\n drivers/net/qede/qede_rxtx.h | 2 +\n 2 files changed, 75 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c\nindex 0e33be1..684c4ae 100644\n--- a/drivers/net/qede/qede_rxtx.c\n+++ b/drivers/net/qede/qede_rxtx.c\n@@ -35,6 +35,52 @@ static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)\n \treturn 0;\n }\n \n+#define QEDE_MAX_BULK_ALLOC_COUNT 512\n+\n+static inline int qede_alloc_rx_bulk_mbufs(struct qede_rx_queue *rxq, int count)\n+{\n+\tvoid *obj_p[QEDE_MAX_BULK_ALLOC_COUNT] __rte_cache_aligned;\n+\tstruct rte_mbuf *mbuf = NULL;\n+\tstruct eth_rx_bd *rx_bd;\n+\tdma_addr_t mapping;\n+\tint i, ret = 0;\n+\tuint16_t idx;\n+\n+\tidx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);\n+\n+\tif (count > QEDE_MAX_BULK_ALLOC_COUNT)\n+\t\tcount = QEDE_MAX_BULK_ALLOC_COUNT;\n+\n+\tret = rte_mempool_get_bulk(rxq->mb_pool, obj_p, count);\n+\tif (unlikely(ret)) {\n+\t\tPMD_RX_LOG(ERR, rxq,\n+\t\t\t \"Failed to allocate %d rx buffers \"\n+\t\t\t \"sw_rx_prod %u sw_rx_cons %u mp entries %u free %u\",\n+\t\t\t count, idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),\n+\t\t\t rte_mempool_avail_count(rxq->mb_pool),\n+\t\t\t rte_mempool_in_use_count(rxq->mb_pool));\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tfor (i = 0; i < count; i++) {\n+\t\tmbuf = obj_p[i];\n+\t\tif (likely(i < count - 1))\n+\t\t\trte_prefetch0(obj_p[i + 1]);\n+\n+\t\tidx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);\n+\t\trxq->sw_rx_ring[idx].mbuf = mbuf;\n+\t\trxq->sw_rx_ring[idx].page_offset = 0;\n+\t\tmapping = rte_mbuf_data_iova_default(mbuf);\n+\t\trx_bd = (struct eth_rx_bd *)\n+\t\t\tecore_chain_produce(&rxq->rx_bd_ring);\n+\t\trx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));\n+\t\trx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));\n+\t\trxq->sw_rx_prod++;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* Criterias for calculating Rx buffer size -\n * 1) rx_buf_size should not exceed the size of mbuf\n * 2) In scattered_rx mode - minimum rx_buf_size should be\n@@ -1131,7 +1177,7 @@ qede_reuse_page(__rte_unused struct qede_dev *qdev,\n \t\tstruct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)\n {\n \tstruct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);\n-\tuint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);\n+\tuint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);\n \tstruct qede_rx_entry *curr_prod;\n \tdma_addr_t new_mapping;\n \n@@ -1364,7 +1410,6 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \tuint8_t bitfield_val;\n #endif\n \tuint8_t tunn_parse_flag;\n-\tuint8_t j;\n \tstruct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;\n \tuint64_t ol_flags;\n \tuint32_t packet_type;\n@@ -1373,6 +1418,7 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \tuint8_t offset, tpa_agg_idx, flags;\n \tstruct qede_agg_info *tpa_info = NULL;\n \tuint32_t rss_hash;\n+\tint rx_alloc_count = 0;\n \n \thw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);\n \tsw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);\n@@ -1382,6 +1428,25 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \tif (hw_comp_cons == sw_comp_cons)\n \t\treturn 0;\n \n+\t/* Allocate buffers that we used in previous loop */\n+\tif (rxq->rx_alloc_count) {\n+\t\tif (unlikely(qede_alloc_rx_bulk_mbufs(rxq,\n+\t\t\t rxq->rx_alloc_count))) {\n+\t\t\tstruct rte_eth_dev *dev;\n+\n+\t\t\tPMD_RX_LOG(ERR, rxq,\n+\t\t\t\t \"New buffer allocation failed,\"\n+\t\t\t\t \"dropping incoming packetn\");\n+\t\t\tdev = &rte_eth_devices[rxq->port_id];\n+\t\t\tdev->data->rx_mbuf_alloc_failed +=\n+\t\t\t\t\t\t\trxq->rx_alloc_count;\n+\t\t\trxq->rx_alloc_errors += rxq->rx_alloc_count;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tqede_update_rx_prod(qdev, rxq);\n+\t\trxq->rx_alloc_count = 0;\n+\t}\n+\n \twhile (sw_comp_cons != hw_comp_cons) {\n \t\tol_flags = 0;\n \t\tpacket_type = RTE_PTYPE_UNKNOWN;\n@@ -1553,16 +1618,7 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t\trx_mb->hash.rss = rss_hash;\n \t\t}\n \n-\t\tif (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {\n-\t\t\tPMD_RX_LOG(ERR, rxq,\n-\t\t\t\t \"New buffer allocation failed,\"\n-\t\t\t\t \"dropping incoming packet\\n\");\n-\t\t\tqede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);\n-\t\t\trte_eth_devices[rxq->port_id].\n-\t\t\t data->rx_mbuf_alloc_failed++;\n-\t\t\trxq->rx_alloc_errors++;\n-\t\t\tbreak;\n-\t\t}\n+\t\trx_alloc_count++;\n \t\tqede_rx_bd_ring_consume(rxq);\n \n \t\tif (!tpa_start_flg && fp_cqe->bd_num > 1) {\n@@ -1574,17 +1630,9 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t\tif (qede_process_sg_pkts(p_rxq, seg1, num_segs,\n \t\t\t\t\t\t pkt_len - len))\n \t\t\t\tgoto next_cqe;\n-\t\t\tfor (j = 0; j < num_segs; j++) {\n-\t\t\t\tif (qede_alloc_rx_buffer(rxq)) {\n-\t\t\t\t\tPMD_RX_LOG(ERR, rxq,\n-\t\t\t\t\t\t\"Buffer allocation failed\");\n-\t\t\t\t\trte_eth_devices[rxq->port_id].\n-\t\t\t\t\t\tdata->rx_mbuf_alloc_failed++;\n-\t\t\t\t\trxq->rx_alloc_errors++;\n-\t\t\t\t\tbreak;\n-\t\t\t\t}\n-\t\t\t\trxq->rx_segs++;\n-\t\t\t}\n+\n+\t\t\trx_alloc_count += num_segs;\n+\t\t\trxq->rx_segs += num_segs;\n \t\t}\n \t\trxq->rx_segs++; /* for the first segment */\n \n@@ -1626,7 +1674,8 @@ qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)\n \t\t}\n \t}\n \n-\tqede_update_rx_prod(qdev, rxq);\n+\t/* Request number of bufferes to be allocated in next loop */\n+\trxq->rx_alloc_count = rx_alloc_count;\n \n \trxq->rcv_pkts += rx_pkt;\n \ndiff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h\nindex 454daa0..5b249cb 100644\n--- a/drivers/net/qede/qede_rxtx.h\n+++ b/drivers/net/qede/qede_rxtx.h\n@@ -192,6 +192,8 @@ struct qede_rx_queue {\n \tuint16_t queue_id;\n \tuint16_t port_id;\n \tuint16_t rx_buf_size;\n+\tuint16_t rx_alloc_count;\n+\tuint16_t unused;\n \tuint64_t rcv_pkts;\n \tuint64_t rx_segs;\n \tuint64_t rx_hw_errors;\n", "prefixes": [ "1/2" ] }