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GET /api/patches/48983/?format=api
{ "id": 48983, "url": "https://patches.dpdk.org/api/patches/48983/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-16-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1545032259-77179-16-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-16-git-send-email-wenzhuo.lu@intel.com", "date": "2018-12-17T07:37:23", "name": "[v5,15/31] net/ice: support device initialization", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7a0dda1e71c03606ab55bc8c1d4b313a5248b6be", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-16-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 2824, "url": "https://patches.dpdk.org/api/series/2824/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824", "date": "2018-12-17T07:37:08", "name": "A new net PMD - ICE", "version": 5, "mbox": "https://patches.dpdk.org/series/2824/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/48983/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/48983/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id C575A1B8CA;\n\tMon, 17 Dec 2018 08:33:23 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id E51A81B605\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:33:12 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:33:11 -0800", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:33:11 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899241\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Wenzhuo Lu <wenzhuo.lu@intel.com>, Qiming Yang <qiming.yang@intel.com>, \n\tXiaoyun Li <xiaoyun.li@intel.com>, Jingjing Wu <jingjing.wu@intel.com>", "Date": "Mon, 17 Dec 2018 15:37:23 +0800", "Message-Id": "<1545032259-77179-16-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v5 15/31] net/ice: support device initialization", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Update the documents too.\n\nSigned-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\nSigned-off-by: Xiaoyun Li <xiaoyun.li@intel.com>\nSigned-off-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n MAINTAINERS | 2 +\n config/common_base | 7 +\n doc/guides/nics/features/ice.ini | 11 +\n doc/guides/nics/ice.rst | 80 ++++\n doc/guides/nics/index.rst | 1 +\n doc/guides/rel_notes/release_19_02.rst | 5 +\n drivers/net/Makefile | 1 +\n drivers/net/ice/Makefile | 54 +++\n drivers/net/ice/base/meson.build | 27 ++\n drivers/net/ice/ice_ethdev.c | 636 ++++++++++++++++++++++++++++++++\n drivers/net/ice/ice_ethdev.h | 305 +++++++++++++++\n drivers/net/ice/ice_logs.h | 45 +++\n drivers/net/ice/ice_rxtx.h | 117 ++++++\n drivers/net/ice/meson.build | 12 +\n drivers/net/ice/rte_pmd_ice_version.map | 4 +\n drivers/net/meson.build | 1 +\n mk/rte.app.mk | 1 +\n 17 files changed, 1309 insertions(+)\n create mode 100644 doc/guides/nics/features/ice.ini\n create mode 100644 doc/guides/nics/ice.rst\n create mode 100644 drivers/net/ice/Makefile\n create mode 100644 drivers/net/ice/base/meson.build\n create mode 100644 drivers/net/ice/ice_ethdev.c\n create mode 100644 drivers/net/ice/ice_ethdev.h\n create mode 100644 drivers/net/ice/ice_logs.h\n create mode 100644 drivers/net/ice/ice_rxtx.h\n create mode 100644 drivers/net/ice/meson.build\n create mode 100644 drivers/net/ice/rte_pmd_ice_version.map", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 37f3bf7..cdb18e0 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -598,6 +598,8 @@ M: Qiming Yang <qiming.yang@intel.com>\n M: Wenzhuo Lu <wenzhuo.lu@intel.com>\n T: git://dpdk.org/next/dpdk-next-net-intel\n F: drivers/net/ice/\n+F: doc/guides/nics/ice.rst\n+F: doc/guides/nics/features/ice.ini\n \n Marvell mvpp2\n M: Tomasz Duszynski <tdu@semihalf.com>\ndiff --git a/config/common_base b/config/common_base\nindex d12ae98..872f440 100644\n--- a/config/common_base\n+++ b/config/common_base\n@@ -297,6 +297,13 @@ CONFIG_RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE=y\n CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR=y\n \n #\n+# Compile burst-oriented ICE PMD driver\n+#\n+CONFIG_RTE_LIBRTE_ICE_PMD=y\n+CONFIG_RTE_LIBRTE_ICE_DEBUG_RX=n\n+CONFIG_RTE_LIBRTE_ICE_DEBUG_TX=n\n+CONFIG_RTE_LIBRTE_ICE_DEBUG_TX_FREE=n\n+\n # Compile burst-oriented AVF PMD driver\n #\n CONFIG_RTE_LIBRTE_AVF_PMD=y\ndiff --git a/doc/guides/nics/features/ice.ini b/doc/guides/nics/features/ice.ini\nnew file mode 100644\nindex 0000000..085e848\n--- /dev/null\n+++ b/doc/guides/nics/features/ice.ini\n@@ -0,0 +1,11 @@\n+;\n+; Supported features of the 'ice' network poll mode driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+BSD nic_uio = Y\n+Linux UIO = Y\n+Linux VFIO = Y\n+x86-32 = Y\n+x86-64 = Y\ndiff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst\nnew file mode 100644\nindex 0000000..946ed04\n--- /dev/null\n+++ b/doc/guides/nics/ice.rst\n@@ -0,0 +1,80 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2018 Intel Corporation.\n+\n+ICE Poll Mode Driver\n+======================\n+\n+The ice PMD (librte_pmd_ice) provides poll mode driver support for\n+10/25 Gbps Intel® Ethernet 810 Series Network Adapters based on\n+the Intel Ethernet Controller E810.\n+\n+\n+Prerequisites\n+-------------\n+\n+- Identifying your adapter using `Intel Support\n+ <http://www.intel.com/support>`_ and get the latest NVM/FW images.\n+\n+- Follow the DPDK :ref:`Getting Started Guide for Linux <linux_gsg>` to setup the basic DPDK environment.\n+\n+- To get better performance on Intel platforms, please follow the \"How to get best performance with NICs on Intel platforms\"\n+ section of the :ref:`Getting Started Guide for Linux <linux_gsg>`.\n+\n+\n+Pre-Installation Configuration\n+------------------------------\n+\n+Config File Options\n+~~~~~~~~~~~~~~~~~~~\n+\n+The following options can be modified in the ``config`` file.\n+Please note that enabling debugging options may affect system performance.\n+\n+- ``CONFIG_RTE_LIBRTE_ICE_PMD`` (default ``y``)\n+\n+ Toggle compilation of the ``librte_pmd_ice`` driver.\n+\n+- ``CONFIG_RTE_LIBRTE_ICE_DEBUG_*`` (default ``n``)\n+\n+ Toggle display of generic debugging messages.\n+\n+Runtime Config Options\n+~~~~~~~~~~~~~~~~~~~~~~\n+\n+- ``Maximum Number of Queue Pairs``\n+\n+ The maximum number of queue pairs is decided by HW. If not configured, APP\n+ uses the number from HW. Users can check the number by calling the API\n+ ``rte_eth_dev_info_get``.\n+ If users want to limit the number of queues, they can set a smaller number\n+ using EAL parameter like ``max_queue_pair_num=n``.\n+\n+\n+Driver compilation and testing\n+------------------------------\n+\n+Refer to the document :ref:`compiling and testing a PMD for a NIC <pmd_build_and_test>`\n+for details.\n+\n+\n+Limitations or Known issues\n+---------------------------\n+\n+19.02 limitation\n+~~~~~~~~~~~~~~~~\n+\n+Ice code released in 19.02 is for evaluation only.\n+\n+\n+Promiscuous mode not supported\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+As promiscuous mode is not supported as this stage, a port can only receive the\n+packets which destination MAC address is this port's own.\n+\n+\n+TX anti-spoofing cannot be disabled\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+TX anti-spoofing is enabled by default. At this stage it's not supported to\n+disable it. So any TX packet which source MAC address is not this port's own\n+will be dropped by HW. It means io-fwd is not supported now. Recommand to use\n+MAC-fwd for evaluation.\ndiff --git a/doc/guides/nics/index.rst b/doc/guides/nics/index.rst\nindex 1e46705..a205f15 100644\n--- a/doc/guides/nics/index.rst\n+++ b/doc/guides/nics/index.rst\n@@ -26,6 +26,7 @@ Network Interface Controller Drivers\n enic\n fm10k\n i40e\n+ ice\n ifc\n igb\n ixgbe\ndiff --git a/doc/guides/rel_notes/release_19_02.rst b/doc/guides/rel_notes/release_19_02.rst\nindex a94fa86..ca560b1 100644\n--- a/doc/guides/rel_notes/release_19_02.rst\n+++ b/doc/guides/rel_notes/release_19_02.rst\n@@ -54,6 +54,11 @@ New Features\n Also, make sure to start the actual text at the margin.\n =========================================================\n \n+* **Added ICE net PMD**\n+\n+ Added the new ``ice`` net driver for Intel® Ethernet Network Adapters E810.\n+ See the :doc:`../nics/ice` NIC guide for more details on this new driver.\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/Makefile b/drivers/net/Makefile\nindex c0386fe..670d7f7 100644\n--- a/drivers/net/Makefile\n+++ b/drivers/net/Makefile\n@@ -30,6 +30,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic\n DIRS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe\n DIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k\n DIRS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += i40e\n+DIRS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice\n DIRS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += ixgbe\n DIRS-$(CONFIG_RTE_LIBRTE_LIO_PMD) += liquidio\n DIRS-$(CONFIG_RTE_LIBRTE_MLX4_PMD) += mlx4\ndiff --git a/drivers/net/ice/Makefile b/drivers/net/ice/Makefile\nnew file mode 100644\nindex 0000000..70f23e3\n--- /dev/null\n+++ b/drivers/net/ice/Makefile\n@@ -0,0 +1,54 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Intel Corporation\n+\n+include $(RTE_SDK)/mk/rte.vars.mk\n+\n+#\n+# library name\n+#\n+LIB = librte_pmd_ice.a\n+\n+CFLAGS += -O3\n+CFLAGS += $(WERROR_FLAGS)\n+\n+LDLIBS += -lrte_eal -lrte_ethdev -lrte_kvargs -lrte_bus_pci\n+\n+EXPORT_MAP := rte_pmd_ice_version.map\n+\n+LIBABIVER := 1\n+\n+#\n+# Add extra flags for base driver files (also known as shared code)\n+# to disable warnings\n+#\n+ifeq ($(CONFIG_RTE_TOOLCHAIN_ICC),y)\n+CFLAGS_BASE_DRIVER +=\n+else ifeq ($(CONFIG_RTE_TOOLCHAIN_CLANG),y)\n+CFLAGS_BASE_DRIVER += -Wno-unused-parameter\n+CFLAGS_BASE_DRIVER += -Wno-unused-variable\n+else\n+CFLAGS_BASE_DRIVER += -Wno-unused-parameter\n+CFLAGS_BASE_DRIVER += -Wno-unused-variable\n+\n+ifeq ($(shell test $(GCC_VERSION) -ge 44 && echo 1), 1)\n+CFLAGS_BASE_DRIVER += -Wno-unused-but-set-variable\n+endif\n+\n+endif\n+OBJS_BASE_DRIVER=$(patsubst %.c,%.o,$(notdir $(wildcard $(SRCDIR)/base/*.c)))\n+$(foreach obj, $(OBJS_BASE_DRIVER), $(eval CFLAGS_$(obj)+=$(CFLAGS_BASE_DRIVER)))\n+\n+VPATH += $(SRCDIR)/base\n+\n+#\n+# all source are stored in SRCS-y\n+#\n+SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_controlq.c\n+SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_common.c\n+SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_sched.c\n+SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_switch.c\n+SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_nvm.c\n+\n+SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += ice_ethdev.c\n+\n+include $(RTE_SDK)/mk/rte.lib.mk\ndiff --git a/drivers/net/ice/base/meson.build b/drivers/net/ice/base/meson.build\nnew file mode 100644\nindex 0000000..0cfc8cd\n--- /dev/null\n+++ b/drivers/net/ice/base/meson.build\n@@ -0,0 +1,27 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Intel Corporation\n+\n+sources = [\n+\t'ice_controlq.c',\n+\t'ice_common.c',\n+\t'ice_sched.c',\n+\t'ice_switch.c',\n+\t'ice_nvm.c',\n+]\n+\n+error_cflags = ['-Wno-unused-value',\n+\t\t'-Wno-unused-but-set-variable',\n+\t\t'-Wno-unused-variable',\n+]\n+c_args = cflags\n+\n+foreach flag: error_cflags\n+\tif cc.has_argument(flag)\n+\t\tc_args += flag\n+\tendif\n+endforeach\n+\n+base_lib = static_library('ice_base', sources,\n+\tdependencies: static_rte_eal,\n+\tc_args: c_args)\n+base_objs = base_lib.extract_all_objects()\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nnew file mode 100644\nindex 0000000..4f0c819\n--- /dev/null\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -0,0 +1,636 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#include <rte_ethdev_pci.h>\n+\n+#include \"base/ice_sched.h\"\n+#include \"ice_ethdev.h\"\n+#include \"ice_rxtx.h\"\n+\n+#define ICE_MAX_QP_NUM \"max_queue_pair_num\"\n+#define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100\n+\n+int ice_logtype_init;\n+int ice_logtype_driver;\n+\n+static const struct rte_pci_id pci_id_ice_map[] = {\n+\t{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },\n+\t{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },\n+\t{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },\n+\t{ .vendor_id = 0, /* sentinel */ },\n+};\n+\n+static const struct eth_dev_ops ice_eth_dev_ops = {\n+\t.dev_configure = NULL,\n+};\n+\n+static void\n+ice_init_controlq_parameter(struct ice_hw *hw)\n+{\n+\t/* fields for adminq */\n+\thw->adminq.num_rq_entries = ICE_ADMINQ_LEN;\n+\thw->adminq.num_sq_entries = ICE_ADMINQ_LEN;\n+\thw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;\n+\thw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;\n+\n+\t/* fields for mailboxq, DPDK used as PF host */\n+\thw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;\n+\thw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;\n+\thw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;\n+\thw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;\n+}\n+\n+static int\n+ice_check_qp_num(const char *key, const char *qp_value,\n+\t\t __rte_unused void *opaque)\n+{\n+\tchar *end = NULL;\n+\tint num = 0;\n+\n+\twhile (isblank(*qp_value))\n+\t\tqp_value++;\n+\n+\tnum = strtoul(qp_value, &end, 10);\n+\n+\tif (!num || (*end == '-') || errno) {\n+\t\tPMD_DRV_LOG(WARNING, \"invalid value:\\\"%s\\\" for key:\\\"%s\\\", \"\n+\t\t\t \"value must be > 0\",\n+\t\t\t qp_value, key);\n+\t\treturn -1;\n+\t}\n+\n+\treturn num;\n+}\n+\n+static int\n+ice_config_max_queue_pair_num(struct rte_devargs *devargs)\n+{\n+\tstruct rte_kvargs *kvlist;\n+\tconst char *queue_num_key = ICE_MAX_QP_NUM;\n+\tint ret;\n+\n+\tif (!devargs)\n+\t\treturn 0;\n+\n+\tkvlist = rte_kvargs_parse(devargs->args, NULL);\n+\tif (!kvlist)\n+\t\treturn 0;\n+\n+\tif (!rte_kvargs_count(kvlist, queue_num_key)) {\n+\t\trte_kvargs_free(kvlist);\n+\t\treturn 0;\n+\t}\n+\n+\tif (rte_kvargs_process(kvlist, queue_num_key,\n+\t\t\t ice_check_qp_num, NULL) < 0) {\n+\t\trte_kvargs_free(kvlist);\n+\t\treturn 0;\n+\t}\n+\tret = rte_kvargs_process(kvlist, queue_num_key,\n+\t\t\t\t ice_check_qp_num, NULL);\n+\trte_kvargs_free(kvlist);\n+\n+\treturn ret;\n+}\n+\n+static int\n+ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,\n+\t\t uint32_t num)\n+{\n+\tstruct pool_entry *entry;\n+\n+\tif (!pool || !num)\n+\t\treturn -EINVAL;\n+\n+\tentry = rte_zmalloc(NULL, sizeof(*entry), 0);\n+\tif (!entry) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t \"Failed to allocate memory for resource pool\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* queue heap initialize */\n+\tpool->num_free = num;\n+\tpool->num_alloc = 0;\n+\tpool->base = base;\n+\tLIST_INIT(&pool->alloc_list);\n+\tLIST_INIT(&pool->free_list);\n+\n+\t/* Initialize element */\n+\tentry->base = 0;\n+\tentry->len = num;\n+\n+\tLIST_INSERT_HEAD(&pool->free_list, entry, next);\n+\treturn 0;\n+}\n+\n+static int\n+ice_res_pool_alloc(struct ice_res_pool_info *pool,\n+\t\t uint16_t num)\n+{\n+\tstruct pool_entry *entry, *valid_entry;\n+\n+\tif (!pool || !num) {\n+\t\tPMD_INIT_LOG(ERR, \"Invalid parameter\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (pool->num_free < num) {\n+\t\tPMD_INIT_LOG(ERR, \"No resource. ask:%u, available:%u\",\n+\t\t\t num, pool->num_free);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tvalid_entry = NULL;\n+\t/* Lookup in free list and find most fit one */\n+\tLIST_FOREACH(entry, &pool->free_list, next) {\n+\t\tif (entry->len >= num) {\n+\t\t\t/* Find best one */\n+\t\t\tif (entry->len == num) {\n+\t\t\t\tvalid_entry = entry;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (!valid_entry ||\n+\t\t\t valid_entry->len > entry->len)\n+\t\t\t\tvalid_entry = entry;\n+\t\t}\n+\t}\n+\n+\t/* Not find one to satisfy the request, return */\n+\tif (!valid_entry) {\n+\t\tPMD_INIT_LOG(ERR, \"No valid entry found\");\n+\t\treturn -ENOMEM;\n+\t}\n+\t/**\n+\t * The entry have equal queue number as requested,\n+\t * remove it from alloc_list.\n+\t */\n+\tif (valid_entry->len == num) {\n+\t\tLIST_REMOVE(valid_entry, next);\n+\t} else {\n+\t\t/**\n+\t\t * The entry have more numbers than requested,\n+\t\t * create a new entry for alloc_list and minus its\n+\t\t * queue base and number in free_list.\n+\t\t */\n+\t\tentry = rte_zmalloc(NULL, sizeof(*entry), 0);\n+\t\tif (!entry) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t \"Failed to allocate memory for \"\n+\t\t\t\t \"resource pool\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\tentry->base = valid_entry->base;\n+\t\tentry->len = num;\n+\t\tvalid_entry->base += num;\n+\t\tvalid_entry->len -= num;\n+\t\tvalid_entry = entry;\n+\t}\n+\n+\t/* Insert it into alloc list, not sorted */\n+\tLIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);\n+\n+\tpool->num_free -= valid_entry->len;\n+\tpool->num_alloc += valid_entry->len;\n+\n+\treturn valid_entry->base + pool->base;\n+}\n+\n+static void\n+ice_res_pool_destroy(struct ice_res_pool_info *pool)\n+{\n+\tstruct pool_entry *entry, *next_entry;\n+\n+\tif (!pool)\n+\t\treturn;\n+\n+\tfor (entry = LIST_FIRST(&pool->alloc_list);\n+\t entry && (next_entry = LIST_NEXT(entry, next), 1);\n+\t entry = next_entry) {\n+\t\tLIST_REMOVE(entry, next);\n+\t\trte_free(entry);\n+\t}\n+\n+\tfor (entry = LIST_FIRST(&pool->free_list);\n+\t entry && (next_entry = LIST_NEXT(entry, next), 1);\n+\t entry = next_entry) {\n+\t\tLIST_REMOVE(entry, next);\n+\t\trte_free(entry);\n+\t}\n+\n+\tpool->num_free = 0;\n+\tpool->num_alloc = 0;\n+\tpool->base = 0;\n+\tLIST_INIT(&pool->alloc_list);\n+\tLIST_INIT(&pool->free_list);\n+}\n+\n+static void\n+ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)\n+{\n+\t/* Set VSI LUT selection */\n+\tinfo->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &\n+\t\t\t ICE_AQ_VSI_Q_OPT_RSS_LUT_M;\n+\t/* Set Hash scheme */\n+\tinfo->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &\n+\t\t\t ICE_AQ_VSI_Q_OPT_RSS_HASH_M;\n+\t/* enable TC */\n+\tinfo->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;\n+}\n+\n+static enum ice_status\n+ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,\n+\t\t\t\tstruct ice_aqc_vsi_props *info,\n+\t\t\t\tuint8_t enabled_tcmap)\n+{\n+\tuint16_t bsf, qp_idx;\n+\n+\t/* default tc 0 now. Multi-TC supporting need to be done later.\n+\t * Configure TC and queue mapping parameters, for enabled TC,\n+\t * allocate qpnum_per_tc queues to this traffic.\n+\t */\n+\tif (enabled_tcmap != 0x01) {\n+\t\tPMD_INIT_LOG(ERR, \"only TC0 is supported\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\n+\tvsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);\n+\tbsf = rte_bsf32(vsi->nb_qps);\n+\t/* Adjust the queue number to actual queues that can be applied */\n+\tvsi->nb_qps = 0x1 << bsf;\n+\n+\tqp_idx = 0;\n+\t/* Set tc and queue mapping with VSI */\n+\tinfo->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<\n+\t\t\t\t\t\tICE_AQ_VSI_TC_Q_OFFSET_S) |\n+\t\t\t\t\t (bsf << ICE_AQ_VSI_TC_Q_NUM_S));\n+\n+\t/* Associate queue number with VSI */\n+\tinfo->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);\n+\tinfo->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);\n+\tinfo->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);\n+\tinfo->valid_sections |=\n+\t\trte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);\n+\t/* Set the info.ingress_table and info.egress_table\n+\t * for UP translate table. Now just set it to 1:1 map by default\n+\t * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688\n+\t */\n+#define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688\n+\tinfo->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);\n+\tinfo->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);\n+\tinfo->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);\n+\treturn 0;\n+}\n+\n+static int\n+ice_init_mac_address(struct rte_eth_dev *dev)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tif (!is_unicast_ether_addr\n+\t\t((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {\n+\t\tPMD_INIT_LOG(ERR, \"Invalid MAC address\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,\n+\t\t\t(struct ether_addr *)hw->port_info[0].mac.perm_addr);\n+\n+\tdev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);\n+\tif (!dev->data->mac_addrs) {\n+\t\tPMD_INIT_LOG(ERR,\n+\t\t\t \"Failed to allocate memory to store mac address\");\n+\t\treturn -ENOMEM;\n+\t}\n+\t/* store it to dev data */\n+\tether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,\n+\t\t\t&dev->data->mac_addrs[0]);\n+\treturn 0;\n+}\n+\n+/* Initialize SW parameters of PF */\n+static int\n+ice_pf_sw_init(struct rte_eth_dev *dev)\n+{\n+\tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\n+\tif (ice_config_max_queue_pair_num(dev->device->devargs) > 0)\n+\t\tpf->lan_nb_qp_max =\n+\t\t\tice_config_max_queue_pair_num(dev->device->devargs);\n+\telse\n+\t\tpf->lan_nb_qp_max =\n+\t\t\t(uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,\n+\t\t\t\t\t hw->func_caps.common_cap.num_rxq);\n+\n+\tpf->lan_nb_qps = pf->lan_nb_qp_max;\n+\n+\treturn 0;\n+}\n+\n+static struct ice_vsi *\n+ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)\n+{\n+\tstruct ice_hw *hw = ICE_PF_TO_HW(pf);\n+\tstruct ice_vsi *vsi = NULL;\n+\tstruct ice_vsi_ctx vsi_ctx;\n+\tint ret;\n+\tuint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };\n+\tuint8_t tc_bitmap = 0x1;\n+\n+\t/* hw->num_lports = 1 in NIC mode */\n+\tvsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);\n+\tif (!vsi)\n+\t\treturn NULL;\n+\n+\tvsi->idx = pf->next_vsi_idx;\n+\tpf->next_vsi_idx++;\n+\tvsi->type = type;\n+\tvsi->adapter = ICE_PF_TO_ADAPTER(pf);\n+\tvsi->max_macaddrs = ICE_NUM_MACADDR_MAX;\n+\tvsi->vlan_anti_spoof_on = 0;\n+\tvsi->vlan_filter_on = 1;\n+\tTAILQ_INIT(&vsi->mac_list);\n+\tTAILQ_INIT(&vsi->vlan_list);\n+\n+\tmemset(&vsi_ctx, 0, sizeof(vsi_ctx));\n+\t/* base_queue in used in queue mapping of VSI add/update command.\n+\t * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ\n+\t * cases in the first stage. Only Main VSI.\n+\t */\n+\tvsi->base_queue = 0;\n+\tswitch (type) {\n+\tcase ICE_VSI_PF:\n+\t\tvsi->nb_qps = pf->lan_nb_qps;\n+\t\tice_vsi_config_default_rss(&vsi_ctx.info);\n+\t\tvsi_ctx.alloc_from_pool = true;\n+\t\tvsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;\n+\t\t/* switch_id is queried by get_switch_config aq, which is done\n+\t\t * by ice_init_hw\n+\t\t */\n+\t\tvsi_ctx.info.sw_id = hw->port_info->sw_id;\n+\t\tvsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;\n+\t\t/* Allow all untagged or tagged packets */\n+\t\tvsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;\n+\t\tvsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;\n+\t\tvsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |\n+\t\t\t\t\t ICE_AQ_VSI_Q_OPT_RSS_TPLZ;\n+\t\t/* Enable VLAN/UP trip */\n+\t\tret = ice_vsi_config_tc_queue_mapping(vsi,\n+\t\t\t\t\t\t &vsi_ctx.info,\n+\t\t\t\t\t\t ICE_DEFAULT_TCMAP);\n+\t\tif (ret) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t \"tc queue mapping with vsi failed, \"\n+\t\t\t\t \"err = %d\",\n+\t\t\t\t ret);\n+\t\t\tgoto fail_mem;\n+\t\t}\n+\n+\t\tbreak;\n+\tdefault:\n+\t\t/* for other types of VSI */\n+\t\tPMD_INIT_LOG(ERR, \"other types of VSI not supported\");\n+\t\tgoto fail_mem;\n+\t}\n+\n+\t/* VF has MSIX interrupt in VF range, don't allocate here */\n+\tif (type == ICE_VSI_PF) {\n+\t\tret = ice_res_pool_alloc(&pf->msix_pool,\n+\t\t\t\t\t RTE_MIN(vsi->nb_qps,\n+\t\t\t\t\t\t RTE_MAX_RXTX_INTR_VEC_ID));\n+\t\tif (ret < 0) {\n+\t\t\tPMD_INIT_LOG(ERR, \"VSI MAIN %d get heap failed %d\",\n+\t\t\t\t vsi->vsi_id, ret);\n+\t\t}\n+\t\tvsi->msix_intr = ret;\n+\t\tvsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);\n+\t} else {\n+\t\tvsi->msix_intr = 0;\n+\t\tvsi->nb_msix = 0;\n+\t}\n+\tret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);\n+\tif (ret != ICE_SUCCESS) {\n+\t\tPMD_INIT_LOG(ERR, \"add vsi failed, err = %d\", ret);\n+\t\tgoto fail_mem;\n+\t}\n+\t/* store vsi information is SW structure */\n+\tvsi->vsi_id = vsi_ctx.vsi_num;\n+\tvsi->info = vsi_ctx.info;\n+\tpf->vsis_allocated = vsi_ctx.vsis_allocd;\n+\tpf->vsis_unallocated = vsi_ctx.vsis_unallocated;\n+\n+\t/* At the beginning, only TC0. */\n+\t/* What we need here is the maximam number of the TX queues.\n+\t * Currently vsi->nb_qps means it.\n+\t * Correct it if any change.\n+\t */\n+\tmax_txqs[0] = vsi->nb_qps;\n+\tret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,\n+\t\t\t tc_bitmap, max_txqs);\n+\tif (ret != ICE_SUCCESS)\n+\t\tPMD_INIT_LOG(ERR, \"Failed to config vsi sched\");\n+\n+\treturn vsi;\n+fail_mem:\n+\trte_free(vsi);\n+\tpf->next_vsi_idx--;\n+\treturn NULL;\n+}\n+\n+static int\n+ice_pf_setup(struct ice_pf *pf)\n+{\n+\tstruct ice_vsi *vsi;\n+\n+\t/* Clear all stats counters */\n+\tpf->offset_loaded = FALSE;\n+\tmemset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));\n+\tmemset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));\n+\tmemset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));\n+\tmemset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));\n+\n+\tvsi = ice_setup_vsi(pf, ICE_VSI_PF);\n+\tif (!vsi) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to add vsi for PF\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpf->main_vsi = vsi;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_dev_init(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tint ret;\n+\n+\tdev->dev_ops = &ice_eth_dev_ops;\n+\n+\tpci_dev = RTE_DEV_TO_PCI(dev->device);\n+\n+\tpf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tpf->adapter->eth_dev = dev;\n+\tpf->dev_data = dev->data;\n+\thw->back = pf->adapter;\n+\thw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;\n+\thw->vendor_id = pci_dev->id.vendor_id;\n+\thw->device_id = pci_dev->id.device_id;\n+\thw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;\n+\thw->subsystem_device_id = pci_dev->id.subsystem_device_id;\n+\thw->bus.device = pci_dev->addr.devid;\n+\thw->bus.func = pci_dev->addr.function;\n+\n+\tice_init_controlq_parameter(hw);\n+\n+\tret = ice_init_hw(hw);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to initialize HW\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tPMD_INIT_LOG(INFO, \"FW %d.%d.%05d API %d.%d\",\n+\t\t hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,\n+\t\t hw->api_maj_ver, hw->api_min_ver);\n+\n+\tice_pf_sw_init(dev);\n+\tret = ice_init_mac_address(dev);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to initialize mac address\");\n+\t\tgoto err_init_mac;\n+\t}\n+\n+\tret = ice_res_pool_init(&pf->msix_pool, 1,\n+\t\t\t\thw->func_caps.common_cap.num_msix_vectors - 1);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to init MSIX pool\");\n+\t\tgoto err_msix_pool_init;\n+\t}\n+\n+\tret = ice_pf_setup(pf);\n+\tif (ret) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to setup PF\");\n+\t\tgoto err_pf_setup;\n+\t}\n+\n+\treturn 0;\n+\n+err_pf_setup:\n+\tice_res_pool_destroy(&pf->msix_pool);\n+err_msix_pool_init:\n+\trte_free(dev->data->mac_addrs);\n+err_init_mac:\n+\tice_sched_cleanup_all(hw);\n+\trte_free(hw->port_info);\n+\tice_shutdown_all_ctrlq(hw);\n+\n+\treturn ret;\n+}\n+\n+static int\n+ice_release_vsi(struct ice_vsi *vsi)\n+{\n+\tstruct ice_hw *hw;\n+\tstruct ice_vsi_ctx vsi_ctx;\n+\tenum ice_status ret;\n+\n+\tif (!vsi)\n+\t\treturn 0;\n+\n+\thw = ICE_VSI_TO_HW(vsi);\n+\n+\tmemset(&vsi_ctx, 0, sizeof(vsi_ctx));\n+\n+\tvsi_ctx.vsi_num = vsi->vsi_id;\n+\tvsi_ctx.info = vsi->info;\n+\tret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);\n+\tif (ret != ICE_SUCCESS) {\n+\t\tPMD_INIT_LOG(ERR, \"Failed to free vsi by aq, %u\", vsi->vsi_id);\n+\t\trte_free(vsi);\n+\t\treturn -1;\n+\t}\n+\n+\trte_free(vsi);\n+\treturn 0;\n+}\n+\n+static void\n+ice_dev_close(struct rte_eth_dev *dev)\n+{\n+\tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\tice_res_pool_destroy(&pf->msix_pool);\n+\tice_release_vsi(pf->main_vsi);\n+\n+\tice_shutdown_all_ctrlq(hw);\n+}\n+\n+static int\n+ice_dev_uninit(struct rte_eth_dev *dev)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);\n+\n+\tice_dev_close(dev);\n+\n+\tdev->dev_ops = NULL;\n+\tdev->rx_pkt_burst = NULL;\n+\tdev->tx_pkt_burst = NULL;\n+\n+\trte_free(dev->data->mac_addrs);\n+\tdev->data->mac_addrs = NULL;\n+\n+\tice_release_vsi(pf->main_vsi);\n+\tice_sched_cleanup_all(hw);\n+\trte_free(hw->port_info);\n+\tice_shutdown_all_ctrlq(hw);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n+\t struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_eth_dev_pci_generic_probe(pci_dev,\n+\t\t\t\t\t sizeof(struct ice_adapter),\n+\t\t\t\t\t ice_dev_init);\n+}\n+\n+static int\n+ice_pci_remove(struct rte_pci_device *pci_dev)\n+{\n+\treturn rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);\n+}\n+\n+static struct rte_pci_driver rte_ice_pmd = {\n+\t.id_table = pci_id_ice_map,\n+\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,\n+\t.probe = ice_pci_probe,\n+\t.remove = ice_pci_remove,\n+};\n+\n+/**\n+ * Driver initialization routine.\n+ * Invoked once at EAL init time.\n+ * Register itself as the [Poll Mode] Driver of PCI devices.\n+ */\n+RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);\n+RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);\n+RTE_PMD_REGISTER_KMOD_DEP(net_ice, \"* igb_uio | uio_pci_generic | vfio-pci\");\n+\n+RTE_INIT(ice_init_log)\n+{\n+\tice_logtype_init = rte_log_register(\"pmd.net.ice.init\");\n+\tif (ice_logtype_init >= 0)\n+\t\trte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);\n+\tice_logtype_driver = rte_log_register(\"pmd.net.ice.driver\");\n+\tif (ice_logtype_driver >= 0)\n+\t\trte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);\n+}\ndiff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nnew file mode 100644\nindex 0000000..94e45c8\n--- /dev/null\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -0,0 +1,305 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#ifndef _ICE_ETHDEV_H_\n+#define _ICE_ETHDEV_H_\n+\n+#include <rte_kvargs.h>\n+\n+#include \"base/ice_common.h\"\n+#include \"base/ice_adminq_cmd.h\"\n+\n+#define ICE_VLAN_TAG_SIZE 4\n+\n+#define ICE_ADMINQ_LEN 32\n+#define ICE_SBIOQ_LEN 32\n+#define ICE_MAILBOXQ_LEN 32\n+#define ICE_ADMINQ_BUF_SZ 4096\n+#define ICE_SBIOQ_BUF_SZ 4096\n+#define ICE_MAILBOXQ_BUF_SZ 4096\n+/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */\n+#define ICE_MAX_Q_PER_TC 64\n+#define ICE_NUM_DESC_DEFAULT 512\n+#define ICE_BUF_SIZE_MIN 1024\n+#define ICE_FRAME_SIZE_MAX 9728\n+#define ICE_QUEUE_BASE_ADDR_UNIT 128\n+/* number of VSIs and queue default setting */\n+#define ICE_MAX_QP_NUM_PER_VF 16\n+#define ICE_DEFAULT_QP_NUM_FDIR 1\n+#define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))\n+#define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE)\n+/* Maximun number of MAC addresses */\n+#define ICE_NUM_MACADDR_MAX 64\n+/* Maximum number of VFs */\n+#define ICE_MAX_VF 128\n+#define ICE_MAX_INTR_QUEUE_NUM 256\n+\n+#define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET\n+#define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET\n+\n+#define ICE_MAX_PKT_TYPE 1024\n+\n+/**\n+ * vlan_id is a 12 bit number.\n+ * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.\n+ * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.\n+ * The higher 7 bit val specifies VFTA array index.\n+ */\n+#define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))\n+#define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5)\n+\n+/* Default TC traffic in case DCB is not enabled */\n+#define ICE_DEFAULT_TCMAP 0x1\n+#define ICE_FDIR_QUEUE_ID 0\n+\n+/* Always assign pool 0 to main VSI, VMDQ will start from 1 */\n+#define ICE_VMDQ_POOL_BASE 1\n+\n+#define ICE_DEFAULT_RX_FREE_THRESH 32\n+#define ICE_DEFAULT_RX_PTHRESH 8\n+#define ICE_DEFAULT_RX_HTHRESH 8\n+#define ICE_DEFAULT_RX_WTHRESH 0\n+\n+#define ICE_DEFAULT_TX_FREE_THRESH 32\n+#define ICE_DEFAULT_TX_PTHRESH 32\n+#define ICE_DEFAULT_TX_HTHRESH 0\n+#define ICE_DEFAULT_TX_WTHRESH 0\n+#define ICE_DEFAULT_TX_RSBIT_THRESH 32\n+\n+/* Bit shift and mask */\n+#define ICE_4_BIT_WIDTH (CHAR_BIT / 2)\n+#define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)\n+#define ICE_8_BIT_WIDTH CHAR_BIT\n+#define ICE_8_BIT_MASK UINT8_MAX\n+#define ICE_16_BIT_WIDTH (CHAR_BIT * 2)\n+#define ICE_16_BIT_MASK UINT16_MAX\n+#define ICE_32_BIT_WIDTH (CHAR_BIT * 4)\n+#define ICE_32_BIT_MASK UINT32_MAX\n+#define ICE_40_BIT_WIDTH (CHAR_BIT * 5)\n+#define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)\n+#define ICE_48_BIT_WIDTH (CHAR_BIT * 6)\n+#define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)\n+\n+#define ICE_FLAG_RSS BIT_ULL(0)\n+#define ICE_FLAG_DCB BIT_ULL(1)\n+#define ICE_FLAG_VMDQ BIT_ULL(2)\n+#define ICE_FLAG_SRIOV BIT_ULL(3)\n+#define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)\n+#define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)\n+#define ICE_FLAG_FDIR BIT_ULL(6)\n+#define ICE_FLAG_VXLAN BIT_ULL(7)\n+#define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)\n+#define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)\n+#define ICE_FLAG_ALL (ICE_FLAG_RSS | \\\n+\t\t ICE_FLAG_DCB | \\\n+\t\t ICE_FLAG_VMDQ | \\\n+\t\t ICE_FLAG_SRIOV | \\\n+\t\t ICE_FLAG_HEADER_SPLIT_DISABLED | \\\n+\t\t ICE_FLAG_HEADER_SPLIT_ENABLED | \\\n+\t\t ICE_FLAG_FDIR | \\\n+\t\t ICE_FLAG_VXLAN | \\\n+\t\t ICE_FLAG_RSS_AQ_CAPABLE | \\\n+\t\t ICE_FLAG_VF_MAC_BY_PF)\n+\n+struct ice_adapter;\n+\n+/**\n+ * MAC filter structure\n+ */\n+struct ice_mac_filter_info {\n+\tstruct ether_addr mac_addr;\n+};\n+\n+TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);\n+\n+/* MAC filter list structure */\n+struct ice_mac_filter {\n+\tTAILQ_ENTRY(ice_mac_filter) next;\n+\tstruct ice_mac_filter_info mac_info;\n+};\n+\n+/**\n+ * VLAN filter structure\n+ */\n+struct ice_vlan_filter_info {\n+\tuint16_t vlan_id;\n+};\n+\n+TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);\n+\n+/* VLAN filter list structure */\n+struct ice_vlan_filter {\n+\tTAILQ_ENTRY(ice_vlan_filter) next;\n+\tstruct ice_vlan_filter_info vlan_info;\n+};\n+\n+struct pool_entry {\n+\tLIST_ENTRY(pool_entry) next;\n+\tuint16_t base;\n+\tuint16_t len;\n+};\n+\n+LIST_HEAD(res_list, pool_entry);\n+\n+struct ice_res_pool_info {\n+\tuint32_t base; /* Resource start index */\n+\tuint32_t num_alloc; /* Allocated resource number */\n+\tuint32_t num_free; /* Total available resource number */\n+\tstruct res_list alloc_list; /* Allocated resource list */\n+\tstruct res_list free_list; /* Available resource list */\n+};\n+\n+TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);\n+\n+struct ice_vsi;\n+\n+/* VSI list structure */\n+struct ice_vsi_list {\n+\tTAILQ_ENTRY(ice_vsi_list) list;\n+\tstruct ice_vsi *vsi;\n+};\n+\n+struct ice_rx_queue;\n+struct ice_tx_queue;\n+\n+/**\n+ * Structure that defines a VSI, associated with a adapter.\n+ */\n+struct ice_vsi {\n+\tstruct ice_adapter *adapter; /* Backreference to associated adapter */\n+\tstruct ice_aqc_vsi_props info; /* VSI properties */\n+\t/**\n+\t * When drivers loaded, only a default main VSI exists. In case new VSI\n+\t * needs to add, HW needs to know the layout that VSIs are organized.\n+\t * Besides that, VSI isan element and can't switch packets, which needs\n+\t * to add new component VEB to perform switching. So, a new VSI needs\n+\t * to specify the the uplink VSI (Parent VSI) before created. The\n+\t * uplink VSI will check whether it had a VEB to switch packets. If no,\n+\t * it will try to create one. Then, uplink VSI will move the new VSI\n+\t * into its' sib_vsi_list to manage all the downlink VSI.\n+\t * sib_vsi_list: the VSI list that shared the same uplink VSI.\n+\t * parent_vsi : the uplink VSI. It's NULL for main VSI.\n+\t * veb : the VEB associates with the VSI.\n+\t */\n+\tstruct ice_vsi_list sib_vsi_list; /* sibling vsi list */\n+\tstruct ice_vsi *parent_vsi;\n+\tenum ice_vsi_type type; /* VSI types */\n+\tuint16_t vlan_num; /* Total VLAN number */\n+\tuint16_t mac_num; /* Total mac number */\n+\tstruct ice_mac_filter_list mac_list; /* macvlan filter list */\n+\tstruct ice_vlan_filter_list vlan_list; /* vlan filter list */\n+\tuint16_t nb_qps; /* Number of queue pairs VSI can occupy */\n+\tuint16_t nb_used_qps; /* Number of queue pairs VSI uses */\n+\tuint16_t max_macaddrs; /* Maximum number of MAC addresses */\n+\tuint16_t base_queue; /* The first queue index of this VSI */\n+\tuint16_t vsi_id; /* Hardware Id */\n+\tuint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */\n+\t/* VF number to which the VSI connects, valid when VSI is VF type */\n+\tuint8_t vf_num;\n+\tuint16_t msix_intr; /* The MSIX interrupt binds to VSI */\n+\tuint16_t nb_msix; /* The max number of msix vector */\n+\tuint8_t enabled_tc; /* The traffic class enabled */\n+\tuint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */\n+\tuint8_t vlan_filter_on; /* The VLAN filter enabled */\n+\t/* information about rss configuration */\n+\tu32 rss_key_size;\n+\tu32 rss_lut_size;\n+\tuint8_t *rss_lut;\n+\tuint8_t *rss_key;\n+\tstruct ice_eth_stats eth_stats_offset;\n+\tstruct ice_eth_stats eth_stats;\n+\tbool offset_loaded;\n+};\n+\n+struct ice_pf {\n+\tstruct ice_adapter *adapter; /* The adapter this PF associate to */\n+\tstruct ice_vsi *main_vsi; /* pointer to main VSI structure */\n+\t/* Used for next free software vsi idx.\n+\t * To save the effort, we don't recycle the index.\n+\t * Suppose the indexes are more than enough.\n+\t */\n+\tuint16_t next_vsi_idx;\n+\tuint16_t vsis_allocated;\n+\tuint16_t vsis_unallocated;\n+\tstruct ice_res_pool_info qp_pool; /*Queue pair pool */\n+\tstruct ice_res_pool_info msix_pool; /* MSIX interrupt pool */\n+\tstruct rte_eth_dev_data *dev_data; /* Pointer to the device data */\n+\tstruct ether_addr dev_addr; /* PF device mac address */\n+\tuint64_t flags; /* PF feature flags */\n+\tuint16_t hash_lut_size; /* The size of hash lookup table */\n+\tuint16_t lan_nb_qp_max;\n+\tuint16_t lan_nb_qps; /* The number of queue pairs of LAN */\n+\tstruct ice_hw_port_stats stats_offset;\n+\tstruct ice_hw_port_stats stats;\n+\t/* internal packet statistics, it should be excluded from the total */\n+\tstruct ice_eth_stats internal_stats_offset;\n+\tstruct ice_eth_stats internal_stats;\n+\tbool offset_loaded;\n+\tbool adapter_stopped;\n+};\n+\n+/**\n+ * Structure to store private data for each PF/VF instance.\n+ */\n+struct ice_adapter {\n+\t/* Common for both PF and VF */\n+\tstruct ice_hw hw;\n+\tstruct rte_eth_dev *eth_dev;\n+\tstruct ice_pf pf;\n+\tbool rx_bulk_alloc_allowed;\n+\tbool tx_simple_allowed;\n+\t/* ptype mapping table */\n+\tuint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;\n+};\n+\n+struct ice_vsi_vlan_pvid_info {\n+\tuint16_t on;\t\t/* Enable or disable pvid */\n+\tunion {\n+\t\tuint16_t pvid;\t/* Valid in case 'on' is set to set pvid */\n+\t\tstruct {\n+\t\t\t/* Valid in case 'on' is cleared. 'tagged' will reject\n+\t\t\t * tagged packets, while 'untagged' will reject\n+\t\t\t * untagged packets.\n+\t\t\t */\n+\t\t\tuint8_t tagged;\n+\t\t\tuint8_t untagged;\n+\t\t} reject;\n+\t} config;\n+};\n+\n+#define ICE_DEV_TO_PCI(eth_dev) \\\n+\tRTE_DEV_TO_PCI((eth_dev)->device)\n+\n+/* ICE_DEV_PRIVATE_TO */\n+#define ICE_DEV_PRIVATE_TO_PF(adapter) \\\n+\t(&((struct ice_adapter *)adapter)->pf)\n+#define ICE_DEV_PRIVATE_TO_HW(adapter) \\\n+\t(&((struct ice_adapter *)adapter)->hw)\n+#define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \\\n+\t((struct ice_adapter *)adapter)\n+\n+/* ICE_VSI_TO */\n+#define ICE_VSI_TO_HW(vsi) \\\n+\t(&(((struct ice_vsi *)vsi)->adapter->hw))\n+#define ICE_VSI_TO_PF(vsi) \\\n+\t(&(((struct ice_vsi *)vsi)->adapter->pf))\n+#define ICE_VSI_TO_ETH_DEV(vsi) \\\n+\t(((struct ice_vsi *)vsi)->adapter->eth_dev)\n+\n+/* ICE_PF_TO */\n+#define ICE_PF_TO_HW(pf) \\\n+\t(&(((struct ice_pf *)pf)->adapter->hw))\n+#define ICE_PF_TO_ADAPTER(pf) \\\n+\t((struct ice_adapter *)(pf)->adapter)\n+#define ICE_PF_TO_ETH_DEV(pf) \\\n+\t(((struct ice_pf *)pf)->adapter->eth_dev)\n+\n+static inline int\n+ice_align_floor(int n)\n+{\n+\tif (n == 0)\n+\t\treturn 0;\n+\treturn 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));\n+}\n+#endif /* _ICE_ETHDEV_H_ */\ndiff --git a/drivers/net/ice/ice_logs.h b/drivers/net/ice/ice_logs.h\nnew file mode 100644\nindex 0000000..de2d573\n--- /dev/null\n+++ b/drivers/net/ice/ice_logs.h\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#ifndef _ICE_LOGS_H_\n+#define _ICE_LOGS_H_\n+\n+extern int ice_logtype_init;\n+extern int ice_logtype_driver;\n+\n+#define PMD_INIT_LOG(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, ice_logtype_init, \"%s(): \" fmt \"\\n\", \\\n+\t\t__func__, ##args)\n+\n+#define PMD_INIT_FUNC_TRACE() PMD_INIT_LOG(DEBUG, \" >>\")\n+\n+#ifdef RTE_LIBRTE_ICE_DEBUG_RX\n+#define PMD_RX_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n+#else\n+#define PMD_RX_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_ICE_DEBUG_TX\n+#define PMD_TX_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n+#else\n+#define PMD_TX_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE\n+#define PMD_TX_FREE_LOG(level, fmt, args...) \\\n+\tRTE_LOG(level, PMD, \"%s(): \" fmt \"\\n\", __func__, ## args)\n+#else\n+#define PMD_TX_FREE_LOG(level, fmt, args...) do { } while (0)\n+#endif\n+\n+#define PMD_DRV_LOG_RAW(level, fmt, args...) \\\n+\trte_log(RTE_LOG_ ## level, ice_logtype_driver, \"%s(): \" fmt, \\\n+\t\t__func__, ## args)\n+\n+#define PMD_DRV_LOG(level, fmt, args...) \\\n+\tPMD_DRV_LOG_RAW(level, fmt \"\\n\", ## args)\n+\n+#endif /* _ICE_LOGS_H_ */\ndiff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h\nnew file mode 100644\nindex 0000000..c37dc23\n--- /dev/null\n+++ b/drivers/net/ice/ice_rxtx.h\n@@ -0,0 +1,117 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018 Intel Corporation\n+ */\n+\n+#ifndef _ICE_RXTX_H_\n+#define _ICE_RXTX_H_\n+\n+#include \"ice_ethdev.h\"\n+\n+#define ICE_ALIGN_RING_DESC 32\n+#define ICE_MIN_RING_DESC 64\n+#define ICE_MAX_RING_DESC 4096\n+#define ICE_DMA_MEM_ALIGN 4096\n+#define ICE_RING_BASE_ALIGN 128\n+\n+#define ICE_RX_MAX_BURST 32\n+#define ICE_TX_MAX_BURST 32\n+\n+#define ICE_CHK_Q_ENA_COUNT 100\n+#define ICE_CHK_Q_ENA_INTERVAL_US 100\n+\n+#ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC\n+#define ice_rx_desc ice_16byte_rx_desc\n+#else\n+#define ice_rx_desc ice_32byte_rx_desc\n+#endif\n+\n+#define ICE_SUPPORT_CHAIN_NUM 5\n+\n+struct ice_rx_entry {\n+\tstruct rte_mbuf *mbuf;\n+};\n+\n+struct ice_rx_queue {\n+\tstruct rte_mempool *mp; /* mbuf pool to populate RX ring */\n+\tvolatile union ice_rx_desc *rx_ring;/* RX ring virtual address */\n+\tuint64_t rx_ring_phys_addr; /* RX ring DMA address */\n+\tstruct ice_rx_entry *sw_ring; /* address of RX soft ring */\n+\tuint16_t nb_rx_desc; /* number of RX descriptors */\n+\tuint16_t rx_free_thresh; /* max free RX desc to hold */\n+\tuint16_t rx_tail; /* current value of tail */\n+\tuint16_t nb_rx_hold; /* number of held free RX desc */\n+\tstruct rte_mbuf *pkt_first_seg; /**< first segment of current packet */\n+\tstruct rte_mbuf *pkt_last_seg; /**< last segment of current packet */\n+#ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC\n+\tuint16_t rx_nb_avail; /**< number of staged packets ready */\n+\tuint16_t rx_next_avail; /**< index of next staged packets */\n+\tuint16_t rx_free_trigger; /**< triggers rx buffer allocation */\n+\tstruct rte_mbuf fake_mbuf; /**< dummy mbuf */\n+\tstruct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2];\n+#endif\n+\tuint8_t port_id; /* device port ID */\n+\tuint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */\n+\tuint16_t queue_id; /* RX queue index */\n+\tuint16_t reg_idx; /* RX queue register index */\n+\tuint8_t drop_en; /* if not 0, set register bit */\n+\tvolatile uint8_t *qrx_tail; /* register address of tail */\n+\tstruct ice_vsi *vsi; /* the VSI this queue belongs to */\n+\tuint16_t rx_buf_len; /* The packet buffer size */\n+\tuint16_t rx_hdr_len; /* The header buffer size */\n+\tuint16_t max_pkt_len; /* Maximum packet length */\n+\tbool q_set; /* indicate if rx queue has been configured */\n+\tbool rx_deferred_start; /* don't start this queue in dev start */\n+};\n+\n+struct ice_tx_entry {\n+\tstruct rte_mbuf *mbuf;\n+\tuint16_t next_id;\n+\tuint16_t last_id;\n+};\n+\n+struct ice_tx_queue {\n+\tuint16_t nb_tx_desc; /* number of TX descriptors */\n+\tuint64_t tx_ring_phys_addr; /* TX ring DMA address */\n+\tvolatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */\n+\tstruct ice_tx_entry *sw_ring; /* virtual address of SW ring */\n+\tuint16_t tx_tail; /* current value of tail register */\n+\tvolatile uint8_t *qtx_tail; /* register address of tail */\n+\tuint16_t nb_tx_used; /* number of TX desc used since RS bit set */\n+\t/* index to last TX descriptor to have been cleaned */\n+\tuint16_t last_desc_cleaned;\n+\t/* Total number of TX descriptors ready to be allocated. */\n+\tuint16_t nb_tx_free;\n+\t/* Start freeing TX buffers if there are less free descriptors than\n+\t * this value.\n+\t */\n+\tuint16_t tx_free_thresh;\n+\t/* Number of TX descriptors to use before RS bit is set. */\n+\tuint16_t tx_rs_thresh;\n+\tuint8_t pthresh; /**< Prefetch threshold register. */\n+\tuint8_t hthresh; /**< Host threshold register. */\n+\tuint8_t wthresh; /**< Write-back threshold reg. */\n+\tuint8_t port_id; /* Device port identifier. */\n+\tuint16_t queue_id; /* TX queue index. */\n+\tuint32_t q_teid; /* TX schedule node id. */\n+\tuint16_t reg_idx;\n+\tuint64_t offloads;\n+\tstruct ice_vsi *vsi; /* the VSI this queue belongs to */\n+\tuint16_t tx_next_dd;\n+\tuint16_t tx_next_rs;\n+\tbool tx_deferred_start; /* don't start this queue in dev start */\n+\tbool q_set; /* indicate if tx queue has been configured */\n+};\n+\n+/* Offload features */\n+union ice_tx_offload {\n+\tuint64_t data;\n+\tstruct {\n+\t\tuint64_t l2_len:7; /* L2 (MAC) Header Length. */\n+\t\tuint64_t l3_len:9; /* L3 (IP) Header Length. */\n+\t\tuint64_t l4_len:8; /* L4 Header Length. */\n+\t\tuint64_t tso_segsz:16; /* TCP TSO segment size */\n+\t\tuint64_t outer_l2_len:8; /* outer L2 Header Length */\n+\t\tuint64_t outer_l3_len:16; /* outer L3 Header Length */\n+\t};\n+};\n+#endif /* _ICE_RXTX_H_ */\ndiff --git a/drivers/net/ice/meson.build b/drivers/net/ice/meson.build\nnew file mode 100644\nindex 0000000..9ed7b27\n--- /dev/null\n+++ b/drivers/net/ice/meson.build\n@@ -0,0 +1,12 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2018 Intel Corporation\n+\n+subdir('base')\n+objs = [base_objs]\n+\n+sources = files(\n+\t'ice_ethdev.c'\n+\t)\n+\n+deps += ['hash']\n+includes += include_directories('base')\ndiff --git a/drivers/net/ice/rte_pmd_ice_version.map b/drivers/net/ice/rte_pmd_ice_version.map\nnew file mode 100644\nindex 0000000..7b23b60\n--- /dev/null\n+++ b/drivers/net/ice/rte_pmd_ice_version.map\n@@ -0,0 +1,4 @@\n+DPDK_19.02 {\n+\n+\tlocal: *;\n+};\ndiff --git a/drivers/net/meson.build b/drivers/net/meson.build\nindex 980eec2..45da3bb 100644\n--- a/drivers/net/meson.build\n+++ b/drivers/net/meson.build\n@@ -17,6 +17,7 @@ drivers = ['af_packet',\n \t'enic',\n \t'failsafe',\n \t'fm10k', 'i40e',\n+\t'ice',\n \t'ifc',\n \t'ixgbe',\n \t'kni',\ndiff --git a/mk/rte.app.mk b/mk/rte.app.mk\nindex 5699d97..02e8b6f 100644\n--- a/mk/rte.app.mk\n+++ b/mk/rte.app.mk\n@@ -163,6 +163,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += -lrte_pmd_enic\n _LDLIBS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += -lrte_pmd_fm10k\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += -lrte_pmd_failsafe\n _LDLIBS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += -lrte_pmd_i40e\n+_LDLIBS-$(CONFIG_RTE_LIBRTE_ICE_PMD) += -lrte_pmd_ice\n _LDLIBS-$(CONFIG_RTE_LIBRTE_IXGBE_PMD) += -lrte_pmd_ixgbe\n ifeq ($(CONFIG_RTE_LIBRTE_KNI),y)\n _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_KNI) += -lrte_pmd_kni\n", "prefixes": [ "v5", "15/31" ] }