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GET /api/patches/48976/?format=api
{ "id": 48976, "url": "https://patches.dpdk.org/api/patches/48976/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-10-git-send-email-wenzhuo.lu@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1545032259-77179-10-git-send-email-wenzhuo.lu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1545032259-77179-10-git-send-email-wenzhuo.lu@intel.com", "date": "2018-12-17T07:37:17", "name": "[v5,09/31] net/ice/base: add code to work with the NVM", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d1c5ba3be79cfa38ed712a926e6fd516040feb6a", "submitter": { "id": 258, "url": "https://patches.dpdk.org/api/people/258/?format=api", "name": "Wenzhuo Lu", "email": "wenzhuo.lu@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1545032259-77179-10-git-send-email-wenzhuo.lu@intel.com/mbox/", "series": [ { "id": 2824, "url": "https://patches.dpdk.org/api/series/2824/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2824", "date": "2018-12-17T07:37:08", "name": "A new net PMD - ICE", "version": 5, "mbox": "https://patches.dpdk.org/series/2824/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/48976/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/48976/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 8F3AF1B5AC;\n\tMon, 17 Dec 2018 08:33:10 +0100 (CET)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby dpdk.org (Postfix) with ESMTP id A7AF91B5E0\n\tfor <dev@dpdk.org>; Mon, 17 Dec 2018 08:33:05 +0100 (CET)", "from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t16 Dec 2018 23:33:04 -0800", "from dpdk26.sh.intel.com ([10.67.110.164])\n\tby orsmga002.jf.intel.com with ESMTP; 16 Dec 2018 23:33:04 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,364,1539673200\"; d=\"scan'208\";a=\"118899148\"", "From": "Wenzhuo Lu <wenzhuo.lu@intel.com>", "To": "dev@dpdk.org", "Cc": "Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Mon, 17 Dec 2018 15:37:17 +0800", "Message-Id": "<1545032259-77179-10-git-send-email-wenzhuo.lu@intel.com>", "X-Mailer": "git-send-email 1.9.3", "In-Reply-To": "<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "References": "<1542956179-80951-1-git-send-email-wenzhuo.lu@intel.com>\n\t<1545032259-77179-1-git-send-email-wenzhuo.lu@intel.com>", "Subject": "[dpdk-dev] [PATCH v5 09/31] net/ice/base: add code to work with the\n\tNVM", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n\nAdd code to read/write/query the NVM image.\n\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\n---\n drivers/net/ice/base/ice_nvm.c | 387 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 387 insertions(+)\n create mode 100644 drivers/net/ice/base/ice_nvm.c", "diff": "diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nnew file mode 100644\nindex 0000000..25a2ca4\n--- /dev/null\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -0,0 +1,387 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2001-2018\n+ */\n+\n+#include \"ice_common.h\"\n+\n+\n+/**\n+ * ice_aq_read_nvm\n+ * @hw: pointer to the hw struct\n+ * @module_typeid: module pointer location in words from the NVM beginning\n+ * @offset: byte offset from the module beginning\n+ * @length: length of the section to be read (in bytes from the offset)\n+ * @data: command buffer (size [bytes] = length)\n+ * @last_command: tells if this is the last command in a series\n+ * @cd: pointer to command details structure or NULL\n+ *\n+ * Read the NVM using the admin queue commands (0x0701)\n+ */\n+static enum ice_status\n+ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,\n+\t\tvoid *data, bool last_command, struct ice_sq_cd *cd)\n+{\n+\tstruct ice_aq_desc desc;\n+\tstruct ice_aqc_nvm *cmd;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_aq_read_nvm\");\n+\n+\tcmd = &desc.params.nvm;\n+\n+\t/* In offset the highest byte must be zeroed. */\n+\tif (offset & 0xFF000000)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);\n+\n+\t/* If this is the last command in a series, set the proper flag. */\n+\tif (last_command)\n+\t\tcmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;\n+\tcmd->module_typeid = CPU_TO_LE16(module_typeid);\n+\tcmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);\n+\tcmd->offset_high = (offset >> 16) & 0xFF;\n+\tcmd->length = CPU_TO_LE16(length);\n+\n+\treturn ice_aq_send_cmd(hw, &desc, data, length, cd);\n+}\n+\n+/**\n+ * ice_check_sr_access_params - verify params for Shadow RAM R/W operations.\n+ * @hw: pointer to the HW structure\n+ * @offset: offset in words from module start\n+ * @words: number of words to access\n+ */\n+static enum ice_status\n+ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)\n+{\n+\tif ((offset + words) > hw->nvm.sr_words) {\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM error: offset beyond SR lmt.\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {\n+\t\t/* We can access only up to 4KB (one sector), in one AQ write */\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM error: tried to access %d words, limit is %d.\\n\",\n+\t\t\t words, ICE_SR_SECTOR_SIZE_IN_WORDS);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=\n+\t (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {\n+\t\t/* A single access cannot spread over two sectors */\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM error: cannot spread over two sectors.\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_read_sr_aq - Read Shadow RAM.\n+ * @hw: pointer to the HW structure\n+ * @offset: offset in words from module start\n+ * @words: number of words to read\n+ * @data: buffer for words reads from Shadow RAM\n+ * @last_command: tells the AdminQ that this is the last command\n+ *\n+ * Reads 16-bit word buffers from the Shadow RAM using the admin command.\n+ */\n+static enum ice_status\n+ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,\n+\t bool last_command)\n+{\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_read_sr_aq\");\n+\n+\tstatus = ice_check_sr_access_params(hw, offset, words);\n+\n+\t/* values in \"offset\" and \"words\" parameters are sized as words\n+\t * (16 bits) but ice_aq_read_nvm expects these values in bytes.\n+\t * So do this conversion while calling ice_aq_read_nvm.\n+\t */\n+\tif (!status)\n+\t\tstatus = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,\n+\t\t\t\t\t last_command, NULL);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_read_sr_word_aq - Reads Shadow RAM via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.\n+ */\n+static enum ice_status\n+ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_read_sr_word_aq\");\n+\n+\tstatus = ice_read_sr_aq(hw, offset, 1, data, true);\n+\tif (!status)\n+\t\t*data = LE16_TO_CPU(*(__le16 *)data);\n+\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq\n+ * method. Ownership of the NVM is taken before reading the buffer and later\n+ * released.\n+ */\n+static enum ice_status\n+ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)\n+{\n+\tenum ice_status status;\n+\tbool last_cmd = false;\n+\tu16 words_read = 0;\n+\tu16 i = 0;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_read_sr_buf_aq\");\n+\n+\tdo {\n+\t\tu16 read_size, off_w;\n+\n+\t\t/* Calculate number of bytes we should read in this step.\n+\t\t * It's not allowed to read more than one page at a time or\n+\t\t * to cross page boundaries.\n+\t\t */\n+\t\toff_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS;\n+\t\tread_size = off_w ?\n+\t\t\tmin(*words,\n+\t\t\t (u16)(ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) :\n+\t\t\tmin((*words - words_read), ICE_SR_SECTOR_SIZE_IN_WORDS);\n+\n+\t\t/* Check if this is last command, if so set proper flag */\n+\t\tif ((words_read + read_size) >= *words)\n+\t\t\tlast_cmd = true;\n+\n+\t\tstatus = ice_read_sr_aq(hw, offset, read_size,\n+\t\t\t\t\tdata + words_read, last_cmd);\n+\t\tif (status)\n+\t\t\tgoto read_nvm_buf_aq_exit;\n+\n+\t\t/* Increment counter for words already read and move offset to\n+\t\t * new read location\n+\t\t */\n+\t\twords_read += read_size;\n+\t\toffset += read_size;\n+\t} while (words_read < *words);\n+\n+\tfor (i = 0; i < *words; i++)\n+\t\tdata[i] = LE16_TO_CPU(((__le16 *)data)[i]);\n+\n+read_nvm_buf_aq_exit:\n+\t*words = words_read;\n+\treturn status;\n+}\n+\n+/**\n+ * ice_acquire_nvm - Generic request for acquiring the NVM ownership\n+ * @hw: pointer to the HW structure\n+ * @access: NVM access type (read or write)\n+ *\n+ * This function will request NVM ownership.\n+ */\n+static enum ice_status\n+ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)\n+{\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_acquire_nvm\");\n+\n+\tif (hw->nvm.blank_nvm_mode)\n+\t\treturn ICE_SUCCESS;\n+\n+\treturn ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);\n+}\n+\n+/**\n+ * ice_release_nvm - Generic request for releasing the NVM ownership\n+ * @hw: pointer to the HW structure\n+ *\n+ * This function will release NVM ownership.\n+ */\n+static void ice_release_nvm(struct ice_hw *hw)\n+{\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_release_nvm\");\n+\n+\tif (hw->nvm.blank_nvm_mode)\n+\t\treturn;\n+\n+\tice_release_res(hw, ICE_NVM_RES_ID);\n+}\n+\n+/**\n+ * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.\n+ */\n+enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_acquire_nvm(hw, ICE_RES_READ);\n+\tif (!status) {\n+\t\tstatus = ice_read_sr_word_aq(hw, offset, data);\n+\t\tice_release_nvm(hw);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_init_nvm - initializes NVM setting\n+ * @hw: pointer to the hw struct\n+ *\n+ * This function reads and populates NVM settings such as Shadow RAM size,\n+ * max_timeout, and blank_nvm_mode\n+ */\n+enum ice_status ice_init_nvm(struct ice_hw *hw)\n+{\n+\tstruct ice_nvm_info *nvm = &hw->nvm;\n+\tu16 oem_hi, oem_lo, cfg_ptr;\n+\tu16 eetrack_lo, eetrack_hi;\n+\tenum ice_status status = ICE_SUCCESS;\n+\tu32 fla, gens_stat;\n+\tu8 sr_size;\n+\n+\tice_debug(hw, ICE_DBG_TRACE, \"ice_init_nvm\");\n+\n+\t/* The SR size is stored regardless of the nvm programming mode\n+\t * as the blank mode may be used in the factory line.\n+\t */\n+\tgens_stat = rd32(hw, GLNVM_GENS);\n+\tsr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;\n+\n+\t/* Switching to words (sr_size contains power of 2) */\n+\tnvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;\n+\n+\t/* Check if we are in the normal or blank NVM programming mode */\n+\tfla = rd32(hw, GLNVM_FLA);\n+\tif (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */\n+\t\tnvm->blank_nvm_mode = false;\n+\t} else { /* Blank programming mode */\n+\t\tnvm->blank_nvm_mode = true;\n+\t\tstatus = ICE_ERR_NVM_BLANK_MODE;\n+\t\tice_debug(hw, ICE_DBG_NVM,\n+\t\t\t \"NVM init error: unsupported blank mode.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"Failed to read DEV starter version.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read EETRACK lo.\\n\");\n+\t\treturn status;\n+\t}\n+\tstatus = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read EETRACK hi.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\thw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;\n+\n+\tstatus = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read BOOT_CONFIG_PTR.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read OEM_VER hi.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),\n+\t\t\t\t &oem_lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_INIT, \"Failed to read OEM_VER lo.\\n\");\n+\t\treturn status;\n+\t}\n+\n+\thw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq\n+ * method. The buf read is preceded by the NVM ownership take\n+ * and followed by the release.\n+ */\n+enum ice_status\n+ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_acquire_nvm(hw, ICE_RES_READ);\n+\tif (!status) {\n+\t\tstatus = ice_read_sr_buf_aq(hw, offset, words, data);\n+\t\tice_release_nvm(hw);\n+\t}\n+\n+\treturn status;\n+}\n+\n+\n+/**\n+ * ice_nvm_validate_checksum\n+ * @hw: pointer to the hw struct\n+ *\n+ * Verify NVM PFA checksum validity (0x0706)\n+ */\n+enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)\n+{\n+\tstruct ice_aqc_nvm_checksum *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\n+\tstatus = ice_acquire_nvm(hw, ICE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tcmd = &desc.params.nvm_checksum;\n+\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);\n+\tcmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+\tice_release_nvm(hw);\n+\n+\tif (!status)\n+\t\tif (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)\n+\t\t\tstatus = ICE_ERR_NVM_CHECKSUM;\n+\n+\treturn status;\n+}\n", "prefixes": [ "v5", "09/31" ] }