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GET /api/patches/48838/?format=api
{ "id": 48838, "url": "https://patches.dpdk.org/api/patches/48838/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1544781564-63598-1-git-send-email-lee.daly@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1544781564-63598-1-git-send-email-lee.daly@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1544781564-63598-1-git-send-email-lee.daly@intel.com", "date": "2018-12-14T09:59:22", "name": "[v4,1/3] compress/isal: enable checksum support in driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "84bbf7ede9c1a09083edff6716d5b104e9494353", "submitter": { "id": 825, "url": "https://patches.dpdk.org/api/people/825/?format=api", "name": "Daly, Lee", "email": "lee.daly@intel.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1544781564-63598-1-git-send-email-lee.daly@intel.com/mbox/", "series": [ { "id": 2773, "url": "https://patches.dpdk.org/api/series/2773/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2773", "date": "2018-12-14T09:59:22", "name": "[v4,1/3] compress/isal: enable checksum support in driver", "version": 4, "mbox": "https://patches.dpdk.org/series/2773/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/48838/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/48838/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 1E9D01B9D6;\n\tFri, 14 Dec 2018 10:59:32 +0100 (CET)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id 1A5C21B9CD\n\tfor <dev@dpdk.org>; Fri, 14 Dec 2018 10:59:29 +0100 (CET)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t14 Dec 2018 01:59:29 -0800", "from silpixa00399501.ir.intel.com ([10.237.223.69])\n\tby orsmga003.jf.intel.com with ESMTP; 14 Dec 2018 01:59:27 -0800" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.56,352,1539673200\"; d=\"scan'208\";a=\"110349973\"", "From": "Lee Daly <lee.daly@intel.com>", "To": "akhil.goyal@nxp.com", "Cc": "dev@dpdk.org,\n\tLee Daly <lee.daly@intel.com>", "Date": "Fri, 14 Dec 2018 09:59:22 +0000", "Message-Id": "<1544781564-63598-1-git-send-email-lee.daly@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<11544697752-156863-1-git-send-email-lee.daly@intel.com>", "References": "<11544697752-156863-1-git-send-email-lee.daly@intel.com>", "Subject": "[dpdk-dev] [PATCH v4 1/3] compress/isal: enable checksum support in\n\tdriver", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds checksum support in the ISA-L PMD for both compression\nand decompression.\nCRC32 is supported as well as Adler32.\n\nV2:\nDocumentation Changes\nV3:\nAdded Release note\nV4:\nRemoved dependency on offset unit test\n\nSigned-off-by: Lee Daly <lee.daly@intel.com>\nAcked-by: Fiona Trahe <fiona.trahe@intel.com>\n---\n drivers/compress/isal/isal_compress_pmd.c | 80 ++++++++++++++++++++++-----\n drivers/compress/isal/isal_compress_pmd_ops.c | 4 +-\n 2 files changed, 69 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/compress/isal/isal_compress_pmd.c b/drivers/compress/isal/isal_compress_pmd.c\nindex 9f1e968..b087ed8 100644\n--- a/drivers/compress/isal/isal_compress_pmd.c\n+++ b/drivers/compress/isal/isal_compress_pmd.c\n@@ -16,6 +16,8 @@\n #define RTE_COMP_ISAL_LEVEL_ONE 1\n #define RTE_COMP_ISAL_LEVEL_TWO 2\n #define RTE_COMP_ISAL_LEVEL_THREE 3 /* Optimised for AVX512 & AVX2 only */\n+#define CHKSUM_SZ_CRC 8\n+#define CHKSUM_SZ_ADLER 4\n \n int isal_logtype_driver;\n \n@@ -43,12 +45,6 @@ isal_comp_set_priv_xform_parameters(struct isal_priv_xform *priv_xform,\n \t\t}\n \t\tpriv_xform->compress.algo = RTE_COMP_ALGO_DEFLATE;\n \n-\t\t/* Set private xform checksum - raw deflate by default */\n-\t\tif (xform->compress.chksum != RTE_COMP_CHECKSUM_NONE) {\n-\t\t\tISAL_PMD_LOG(ERR, \"Checksum not supported\\n\");\n-\t\t\treturn -ENOTSUP;\n-\t\t}\n-\n \t\t/* Set private xform window size, 32K supported */\n \t\tif (xform->compress.window_size == RTE_COMP_ISAL_WINDOW_SIZE)\n \t\t\tpriv_xform->compress.window_size =\n@@ -77,6 +73,27 @@ isal_comp_set_priv_xform_parameters(struct isal_priv_xform *priv_xform,\n \t\t\treturn -ENOTSUP;\n \t\t}\n \n+\t\t/* Set private xform checksum */\n+\t\tswitch (xform->compress.chksum) {\n+\t\t/* Raw deflate by default */\n+\t\tcase(RTE_COMP_CHECKSUM_NONE):\n+\t\t\tpriv_xform->compress.chksum = IGZIP_DEFLATE;\n+\t\t\tbreak;\n+\t\tcase(RTE_COMP_CHECKSUM_CRC32):\n+\t\t\tpriv_xform->compress.chksum = IGZIP_GZIP_NO_HDR;\n+\t\t\tbreak;\n+\t\tcase(RTE_COMP_CHECKSUM_ADLER32):\n+\t\t\tpriv_xform->compress.chksum = IGZIP_ZLIB_NO_HDR;\n+\t\t\tbreak;\n+\t\tcase(RTE_COMP_CHECKSUM_CRC32_ADLER32):\n+\t\t\tISAL_PMD_LOG(ERR, \"Combined CRC and ADLER checksum not\"\n+\t\t\t\t\t\" supported\\n\");\n+\t\t\treturn -ENOTSUP;\n+\t\tdefault:\n+\t\t\tISAL_PMD_LOG(ERR, \"Checksum type not supported\\n\");\n+\t\t\treturn -ENOTSUP;\n+\t\t}\n+\n \t\t/* Set private xform level.\n \t\t * Checking compliance with compressdev API, -1 <= level => 9\n \t\t */\n@@ -170,9 +187,24 @@ isal_comp_set_priv_xform_parameters(struct isal_priv_xform *priv_xform,\n \t\t}\n \t\tpriv_xform->decompress.algo = RTE_COMP_ALGO_DEFLATE;\n \n-\t\t/* Set private xform checksum - raw deflate by default */\n-\t\tif (xform->compress.chksum != RTE_COMP_CHECKSUM_NONE) {\n-\t\t\tISAL_PMD_LOG(ERR, \"Checksum not supported\\n\");\n+\t\t/* Set private xform checksum */\n+\t\tswitch (xform->decompress.chksum) {\n+\t\t/* Raw deflate by default */\n+\t\tcase(RTE_COMP_CHECKSUM_NONE):\n+\t\t\tpriv_xform->decompress.chksum = ISAL_DEFLATE;\n+\t\t\tbreak;\n+\t\tcase(RTE_COMP_CHECKSUM_CRC32):\n+\t\t\tpriv_xform->decompress.chksum = ISAL_GZIP_NO_HDR_VER;\n+\t\t\tbreak;\n+\t\tcase(RTE_COMP_CHECKSUM_ADLER32):\n+\t\t\tpriv_xform->decompress.chksum = ISAL_ZLIB_NO_HDR_VER;\n+\t\t\tbreak;\n+\t\tcase(RTE_COMP_CHECKSUM_CRC32_ADLER32):\n+\t\t\tISAL_PMD_LOG(ERR, \"Combined CRC and ADLER checksum not\"\n+\t\t\t\t\t\" supported\\n\");\n+\t\t\treturn -ENOTSUP;\n+\t\tdefault:\n+\t\t\tISAL_PMD_LOG(ERR, \"Checksum type not supported\\n\");\n \t\t\treturn -ENOTSUP;\n \t\t}\n \n@@ -376,6 +408,9 @@ process_isal_deflate(struct rte_comp_op *op, struct isal_comp_qp *qp,\n \n \tqp->stream->level_buf = temp_level_buf;\n \n+\t/* Set Checksum flag */\n+\tqp->stream->gzip_flag = priv_xform->compress.chksum;\n+\n \t/* Stateless operation, input will be consumed in one go */\n \tqp->stream->flush = NO_FLUSH;\n \n@@ -459,8 +494,18 @@ process_isal_deflate(struct rte_comp_op *op, struct isal_comp_qp *qp,\n \t\t\treturn ret;\n \t\t}\n \t}\n+\n \top->consumed = qp->stream->total_in;\n-\top->produced = qp->stream->total_out;\n+\tif (qp->stream->gzip_flag == IGZIP_DEFLATE) {\n+\t\top->produced = qp->stream->total_out;\n+\t} else if (qp->stream->gzip_flag == IGZIP_ZLIB_NO_HDR) {\n+\t\top->produced = qp->stream->total_out - CHKSUM_SZ_ADLER;\n+\t\top->output_chksum = qp->stream->internal_state.crc + 1;\n+\t} else {\n+\t\top->produced = qp->stream->total_out - CHKSUM_SZ_CRC;\n+\t\top->output_chksum = qp->stream->internal_state.crc;\n+\t}\n+\n \tisal_deflate_reset(qp->stream);\n \n \treturn ret;\n@@ -468,7 +513,8 @@ process_isal_deflate(struct rte_comp_op *op, struct isal_comp_qp *qp,\n \n /* Stateless Decompression Function */\n static int\n-process_isal_inflate(struct rte_comp_op *op, struct isal_comp_qp *qp)\n+process_isal_inflate(struct rte_comp_op *op, struct isal_comp_qp *qp,\n+\t\tstruct isal_priv_xform *priv_xform)\n {\n \tint ret = 0;\n \n@@ -477,6 +523,9 @@ process_isal_inflate(struct rte_comp_op *op, struct isal_comp_qp *qp)\n \t/* Initialize decompression state */\n \tisal_inflate_init(qp->state);\n \n+\t/* Set Checksum flag */\n+\tqp->state->crc_flag = priv_xform->decompress.chksum;\n+\n \tif (op->m_src->pkt_len < (op->src.length + op->src.offset)) {\n \t\tISAL_PMD_LOG(ERR, \"Input mbuf(s) not big enough.\\n\");\n \t\top->status = RTE_COMP_OP_STATUS_INVALID_ARGS;\n@@ -531,13 +580,16 @@ process_isal_inflate(struct rte_comp_op *op, struct isal_comp_qp *qp)\n \t\t\treturn -1;\n \t\t}\n \n-\t\tif (ret != ISAL_DECOMP_OK) {\n+\t\tif (ret != ISAL_DECOMP_OK && ret != ISAL_END_INPUT) {\n+\t\t\tISAL_PMD_LOG(ERR, \"Decompression operation failed\\n\");\n \t\t\top->status = RTE_COMP_OP_STATUS_ERROR;\n \t\t\treturn ret;\n \t\t}\n \t\top->consumed = op->src.length - qp->state->avail_in;\n \t}\n-\t\top->produced = qp->state->total_out;\n+\top->produced = qp->state->total_out;\n+\top->output_chksum = qp->state->crc;\n+\n \tisal_inflate_reset(qp->state);\n \n \treturn ret;\n@@ -553,7 +605,7 @@ process_op(struct isal_comp_qp *qp, struct rte_comp_op *op,\n \t\tprocess_isal_deflate(op, qp, priv_xform);\n \t\tbreak;\n \tcase RTE_COMP_DECOMPRESS:\n-\t\tprocess_isal_inflate(op, qp);\n+\t\tprocess_isal_inflate(op, qp, priv_xform);\n \t\tbreak;\n \tdefault:\n \t\tISAL_PMD_LOG(ERR, \"Operation Not Supported\\n\");\ndiff --git a/drivers/compress/isal/isal_compress_pmd_ops.c b/drivers/compress/isal/isal_compress_pmd_ops.c\nindex 41cade8..7b91849 100644\n--- a/drivers/compress/isal/isal_compress_pmd_ops.c\n+++ b/drivers/compress/isal/isal_compress_pmd_ops.c\n@@ -17,7 +17,9 @@ static const struct rte_compressdev_capabilities isal_pmd_capabilities[] = {\n \t\t\t\t\tRTE_COMP_FF_OOP_LB_IN_SGL_OUT |\n \t\t\t\t\tRTE_COMP_FF_SHAREABLE_PRIV_XFORM |\n \t\t\t\t\tRTE_COMP_FF_HUFFMAN_FIXED |\n-\t\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC,\n+\t\t\t\t\tRTE_COMP_FF_HUFFMAN_DYNAMIC |\n+\t\t\t\t\tRTE_COMP_FF_CRC32_CHECKSUM |\n+\t\t\t\t\tRTE_COMP_FF_ADLER32_CHECKSUM,\n \t\t.window_size = {\n \t\t\t.min = 15,\n \t\t\t.max = 15,\n", "prefixes": [ "v4", "1/3" ] }