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GET /api/patches/47391/?format=api
{ "id": 47391, "url": "https://patches.dpdk.org/api/patches/47391/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1540404570-102126-4-git-send-email-yipeng1.wang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1540404570-102126-4-git-send-email-yipeng1.wang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1540404570-102126-4-git-send-email-yipeng1.wang@intel.com", "date": "2018-10-24T18:09:29", "name": "[v2,3/4] test/hash: add readwrite test for ext table", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "edf69322d5ec4d68399d919706450a2413b935d6", "submitter": { "id": 754, "url": "https://patches.dpdk.org/api/people/754/?format=api", "name": "Wang, Yipeng1", "email": "yipeng1.wang@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1540404570-102126-4-git-send-email-yipeng1.wang@intel.com/mbox/", "series": [ { "id": 2078, "url": "https://patches.dpdk.org/api/series/2078/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=2078", "date": "2018-10-24T18:09:26", "name": "hash: improve multiple places", "version": 2, "mbox": "https://patches.dpdk.org/series/2078/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/47391/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/47391/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 652FC4F91;\n\tThu, 25 Oct 2018 03:14:56 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby dpdk.org (Postfix) with ESMTP id ACE504C95\n\tfor <dev@dpdk.org>; Thu, 25 Oct 2018 03:14:48 +0200 (CEST)", "from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t24 Oct 2018 18:14:46 -0700", "from skx-yipeng.jf.intel.com ([10.54.81.175])\n\tby orsmga004.jf.intel.com with ESMTP; 24 Oct 2018 18:14:46 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,422,1534834800\"; d=\"scan'208\";a=\"244139403\"", "From": "Yipeng Wang <yipeng1.wang@intel.com>", "To": "bruce.richardson@intel.com", "Cc": "stephen@networkplumber.org, dev@dpdk.org, yipeng1.wang@intel.com,\n\thonnappa.nagarahalli@arm.com, sameh.gobriel@intel.com", "Date": "Wed, 24 Oct 2018 11:09:29 -0700", "Message-Id": "<1540404570-102126-4-git-send-email-yipeng1.wang@intel.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1540404570-102126-1-git-send-email-yipeng1.wang@intel.com>", "References": "<1540404570-102126-1-git-send-email-yipeng1.wang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 3/4] test/hash: add readwrite test for ext\n\ttable", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This commit improves the readwrite test to consider\nextendable table feature and add more functional tests\nto cover more corner cases.\n\nSigned-off-by: Yipeng Wang <yipeng1.wang@intel.com>\n---\n test/test/test_hash_readwrite.c | 70 ++++++++++++++++++++++++++++++++++-------\n 1 file changed, 58 insertions(+), 12 deletions(-)", "diff": "diff --git a/test/test/test_hash_readwrite.c b/test/test/test_hash_readwrite.c\nindex a8fadd0..13c28e0 100644\n--- a/test/test/test_hash_readwrite.c\n+++ b/test/test/test_hash_readwrite.c\n@@ -21,6 +21,8 @@\n #define TOTAL_ENTRY (16*1024*1024)\n #define TOTAL_INSERT (15*1024*1024)\n \n+#define TOTAL_INSERT_EXT (16*1024*1024)\n+\n #define NUM_TEST 3\n unsigned int core_cnt[NUM_TEST] = {2, 4, 8};\n \n@@ -59,8 +61,10 @@ test_hash_readwrite_worker(__attribute__((unused)) void *arg)\n \tuint64_t i, offset;\n \tuint32_t lcore_id = rte_lcore_id();\n \tuint64_t begin, cycles;\n-\tint ret;\n+\tint *ret;\n \n+\tret = rte_malloc(NULL, sizeof(int) *\n+\t\t\t\ttbl_rw_test_param.num_insert, 0);\n \tfor (i = 0; i < rte_lcore_count(); i++) {\n \t\tif (slave_core_ids[i] == lcore_id)\n \t\t\tbreak;\n@@ -79,13 +83,30 @@ test_hash_readwrite_worker(__attribute__((unused)) void *arg)\n \t\t\t\ttbl_rw_test_param.keys + i) > 0)\n \t\t\tbreak;\n \n-\t\tret = rte_hash_add_key(tbl_rw_test_param.h,\n+\t\tret[i - offset] = rte_hash_add_key(tbl_rw_test_param.h,\n \t\t\t\t tbl_rw_test_param.keys + i);\n-\t\tif (ret < 0)\n+\t\tif (ret[i - offset] < 0)\n+\t\t\tbreak;\n+\n+\t\t/* lookup a random key */\n+\t\tuint32_t rand = rte_rand() % (i + 1 - offset);\n+\n+\t\tif (rte_hash_lookup(tbl_rw_test_param.h,\n+\t\t\t\ttbl_rw_test_param.keys + rand) != ret[rand])\n+\t\t\tbreak;\n+\n+\n+\t\tif (rte_hash_del_key(tbl_rw_test_param.h,\n+\t\t\t\ttbl_rw_test_param.keys + rand) != ret[rand])\n+\t\t\tbreak;\n+\n+\t\tret[rand] = rte_hash_add_key(tbl_rw_test_param.h,\n+\t\t\t\t\ttbl_rw_test_param.keys + rand);\n+\t\tif (ret[rand] < 0)\n \t\t\tbreak;\n \n \t\tif (rte_hash_lookup(tbl_rw_test_param.h,\n-\t\t\t\ttbl_rw_test_param.keys + i) != ret)\n+\t\t\ttbl_rw_test_param.keys + rand) != ret[rand])\n \t\t\tbreak;\n \t}\n \n@@ -100,7 +121,7 @@ test_hash_readwrite_worker(__attribute__((unused)) void *arg)\n }\n \n static int\n-init_params(int use_htm, int use_jhash)\n+init_params(int use_ext, int use_htm, int use_jhash)\n {\n \tunsigned int i;\n \n@@ -129,6 +150,13 @@ init_params(int use_htm, int use_jhash)\n \t\t\tRTE_HASH_EXTRA_FLAGS_RW_CONCURRENCY |\n \t\t\tRTE_HASH_EXTRA_FLAGS_MULTI_WRITER_ADD;\n \n+\tif (use_ext)\n+\t\thash_params.extra_flag |=\n+\t\t\tRTE_HASH_EXTRA_FLAGS_EXT_TABLE;\n+\telse\n+\t\thash_params.extra_flag &=\n+\t\t ~RTE_HASH_EXTRA_FLAGS_EXT_TABLE;\n+\n \thash_params.name = \"tests\";\n \n \thandle = rte_hash_create(&hash_params);\n@@ -167,7 +195,7 @@ init_params(int use_htm, int use_jhash)\n }\n \n static int\n-test_hash_readwrite_functional(int use_htm)\n+test_hash_readwrite_functional(int use_ext, int use_htm)\n {\n \tunsigned int i;\n \tconst void *next_key;\n@@ -178,6 +206,7 @@ test_hash_readwrite_functional(int use_htm)\n \tuint32_t lost_keys = 0;\n \tint use_jhash = 1;\n \tint slave_cnt = rte_lcore_count() - 1;\n+\tuint32_t tot_insert = 0;\n \n \trte_atomic64_init(&gcycles);\n \trte_atomic64_clear(&gcycles);\n@@ -185,11 +214,16 @@ test_hash_readwrite_functional(int use_htm)\n \trte_atomic64_init(&ginsertions);\n \trte_atomic64_clear(&ginsertions);\n \n-\tif (init_params(use_htm, use_jhash) != 0)\n+\tif (init_params(use_ext, use_htm, use_jhash) != 0)\n \t\tgoto err;\n \n+\tif (use_ext)\n+\t\ttot_insert = TOTAL_INSERT_EXT;\n+\telse\n+\t\ttot_insert = TOTAL_INSERT;\n+\n \ttbl_rw_test_param.num_insert =\n-\t\tTOTAL_INSERT / slave_cnt;\n+\t\ttot_insert / slave_cnt;\n \n \ttbl_rw_test_param.rounded_tot_insert =\n \t\ttbl_rw_test_param.num_insert\n@@ -345,7 +379,7 @@ test_hash_readwrite_perf(struct perf *perf_results, int use_htm,\n \trte_atomic64_init(&gwrite_cycles);\n \trte_atomic64_clear(&gwrite_cycles);\n \n-\tif (init_params(use_htm, use_jhash) != 0)\n+\tif (init_params(0, use_htm, use_jhash) != 0)\n \t\tgoto err;\n \n \t/*\n@@ -579,7 +613,7 @@ test_hash_readwrite_main(void)\n \t * than writer threads. This is to timing either reader threads or\n \t * writer threads for performance numbers.\n \t */\n-\tint use_htm, reader_faster;\n+\tint use_htm, use_ext, reader_faster;\n \tunsigned int i = 0, core_id = 0;\n \n \tif (rte_lcore_count() <= 2) {\n@@ -602,7 +636,13 @@ test_hash_readwrite_main(void)\n \t\tprintf(\"Test read-write with Hardware transactional memory\\n\");\n \n \t\tuse_htm = 1;\n-\t\tif (test_hash_readwrite_functional(use_htm) < 0)\n+\t\tuse_ext = 0;\n+\n+\t\tif (test_hash_readwrite_functional(use_ext, use_htm) < 0)\n+\t\t\treturn -1;\n+\n+\t\tuse_ext = 1;\n+\t\tif (test_hash_readwrite_functional(use_ext, use_htm) < 0)\n \t\t\treturn -1;\n \n \t\treader_faster = 1;\n@@ -621,8 +661,14 @@ test_hash_readwrite_main(void)\n \n \tprintf(\"Test read-write without Hardware transactional memory\\n\");\n \tuse_htm = 0;\n-\tif (test_hash_readwrite_functional(use_htm) < 0)\n+\tuse_ext = 0;\n+\tif (test_hash_readwrite_functional(use_ext, use_htm) < 0)\n \t\treturn -1;\n+\n+\tuse_ext = 1;\n+\tif (test_hash_readwrite_functional(use_ext, use_htm) < 0)\n+\t\treturn -1;\n+\n \treader_faster = 1;\n \tif (test_hash_readwrite_perf(&non_htm_results, use_htm,\n \t\t\t\t\t\t\treader_faster) < 0)\n", "prefixes": [ "v2", "3/4" ] }