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GET /api/patches/45592/?format=api
{ "id": 45592, "url": "https://patches.dpdk.org/api/patches/45592/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1538151535-761-2-git-send-email-reshma.pattan@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1538151535-761-2-git-send-email-reshma.pattan@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1538151535-761-2-git-send-email-reshma.pattan@intel.com", "date": "2018-09-28T16:18:55", "name": "examples/ip_pipeline: fix ipv6 address endianness", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6acd78a406f7733177a9fd2444e768fd10634d38", "submitter": { "id": 70, "url": "https://patches.dpdk.org/api/people/70/?format=api", "name": "Pattan, Reshma", "email": "reshma.pattan@intel.com" }, "delegate": { "id": 10018, "url": "https://patches.dpdk.org/api/users/10018/?format=api", "username": "cristian_dumitrescu", "first_name": "Cristian", "last_name": "Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1538151535-761-2-git-send-email-reshma.pattan@intel.com/mbox/", "series": [ { "id": 1578, "url": "https://patches.dpdk.org/api/series/1578/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1578", "date": "2018-09-28T16:18:55", "name": "examples/ip_pipeline: fix ipv6 address endianness", "version": 1, "mbox": "https://patches.dpdk.org/series/1578/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/45592/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/45592/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6273D1B394;\n\tFri, 28 Sep 2018 18:19:09 +0200 (CEST)", "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n\tby dpdk.org (Postfix) with ESMTP id 686811B12F\n\tfor <dev@dpdk.org>; Fri, 28 Sep 2018 18:19:05 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n\tby orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Sep 2018 09:19:04 -0700", "from sivswdev02.ir.intel.com (HELO localhost.localdomain)\n\t([10.237.217.46])\n\tby fmsmga007.fm.intel.com with ESMTP; 28 Sep 2018 09:19:03 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,315,1534834800\"; d=\"scan'208\";a=\"73868267\"", "From": "Reshma Pattan <reshma.pattan@intel.com>", "To": "dev@dpdk.org, cristian.dumitrescu@intel.com, jasvinder.singh@intel.com", "Cc": "Reshma Pattan <reshma.pattan@intel.com>", "Date": "Fri, 28 Sep 2018 17:18:55 +0100", "Message-Id": "<1538151535-761-2-git-send-email-reshma.pattan@intel.com>", "X-Mailer": "git-send-email 1.7.0.7", "In-Reply-To": "<1538151535-761-1-git-send-email-reshma.pattan@intel.com>", "References": "<1538151535-761-1-git-send-email-reshma.pattan@intel.com>", "Subject": "[dpdk-dev] [PATCH] examples/ip_pipeline: fix ipv6 address endianness", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Fix ipv6 endianness from big endian to cpu order.\n\nFixes: a3a95b7d58 (\"examples/ip_pipeline: add table entry commands\")\n\nSigned-off-by: Reshma Pattan <reshma.pattan@intel.com>\n---\n examples/ip_pipeline/thread.c | 40 +++++++++++++++++++++--------------\n 1 file changed, 24 insertions(+), 16 deletions(-)", "diff": "diff --git a/examples/ip_pipeline/thread.c b/examples/ip_pipeline/thread.c\nindex 7fc03332e..b00ea0653 100644\n--- a/examples/ip_pipeline/thread.c\n+++ b/examples/ip_pipeline/thread.c\n@@ -2244,29 +2244,37 @@ match_convert(struct table_rule_match *mh,\n \t\t\t\tml->acl_add.field_value[0].mask_range.u8 =\n \t\t\t\t\tmh->match.acl.proto_mask;\n \n-\t\t\t\tml->acl_add.field_value[1].value.u32 = sa32[0];\n+\t\t\t\tml->acl_add.field_value[1].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(sa32[0]);\n \t\t\t\tml->acl_add.field_value[1].mask_range.u32 =\n \t\t\t\t\tsa32_depth[0];\n-\t\t\t\tml->acl_add.field_value[2].value.u32 = sa32[1];\n+\t\t\t\tml->acl_add.field_value[2].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(sa32[1]);\n \t\t\t\tml->acl_add.field_value[2].mask_range.u32 =\n \t\t\t\t\tsa32_depth[1];\n-\t\t\t\tml->acl_add.field_value[3].value.u32 = sa32[2];\n+\t\t\t\tml->acl_add.field_value[3].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(sa32[2]);\n \t\t\t\tml->acl_add.field_value[3].mask_range.u32 =\n \t\t\t\t\tsa32_depth[2];\n-\t\t\t\tml->acl_add.field_value[4].value.u32 = sa32[3];\n+\t\t\t\tml->acl_add.field_value[4].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(sa32[3]);\n \t\t\t\tml->acl_add.field_value[4].mask_range.u32 =\n \t\t\t\t\tsa32_depth[3];\n \n-\t\t\t\tml->acl_add.field_value[5].value.u32 = da32[0];\n+\t\t\t\tml->acl_add.field_value[5].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(da32[0]);\n \t\t\t\tml->acl_add.field_value[5].mask_range.u32 =\n \t\t\t\t\tda32_depth[0];\n-\t\t\t\tml->acl_add.field_value[6].value.u32 = da32[1];\n+\t\t\t\tml->acl_add.field_value[6].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(da32[1]);\n \t\t\t\tml->acl_add.field_value[6].mask_range.u32 =\n \t\t\t\t\tda32_depth[1];\n-\t\t\t\tml->acl_add.field_value[7].value.u32 = da32[2];\n+\t\t\t\tml->acl_add.field_value[7].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(da32[2]);\n \t\t\t\tml->acl_add.field_value[7].mask_range.u32 =\n \t\t\t\t\tda32_depth[2];\n-\t\t\t\tml->acl_add.field_value[8].value.u32 = da32[3];\n+\t\t\t\tml->acl_add.field_value[8].value.u32 =\n+\t\t\t\t\trte_be_to_cpu_32(da32[3]);\n \t\t\t\tml->acl_add.field_value[8].mask_range.u32 =\n \t\t\t\t\tda32_depth[3];\n \n@@ -2308,36 +2316,36 @@ match_convert(struct table_rule_match *mh,\n \t\t\t\t\tmh->match.acl.proto_mask;\n \n \t\t\t\tml->acl_delete.field_value[1].value.u32 =\n-\t\t\t\t\tsa32[0];\n+\t\t\t\t\trte_be_to_cpu_32(sa32[0]);\n \t\t\t\tml->acl_delete.field_value[1].mask_range.u32 =\n \t\t\t\t\tsa32_depth[0];\n \t\t\t\tml->acl_delete.field_value[2].value.u32 =\n-\t\t\t\t\tsa32[1];\n+\t\t\t\t\trte_be_to_cpu_32(sa32[1]);\n \t\t\t\tml->acl_delete.field_value[2].mask_range.u32 =\n \t\t\t\t\tsa32_depth[1];\n \t\t\t\tml->acl_delete.field_value[3].value.u32 =\n-\t\t\t\t\tsa32[2];\n+\t\t\t\t\trte_be_to_cpu_32(sa32[2]);\n \t\t\t\tml->acl_delete.field_value[3].mask_range.u32 =\n \t\t\t\t\tsa32_depth[2];\n \t\t\t\tml->acl_delete.field_value[4].value.u32 =\n-\t\t\t\t\tsa32[3];\n+\t\t\t\t\trte_be_to_cpu_32(sa32[3]);\n \t\t\t\tml->acl_delete.field_value[4].mask_range.u32 =\n \t\t\t\t\tsa32_depth[3];\n \n \t\t\t\tml->acl_delete.field_value[5].value.u32 =\n-\t\t\t\t\tda32[0];\n+\t\t\t\t\trte_be_to_cpu_32(da32[0]);\n \t\t\t\tml->acl_delete.field_value[5].mask_range.u32 =\n \t\t\t\t\tda32_depth[0];\n \t\t\t\tml->acl_delete.field_value[6].value.u32 =\n-\t\t\t\t\tda32[1];\n+\t\t\t\t\trte_be_to_cpu_32(da32[1]);\n \t\t\t\tml->acl_delete.field_value[6].mask_range.u32 =\n \t\t\t\t\tda32_depth[1];\n \t\t\t\tml->acl_delete.field_value[7].value.u32 =\n-\t\t\t\t\tda32[2];\n+\t\t\t\t\trte_be_to_cpu_32(da32[2]);\n \t\t\t\tml->acl_delete.field_value[7].mask_range.u32 =\n \t\t\t\t\tda32_depth[2];\n \t\t\t\tml->acl_delete.field_value[8].value.u32 =\n-\t\t\t\t\tda32[3];\n+\t\t\t\t\trte_be_to_cpu_32(da32[3]);\n \t\t\t\tml->acl_delete.field_value[8].mask_range.u32 =\n \t\t\t\t\tda32_depth[3];\n \n", "prefixes": [] }