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GET /api/patches/45277/?format=api
{ "id": 45277, "url": "https://patches.dpdk.org/api/patches/45277/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20180925023442.134705-17-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20180925023442.134705-17-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20180925023442.134705-17-qi.z.zhang@intel.com", "date": "2018-09-25T02:34:38", "name": "[16/20] net/i40e/base: add support for carlsville device", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c23f2862ea894abf07b4cbf886b59223956c0123", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20180925023442.134705-17-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 1477, "url": "https://patches.dpdk.org/api/series/1477/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=1477", "date": "2018-09-25T02:34:22", "name": "base code update", "version": 1, "mbox": "https://patches.dpdk.org/series/1477/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/45277/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/45277/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id A77201B3A1;\n\tTue, 25 Sep 2018 04:34:46 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n\tby dpdk.org (Postfix) with ESMTP id 110891B185\n\tfor <dev@dpdk.org>; Tue, 25 Sep 2018 04:34:26 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t24 Sep 2018 19:34:25 -0700", "from dpdk51.sh.intel.com ([10.67.110.190])\n\tby orsmga005.jf.intel.com with ESMTP; 24 Sep 2018 19:34:04 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.54,300,1534834800\"; d=\"scan'208\";a=\"259958548\"", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "beilei.xing@intel.com", "Cc": "dev@dpdk.org, ferruh.yigit@intel.com, helin.zhang@intel.com,\n\tQi Zhang <qi.z.zhang@intel.com>", "Date": "Tue, 25 Sep 2018 10:34:38 +0800", "Message-Id": "<20180925023442.134705-17-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.13.6", "In-Reply-To": "<20180925023442.134705-1-qi.z.zhang@intel.com>", "References": "<20180925023442.134705-1-qi.z.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 16/20] net/i40e/base: add support for carlsville\n\tdevice", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Carlsville Device use 10GBASE-T/1GBASE-T PHY with additional support\nfor 5GBASE-T/2.5GBASE-T.\n\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/i40e/base/i40e_adminq_cmd.h | 59 +++++++++++++++++++++++++++++++++\n drivers/net/i40e/base/i40e_common.c | 10 ++++++\n drivers/net/i40e/base/i40e_devids.h | 3 ++\n drivers/net/i40e/base/i40e_type.h | 8 +++++\n 4 files changed, 80 insertions(+)", "diff": "diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h\nindex 17026ebbf..cd8e3a50a 100644\n--- a/drivers/net/i40e/base/i40e_adminq_cmd.h\n+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h\n@@ -1933,12 +1933,56 @@ enum i40e_aq_phy_type {\n \tI40E_PHY_TYPE_25GBASE_LR\t\t= 0x22,\n \tI40E_PHY_TYPE_25GBASE_AOC\t\t= 0x23,\n \tI40E_PHY_TYPE_25GBASE_ACC\t\t= 0x24,\n+#ifdef CARLSVILLE_HW\n+\tI40E_PHY_TYPE_2_5GBASE_T\t\t= 0x30,\n+\tI40E_PHY_TYPE_5GBASE_T\t\t\t= 0x31,\n+#endif\n \tI40E_PHY_TYPE_MAX,\n \tI40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP\t= 0xFD,\n \tI40E_PHY_TYPE_EMPTY\t\t\t= 0xFE,\n \tI40E_PHY_TYPE_DEFAULT\t\t\t= 0xFF,\n };\n \n+#ifdef CARLSVILLE_HW\n+#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XAUI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XFI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_SFI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XLAUI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_XLPPI) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \\\n+\t\t\t\tBIT_ULL(I40E_PHY_TYPE_5GBASE_T))\n+#else\n #define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \\\n \t\t\t\tBIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \\\n \t\t\t\tBIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \\\n@@ -1975,18 +2019,29 @@ enum i40e_aq_phy_type {\n \t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \\\n \t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \\\n \t\t\t\tBIT_ULL(I40E_PHY_TYPE_25GBASE_ACC))\n+#endif\n \n+#ifdef CARLSVILLE_HW\n+#define I40E_LINK_SPEED_2_5GB_SHIFT\t0x0\n+#endif\n #define I40E_LINK_SPEED_100MB_SHIFT\t0x1\n #define I40E_LINK_SPEED_1000MB_SHIFT\t0x2\n #define I40E_LINK_SPEED_10GB_SHIFT\t0x3\n #define I40E_LINK_SPEED_40GB_SHIFT\t0x4\n #define I40E_LINK_SPEED_20GB_SHIFT\t0x5\n #define I40E_LINK_SPEED_25GB_SHIFT\t0x6\n+#ifdef CARLSVILLE_HW\n+#define I40E_LINK_SPEED_5GB_SHIFT\t0x7\n+#endif\n \n enum i40e_aq_link_speed {\n \tI40E_LINK_SPEED_UNKNOWN\t= 0,\n \tI40E_LINK_SPEED_100MB\t= (1 << I40E_LINK_SPEED_100MB_SHIFT),\n \tI40E_LINK_SPEED_1GB\t= (1 << I40E_LINK_SPEED_1000MB_SHIFT),\n+#ifdef CARLSVILLE_HW\n+\tI40E_LINK_SPEED_2_5GB\t= (1 << I40E_LINK_SPEED_2_5GB_SHIFT),\n+\tI40E_LINK_SPEED_5GB\t= (1 << I40E_LINK_SPEED_5GB_SHIFT),\n+#endif\n \tI40E_LINK_SPEED_10GB\t= (1 << I40E_LINK_SPEED_10GB_SHIFT),\n \tI40E_LINK_SPEED_40GB\t= (1 << I40E_LINK_SPEED_40GB_SHIFT),\n \tI40E_LINK_SPEED_20GB\t= (1 << I40E_LINK_SPEED_20GB_SHIFT),\n@@ -2032,6 +2087,10 @@ struct i40e_aq_get_phy_abilities_resp {\n #define I40E_AQ_PHY_TYPE_EXT_25G_LR\t0x08\n #define I40E_AQ_PHY_TYPE_EXT_25G_AOC\t0x10\n #define I40E_AQ_PHY_TYPE_EXT_25G_ACC\t0x20\n+#ifdef CARLSVILLE_HW\n+#define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T\t0x40\n+#define I40E_AQ_PHY_TYPE_EXT_5GBASE_T\t0x80\n+#endif\n \tu8\tfec_cfg_curr_mod_ext_info;\n #define I40E_AQ_ENABLE_FEC_KR\t\t0x01\n #define I40E_AQ_ENABLE_FEC_RS\t\t0x02\ndiff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c\nindex d0dace06b..f4bd4df9e 100644\n--- a/drivers/net/i40e/base/i40e_common.c\n+++ b/drivers/net/i40e/base/i40e_common.c\n@@ -35,6 +35,9 @@ STATIC enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw)\n \t\tcase I40E_DEV_ID_QSFP_C:\n \t\tcase I40E_DEV_ID_10G_BASE_T:\n \t\tcase I40E_DEV_ID_10G_BASE_T4:\n+#ifdef CARLSVILLE_HW\n+\t\tcase I40E_DEV_ID_10G_BASE_T_BC:\n+#endif\n \t\tcase I40E_DEV_ID_20G_KR2:\n \t\tcase I40E_DEV_ID_20G_KR2_A:\n \t\tcase I40E_DEV_ID_25G_B:\n@@ -1260,6 +1263,10 @@ STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)\n \t\tbreak;\n \tcase I40E_PHY_TYPE_100BASE_TX:\n \tcase I40E_PHY_TYPE_1000BASE_T:\n+#ifdef CARLSVILLE_HW\n+\tcase I40E_PHY_TYPE_2_5GBASE_T:\n+\tcase I40E_PHY_TYPE_5GBASE_T:\n+#endif\n \tcase I40E_PHY_TYPE_10GBASE_T:\n \t\tmedia = I40E_MEDIA_TYPE_BASET;\n \t\tbreak;\n@@ -6682,6 +6689,9 @@ enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,\n \t\tbreak;\n \tcase I40E_DEV_ID_10G_BASE_T:\n \tcase I40E_DEV_ID_10G_BASE_T4:\n+#ifdef CARLSVILLE_HW\n+\tcase I40E_DEV_ID_10G_BASE_T_BC:\n+#endif\n \tcase I40E_DEV_ID_10G_BASE_T_X722:\n \tcase I40E_DEV_ID_25G_B:\n \tcase I40E_DEV_ID_25G_SFP28:\ndiff --git a/drivers/net/i40e/base/i40e_devids.h b/drivers/net/i40e/base/i40e_devids.h\nindex 3cf24721d..8b667c2af 100644\n--- a/drivers/net/i40e/base/i40e_devids.h\n+++ b/drivers/net/i40e/base/i40e_devids.h\n@@ -22,6 +22,9 @@\n #define I40E_DEV_ID_10G_BASE_T4\t\t0x1589\n #define I40E_DEV_ID_25G_B\t\t0x158A\n #define I40E_DEV_ID_25G_SFP28\t\t0x158B\n+#ifdef CARLSVILLE_HW\n+#define I40E_DEV_ID_10G_BASE_T_BC\t0x15FF\n+#endif\n #if defined(INTEGRATED_VF) || defined(VF_DRIVER) || defined(I40E_NDIS_SUPPORT)\n #define I40E_DEV_ID_VF\t\t\t0x154C\n #define I40E_DEV_ID_VF_HV\t\t0x1571\ndiff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h\nindex 19d3596fa..b3621158b 100644\n--- a/drivers/net/i40e/base/i40e_type.h\n+++ b/drivers/net/i40e/base/i40e_type.h\n@@ -329,6 +329,14 @@ struct i40e_phy_info {\n \t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \\\n \t\t\t\t\t I40E_PHY_TYPE_OFFSET)\n+#ifdef CARLSVILLE_HW\n+/* Offset for 2.5G/5G PHY Types value to bit number conversion */\n+#define I40E_PHY_TYPE_OFFSET2 (-10)\n+#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET2)\n+#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T + \\\n+\t\t\t\t\t I40E_PHY_TYPE_OFFSET2)\n+#endif\n #define I40E_HW_CAP_MAX_GPIO\t\t\t30\n #define I40E_HW_CAP_MDIO_PORT_MODE_MDIO\t\t0\n #define I40E_HW_CAP_MDIO_PORT_MODE_I2C\t\t1\n", "prefixes": [ "16/20" ] }